CN110650596B

CN110650596B - Method for manufacturing circuit board

Info

Publication number: CN110650596B
Application number: CN201810679002.6A
Authority: CN
Inventors: 吴建德; 黄重旗
Original assignee: Unimicron Technology Corp
Current assignee: Unimicron Technology Corp
Priority date: 2018-06-27
Filing date: 2018-06-27
Publication date: 2021-07-30
Anticipated expiration: 2038-06-27
Also published as: CN110650596A

Abstract

The invention discloses a manufacturing method of a circuit board, which comprises the following steps: adsorbing a first metal layer on the first electrostatic chuck, wherein the first metal layer has a first surface and a second surface opposite to the first surface, and the first surface contacts the first electrostatic chuck; patterning the first metal layer to expose a portion of the first electrostatic chuck; forming a dielectric layer covering the second surface of the patterned first metal layer and the exposed portion of the first electrostatic chuck; the first electrostatic chuck is removed to expose the first surface of the patterned first metal layer. The method can greatly reduce the production cost.

Description

Method for manufacturing circuit board

Technical Field

The invention relates to the technical field of circuit board processing, in particular to a manufacturing method of a circuit board.

Background

Currently developed fan-out wafer level packaging (FOWLP) technologies can be classified into two broad categories: a chip-first (chip-first) process and a line redistribution layer-first (RDL-first) process. The chip-first process employs a wafer reconstruction process in which a known good wafer (KGD) is picked from an original device wafer and placed on a substrate, and then coated with a molding resin to form a reconstructed wafer. The reconstituted wafer is then temporarily bonded to a carrier board for further processing to produce a circuit redistribution layer (RDL) on the wafer. Because the circuit redistribution layer is processed later, considering that the chip is not hot, only low-temperature processing can be carried out, and at the moment, the types of the selected insulating materials are less, the performance is lower, the damage to the chip in the processing process is also considered, and the method has the disadvantages of improving the yield and reducing the cost.

However, in the RDL-first process, the RDL is built on top of the carrier substrate, coated with a temporary bonding material, and the acceptable wafer is placed on top of the known acceptable RDL, followed by the stamper and die grinding process. Since the chip is not attached during RDL processing, the RDL processing can be performed under a higher temperature condition, such as 230 ℃, which allows various materials to be selected for the RDL-based process, reduces the probability of chip damage during the processing, increases yield and reduces cost. In addition, how to improve the flatness of the RDL-preferred circuit board makes the RDL-preferred circuit board applicable to high-frequency high-speed communication transmission is another major problem of the RDL-preferred process.

Disclosure of Invention

In view of the above, an object of the present invention is to provide a method for manufacturing a circuit board that can solve the above problems.

In order to achieve the above object, an object of the present invention is to provide a method for manufacturing a wiring board, the method comprising the steps of: first, a first metal layer is adsorbed on a first electrostatic chuck, wherein the first metal layer has a first surface and a second surface opposite to the first surface, and the first surface contacts the first electrostatic chuck. Then, the first metal layer is patterned to expose a portion of the first electrostatic chuck. Then, a dielectric layer is formed to cover the second surface of the patterned first metal layer and the exposed part of the first electrostatic chuck. The first electrostatic chuck is removed to expose the first surface of the patterned first metal layer.

According to an embodiment of the present invention, the step of patterning the first metal layer further includes the steps of: forming a photoresist layer on the second surface of the first metal layer; exposing and developing the photoresist layer to form a patterned photoresist layer; etching the first metal layer by using the patterned photoresist layer as a mask; and removing the patterned photoresist layer.

According to an embodiment of the present invention, the thickness of the first metal layer is 0.4 to 70 μm.

According to an embodiment of the present invention, the roughness of the first surface of the first metal layer is 0.01 to 5 micrometers, and the roughness of the second surface is 0.01 to 5 micrometers.

According to one embodiment of the present invention, the Dielectric Layer is a glass fiber cloth (pregpregpreg), Ajinomoto structured-up Film (ABF) or a Photo-electrically-sensitive Dielectric Layer (Photo-Imageable Dielectric Layer).

According to an embodiment of the present invention, the step of forming the dielectric layer further includes: forming at least one blind hole from the upper surface of the dielectric layer to the second surface of the patterned first metal layer to expose a portion of the second surface of the patterned first metal layer; and filling the blind holes with a conductive material to form conductive blind holes.

According to an embodiment of the present invention, before the step of filling the blind hole, the method further includes: a seed layer is formed to cover the inner wall of the blind hole and the exposed part of the second surface of the patterned first metal layer.

According to an embodiment of the present invention, the step of forming the conductive blind via further includes: the upper surface of the dielectric layer and the surface of the conductive blind via are planarized such that the upper surface of the dielectric layer and the surface of the conductive blind via are substantially coplanar.

According to an embodiment of the present invention, the step of planarizing further includes: and forming a patterned second metal layer on the upper surface of the dielectric layer and the surface of the conductive blind hole, wherein the patterned second metal layer has a third surface and a fourth surface opposite to the third surface, and the third surface contacts the upper surface of the dielectric layer and the surface of the conductive blind hole.

According to an embodiment of the present invention, the step of forming the patterned second metal layer includes: pressing a second metal layer on the upper surface of the dielectric layer and the surface of the conductive blind hole, wherein the second metal layer is provided with a third surface and a fourth surface opposite to the third surface, and the third surface is contacted with the upper surface of the dielectric layer and the surface of the conductive blind hole; and patterning the second metal layer.

According to one embodiment of the present invention, the step of forming the patterned second metal layer comprises: adsorbing a second metal layer on the second electrostatic chuck, wherein the second metal layer has a third surface and a fourth surface opposite to the third surface, and the fourth surface contacts the second electrostatic chuck; patterning the second metal layer to expose a portion of the second electrostatic chuck; pressing the fourth surface of the patterned second metal layer onto the surface of the dielectric layer so that the patterned second metal layer is positioned between the first electrostatic chuck and the second electrostatic chuck; and removing the second electrostatic chuck to expose the fourth surface of the patterned second metal layer.

Drawings

Fig. 1 is a flowchart of a method of manufacturing a wiring board of an embodiment of the present invention;

fig. 2, fig. 4A to fig. 4D, and fig. 5 to fig. 16 are schematic cross-sectional views of the respective process stages in the method for manufacturing a wiring board according to the embodiments of the present invention.

Fig. 3 is a schematic view illustrating the adsorption principle of the electrostatic chuck of the present invention.

[ notation ] to show

210: first electrostatic chuck

210 a: suction surface of the first electrostatic chuck 210

210 p: a portion of the first electrostatic chuck 210 exposed

212: upper insulating layer

214: a first electrode

216: second electrode

218: lower insulating layer

220: a first metal layer

222: first surface

224p of the formula: a portion of the second surface 224 exposed

224: second surface

230: dielectric layer

232: upper surface of

310: the photoresist layer

320: patterning photoresist layer

330: patterning the first metal layer

402: seed layer

410: blind hole

420: conductive blind hole

422: surface of

510: second metal layer

512: third surface

514: the fourth surface

520: patterning the second metal layer

610: second electrostatic chuck

610 p: an exposed portion of the second electrostatic chuck 610

E: power line

Detailed Description

In order to make the description of the present invention more complete and complete, the following description is given for illustrative purposes with respect to embodiments and examples of the present invention; it is not intended to be the only form in which the embodiments of the invention may be practiced or utilized. The embodiments disclosed below may be combined with or substituted for one another as desired, or additional embodiments may be added to the embodiments, without further recitation or description.

In the following description, numerous specific details are set forth to provide a thorough understanding of the following embodiments. However, embodiments of the invention may be practiced without these specific details. In other instances, well-known structures and devices are shown schematically in order to simplify the drawing.

An object of the present invention is to provide a method of manufacturing a wiring board, by which a carrier substrate is not required to be removed by an expensive laser apparatus and thus manufacturing cost can be reduced. Fig. 1 is a flowchart of a method for manufacturing a wiring board according to an embodiment of the present invention. Fig. 2, 4A to 4D, and 5 to 16 are schematic cross-sectional views of respective process stages in a method of manufacturing a wiring board according to embodiments of the present invention. As shown in fig. 1, the method 10 includes step S12, step S14, step S16, and step S18.

In step S12, a first metal layer 220 is adsorbed on a first Electrostatic Chuck (ESC) 210, as shown in fig. 2. Specifically, the first metal layer 220 has a first surface 222 and a second surface 224 opposite to the first surface 222, and the first surface 222 contacts the first electrostatic chuck 210. In various embodiments, the first metal layer 220 may be, for example, an ultra-thin copper foil (e.g., having a thickness of about 0.4 to 10 micrometers (0.4 to 10um)), or a general copper foil (e.g., having a thickness of 18 to 70 micrometers (18 to 70um)), but is not limited thereto. In some embodiments, the roughness of the first surface 222 of the first metal layer 220 is, for example, 0.01um to 5um, and the roughness of the second surface 224 is, for example, 0.01um to 5um, but is not limited thereto. It is noted that the roughness of the first surface 222 may be less than, about equal to, or greater than the roughness of the second surface 224. The roughness of the first surface 222 and the second surface 224 can be adjusted according to the product requirement design. The roughness of the first surface 222 and the second surface 224 of the first metal layer 220 can be relatively small, for example, 0.01 to 0.5 micrometers, which can meet the impedance matching requirement of high frequency and high speed lines in signal transmission, and reduce the loss of signal transmission.

It will be understood by those skilled in the art that the first electrostatic chuck 210 includes a mono-pole type electrostatic chuck and a bi-pole type electrostatic chuck. In this embodiment, a bipolar electrostatic chuck will be described as an example. Fig. 3 is a schematic view illustrating the adsorption principle of the electrostatic chuck of the present invention. As shown in fig. 3, the internal structure of the first electrostatic chuck 210 includes a plurality of pairs of first electrodes 214 and second electrodes 216 interposed between an upper insulating layer 212 and a lower insulating layer 218, and the first electrodes 214 and the second electrodes 216 are alternately arranged. The first electrode 214 is connected to the positive side of a Direct Current (DC) power source or a Radio Frequency (RF) power source and the second electrode 216 is connected to the negative side of the DC power source or the RF power source, respectively, such that the dielectric of the upper insulating layer 212 is induced to be polarized, thereby forming an electric field line E as shown in fig. 3 near the suction surface 210a of the first electrostatic chuck 210. Accordingly, the electrostatic chuck 210 may attract the first metal layer 220 through dipole-dipole force generated near the attraction face 210 a. It is considered that, if the voltage application is subsequently stopped, the electric flux lines E disappear, and the electric charges accumulated in the upper insulating layer 212 flow into the ground side via the

electrodes

214 and 216, or disappear together with the electric charges of the opposite polarity. In other words, the first electrostatic chuck 210 and the first metal layer 220 may be separated from each other when the voltage application is stopped.

In step S14, the first metal layer 220 is patterned to expose a portion 210p of the first electrostatic chuck 210. Fig. 4A to 4D are schematic cross-sectional views illustrating the implementation of step S14 according to an embodiment of the present invention. As shown in fig. 4A, a photoresist layer 310 is formed on the second surface 224 of the first metal layer 220. In various embodiments, the photoresist layer 310 may be, for example, a positive photoresist or a negative photoresist, and covers the first metal layer 220 by vacuum lamination, coating, spin coating, or other suitable methods. Next, as shown in fig. 4B, the photoresist layer 310 is exposed and developed to form a patterned photoresist layer 320 and expose a portion of the first metal layer 220. Then, as shown in fig. 4C, the first metal layer 220 is etched using the patterned photoresist layer 320 as a mask to form a patterned first metal layer 330. Then, as shown in fig. 4D, a removal process of the patterned photoresist layer 320 is performed to expose the patterned first metal layer 330. It should be emphasized that, in the embodiment where the first metal layer 220 is an ultra-thin copper foil (e.g., 0.4-10um thick), the Aspect Ratio (Aspect Ratio) of the line height and the line width of the circuit may also be close to 1: if the anisotropic dry etching process is used to etch the first metal layer 220, the aspect ratio of the line height and the line width of the circuit may even approach 5: 1, or higher, may be up to 10: 1. The ratio of the line width to the line distance of the finest line manufactured by the steps can be close to 1: 1. therefore, the line width and the line distance can reach the specification of an ultra-fine line of 0.4um/0.4um and even the specification of a thinner line.

In step S16, a dielectric layer 230 is formed covering the first surface 222 of the patterned first metal layer 330 and the exposed portion 210p of the first electrostatic chuck 210, as shown in fig. 5. In some embodiments, the method of forming the dielectric layer 230 may be, for example, Lamination (deposition), coating, spin coating, or other suitable process. In various embodiments, the material of the Dielectric layer 230 may include glass fiber cloth (pregpregpreg), Ajinomoto fabric-up Film (ABF), Photo-Dielectric layer (Photo-electrically-Dielectric layer), or resin. For example, the resin may be a phenolic resin, a polyimide resin, an epoxy resin, or polytetrafluoroethylene.

In step S18, the first electrostatic chuck 210 is removed, as shown in fig. 6. Specifically, the first electrostatic chuck 210 is removed by stopping the voltage application as described above, so that the first electrostatic chuck 210 can be directly removed, thereby forming a single-sided wiring board (single-sided wiring board). Since the surface of the first electrostatic chuck 210 is very flat, the roughness of the first surface 222 of the patterned first metal layer 330 can be relatively small, such as 0.01 to 0.5 microns, which can meet the impedance matching requirement of high-frequency and high-speed lines in signal transmission and reduce the loss of signal transmission.

In addition, the invention also provides a method for manufacturing a double-sided wiring board (double-sided wiring board) and a multilayer wiring board (multilayer wiring board).

A method of manufacturing a double-sided wiring board according to an embodiment of the present invention will be described below. With continued reference to fig. 7, after step S16, at least one blind via 410 may be formed from the upper surface 232 of the dielectric layer 230 through to the second surface 224 of the patterned first metal layer 330 to expose a portion 224p of the second surface 224 of the patterned first metal layer 330. In some embodiments, the blind via 410 can be formed by, but is not limited to, laser drilling, chemical drilling, or mechanical drilling from the upper surface 232 of the dielectric layer 230 to the second surface 224 of the patterned first metal layer 330. Next, as shown in fig. 8, the blind via 410 is filled with a conductive material to form a conductive blind via 420. In various embodiments, the conductive material may be, for example, copper or other conductive materials, such as silver, nickel, tin, aluminum, or the like, but is not limited thereto. In other embodiments, the seed layer 402 may be formed to cover the inner walls of the blind via 410 and the exposed portion 224p of the second surface 224 of the patterned first metal layer 330 before the step of filling the blind via 410. The seed layer 402 may be a single layer or a multi-layer structure composed of sublayers of different materials, such as a metal layer including a titanium layer and a copper layer on the titanium layer, or a palladium-plated copper layer, but not limited thereto. The seed layer 402 may be formed by, but is not limited to, physical means such as sputtered titanium copper or chemical means such as a palladium copper plated layer. In various embodiments, the upper surface 232 of the dielectric layer 230 and the surface 422 of the conductive blind via 420 may be planarized after the step of forming the conductive blind via 420, and the seed layer 402 on the upper surface 232 of the dielectric layer 230 may be simultaneously removed, such that the upper surface 232 of the dielectric layer 230 and the surface 422 of the conductive blind via 420 are substantially coplanar, thereby facilitating the bonding of the metal layers for subsequent build-up. The planarization process may be, for example, chemical mechanical polishing, mechanical brushing, planarization chemical etching, polishing process, electrolytic etching or electropolishing etching, etc., or a combination thereof, but is not limited thereto.

Continuing with fig. 9, the patterned second metal layer 520 may be formed on the upper surface of the dielectric layer 230 after the planarization step. The patterned second metal layer 520 is formed, for example, by pressing the second metal layer 510 on the upper surface 232 of the dielectric layer 230 and the surface 422 of the conductive via 420. Specifically, the second metal layer 510 has a third surface 512 and a fourth surface 514 opposite to the third surface 512, and the third surface 512 contacts the upper surface 232 of the dielectric layer 230 and the surface 422 of the conductive blind via 420. In addition, during the lamination process, the second metal layer 510 can be properly heated to enhance the bonding with the dielectric layer 230 and the conductive via 420. In various embodiments, the second metal layer 510 may be, for example, an ultra-thin copper foil (e.g., having a thickness of 0.4-10um), or a general copper foil (e.g., having a thickness of 18-70um), but is not limited thereto. In some embodiments, the roughness of the third surface 512 of the second metal layer 510 is, for example, 0.01um to 5um, and the roughness of the fourth surface 514 is, for example, 0.01um to 5 um. Then, referring to fig. 10, the second metal layer 510 is patterned to form a patterned second metal layer 520, and then the first electrostatic chuck 210 is removed, thereby completing the manufacture of the dual-sided circuit board. It is understood that the detailed process flow of the patterning process can refer to the related descriptions in fig. 4A to fig. 4D, and the detailed description thereof is omitted here.

It is noted that the roughness of the third surface 512 may be less than, about equal to, or greater than the roughness of the fourth surface 514. The roughness of the third surface 512 and the fourth surface 514 can be adjusted according to the product requirement design. The roughness of the third surface 512 and the fourth surface 514 of the second metal layer 510 can be relatively small, for example, 0.01 to 0.5 micrometers, which can meet the impedance matching requirement of high frequency and high speed lines in signal transmission, and reduce the loss of signal transmission. When the circuit board is applied to a high-frequency high-speed wireless communication product, in an embodiment, for example, the first metal layer 330 may be inverted, so that the roughness of the second surface 224 is smaller than that of the first surface 222, and in addition, the roughness of the third surface 512 of the second metal layer 510 is smaller than that of the fourth surface 514, so that the second surface 224 and the third surface 512 with small roughness are opposite to each other with the dielectric layer 230 interposed therebetween, which is beneficial to improving the Skin Effect (Skin Effect) generated in response to a high-frequency signal and reducing the attenuation and loss of the high-frequency signal. The above examples are for illustration, but not limited thereto.

A method of manufacturing a double-sided wiring board according to another embodiment of the present invention is briefly described below. Referring to fig. 11, after step S16, a second metal layer 510 may be additionally adsorbed on the second electrostatic chuck 610. Specifically, the second metal layer 510 has a third surface 512 and a fourth surface 514 opposite to the third surface 512, and the third surface 512 contacts the second electrostatic chuck 610. In various embodiments, the second metal layer 510 may be, for example, an ultra-thin copper foil (e.g., having a thickness of 0.4-10um) or a general copper foil (e.g., having a thickness of 18-70um), but is not limited thereto. In some embodiments, the roughness of the third surface 512 of the second metal layer 510 is 0.01um to 5um, and the roughness of the fourth surface 514 is 0.01um to 5 um. It is noted that the roughness of the third surface 512 may be less than, about equal to, or greater than the roughness of the fourth surface 514. The second electrostatic chuck 610 may be similar to the first electrostatic chuck 210, and will not be described herein. Next, as shown in fig. 12, the second metal layer 510 is patterned to form a patterned second metal layer 520 and expose a portion 610p of the second electrostatic chuck 610. It is understood that the detailed process flow of the patterning process can refer to the related descriptions in fig. 4A to fig. 4D, and the detailed description thereof is omitted here.

Then, referring to fig. 13, the third surface 512 of the patterned second metal layer 520 is pressed onto the structure shown in fig. 8. More specifically, the structure shown in fig. 12 is inverted such that the third surface 512 of the patterned second metal layer 520 is pressed down onto the surface 232 of the dielectric layer 230, such that the patterned second metal layer 520 is located between the dielectric layer 230 (and the conductive vias 420) and the second electrostatic chuck 610. It is understood that each electrostatic chuck has an alignment mark (not shown), so there is no concern about poor alignment. Then, as shown in fig. 14, the second electrostatic chuck 610 is removed to expose the fourth surface 514 of the patterned second metal layer 520, and the first electrostatic chuck 210 is removed to expose the first surface 222 of the patterned first metal layer 330, thereby completing the manufacture of the double-sided circuit board. The first electrostatic chuck 210 may be removed simultaneously with the second electrostatic chuck 610, or may be removed sequentially.

Methods of fabricating multilayer wiring boards according to various embodiments of the present invention will be described below. Referring to fig. 15, in an embodiment, after the steps shown in fig. 10 are completed, the steps shown in fig. 5 and fig. 7 to 10 are repeated to manufacture the multilayer circuit board. Alternatively, in another embodiment, after the step shown in fig. 14 is completed, the steps shown in fig. 5, 7, 8, and 11 to 14 may be repeated to realize the fabrication of the multilayer circuit board. After the desired multilayer circuit board is completed, the first electrostatic chuck 210 is removed by stopping the application of the voltage, as shown in fig. 16. It should be noted that, only 3 circuit layers are shown in fig. 15 and 16, but the present invention is not limited thereto, and 4 or more circuit layers can be fabricated according to different wiring designs.

Contrary to the prior art RDL manufacturing method that requires expensive laser equipment to remove the carrier substrate, the present invention is directed to a method for manufacturing a circuit board, which can easily adsorb and separate the metal layer by using an electrostatic chuck, thereby greatly reducing the cost and improving the production efficiency. Moreover, the manufacturing method of the circuit board can directly form the ultra-fine circuit (for example, the line width is approximate to the line distance) without using expensive precise electroplating equipment or using complicated improved semi-additive process (MSAP) so as to achieve the effect of simplifying the process. In addition, in the manufacturing method of the circuit board, the circuit layer can be manufactured by using the metal layer with low roughness, and the surface treatment is not carried out on the circuit layer, so that the signal loss is not easy to generate in the process of high-frequency signal conduction.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A method of manufacturing a wiring board, comprising:

adsorbing a first metal layer on a first electrostatic chuck, wherein the first metal layer has a first surface and a second surface opposite to the first surface, and the first surface contacts the first electrostatic chuck;

patterning the first metal layer to expose a portion of the first electrostatic chuck;

forming a dielectric layer covering the second surface of the patterned first metal layer and the exposed portion of the first electrostatic chuck; and

removing the first electrostatic chuck to expose the first surface of the patterned first metal layer.

2. The method of claim 1, wherein the step of patterning the first metal layer to expose a portion of the first electrostatic chuck comprises:

forming a photoresist layer on the second surface of the first metal layer;

exposing and developing the photoresist layer to form a patterned photoresist layer;

etching the first metal layer by using the patterned photoresist layer as a shield; and

and removing the patterned photoresist layer.

3. The method of manufacturing a wiring board according to claim 1, wherein the thickness of the first metal layer is 0.4 to 70 μm.

4. The method of manufacturing a wiring board according to claim 3, wherein the roughness of the first surface of the first metal layer is 0.01 to 5 micrometers, and the roughness of the second surface is 0.01 to 5 micrometers.

5. The method of manufacturing a wiring board according to claim 1, wherein the dielectric layer is a glass cloth, an ABF or a photosensitive dielectric layer.

6. The method of claim 1, further comprising, after the step of forming the dielectric layer covering the second surface of the patterned first metal layer and the exposed portion of the first electrostatic chuck:

forming at least one blind via from an upper surface of the dielectric layer through to the second surface of the patterned first metal layer to expose a portion of the second surface of the patterned first metal layer; and

and filling the blind holes with a conductive material to form conductive blind holes.

7. The method of manufacturing a wiring board according to claim 6, wherein before the step of filling the blind via with a conductive material to form a conductive blind via, further comprising:

forming a seed layer covering an inner wall of the blind via and the portion of the second surface of the patterned first metal layer exposed.

8. The method of manufacturing a wiring board according to claim 6, wherein after the step of filling the blind via with a conductive material to form a conductive blind via, further comprising:

planarizing the upper surface of the dielectric layer and a surface of the conductive blind via such that the upper surface of the dielectric layer and the surface of the conductive blind via are substantially coplanar.

9. The method of claim 8, wherein the step of planarizing the top surface of the dielectric layer and the surface of the conductive via such that the top surface of the dielectric layer and the surface of the conductive via are substantially coplanar further comprises:

forming a patterned second metal layer on the upper surface of the dielectric layer and the surface of the conductive blind via, wherein the patterned second metal layer has a third surface and a fourth surface opposite the third surface, and the third surface contacts the upper surface of the dielectric layer and the surface of the conductive blind via.

10. The method of claim 9, wherein the step of forming a patterned second metal layer on the top surface of the dielectric layer and the surface of the conductive blind via comprises:

pressing a second metal layer on the upper surface of the dielectric layer and the surface of the conductive blind via, wherein the second metal layer has a third surface and a fourth surface opposite to the third surface, and the third surface contacts the upper surface of the dielectric layer and the surface of the conductive blind via; and

and patterning the second metal layer.

11. The method of claim 9, wherein the step of forming a patterned second metal layer on the top surface of the dielectric layer and the surface of the conductive blind via comprises:

adsorbing a second metal layer on a second electrostatic chuck, wherein the second metal layer has a third surface and a fourth surface opposite the third surface, and the fourth surface contacts the second electrostatic chuck;

patterning the second metal layer to expose a portion of the second electrostatic chuck;

pressing the third surface of the patterned second metal layer onto the surface of the dielectric layer such that the patterned second metal layer is between the first and second electrostatic chucks; and

removing the second electrostatic chuck to expose the fourth surface of the patterned second metal layer.