CN110635700B - Power converter, method for controlling a power converter and primary controller - Google Patents

Power converter, method for controlling a power converter and primary controller Download PDF

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Publication number
CN110635700B
CN110635700B CN201910532877.8A CN201910532877A CN110635700B CN 110635700 B CN110635700 B CN 110635700B CN 201910532877 A CN201910532877 A CN 201910532877A CN 110635700 B CN110635700 B CN 110635700B
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input
voltage
current
output
terminal
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CN201910532877.8A
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CN110635700A (en
Inventor
P·帕皮卡
M·波泽姆尼
M·凯哈
J·托马内克
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Semiconductor Components Industries LLC
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Semiconductor Components Industries LLC
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Priority claimed from US16/366,810 external-priority patent/US10622901B2/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention provides a power converter, a method for controlling the power converter and a primary controller. An exemplary power converter includes: a primary controller having a control voltage terminal for receiving power; and a monitor terminal electrically coupled to the input sense node, wherein the input voltage periodically varies below a first starting threshold voltage to define a valley. The power converter includes a first current source configured to drive a first current from the monitor terminal to the control voltage terminal in response to the input voltage being less than the first starting threshold voltage. A delay timer delays driving the first current such that a center of a power supply time interval is centered within a valley.

Description

Power converter, method for controlling a power converter and primary controller
Cross Reference to Related Applications
The present application claims the benefit of U.S. provisional application serial No. 62/689,752, entitled "Circuits, systems, and Methods for Low Loss" (for low loss Circuits, systems, and methods) filed on 25, 6, 2018. This provisional application is incorporated by reference as if reproduced fully below.
Technical Field
The present application relates to the technical field of power converters, and in particular to self-powering of power for a controller of a power converter.
Background
A primary controller used within a power converter, such as a Switched Mode Power Supply (SMPS), functions using a low voltage power supply. The low voltage power may be supplied to a control voltage terminal of the primary controller from an auxiliary power source, which may include an auxiliary winding of a transformer and a rectifier diode. The primary controller may further include a monitoring terminal configured to monitor a voltage of Alternating Current (AC) power supplied to the primary controller. In some cases, the auxiliary power supply may not be able to supply enough power to maintain the control voltage terminal at a voltage sufficient to enable the primary controller to function.
Disclosure of Invention
One exemplary embodiment is a method of operating a power converter, comprising: monitoring an input voltage on a monitor terminal of the primary controller, the input voltage being a rectified AC signal periodically varying below a first starting threshold voltage to define a valley; driving a first current from the monitor terminal to a control voltage terminal of the primary controller in response to the input voltage being less than a first starting threshold voltage; and charging a control voltage capacitor coupled to the control voltage terminal with the first current.
The exemplary method may further comprise: driving a second current from the monitor terminal to the control voltage terminal in response to the input voltage being less than a second start threshold voltage that is higher than the start threshold voltage; and wherein the second current is less than the first current.
The example method may further include delaying driving the first current from the monitor terminal to the control voltage terminal for a delay time after the input voltage drops below the first starting threshold voltage. Delaying driving the first current from the monitor terminal to the control voltage terminal may further include: determining a valley time as a length of time from when the input voltage drops below a first starting threshold voltage until the input voltage is less than a reference voltage; recording an amount of time to charge the control voltage capacitor with the first current as a supply time interval; and calculating the delay time as the valley time minus half of the power supply time interval. The example method may further include adjusting the delay time in response to the first current being driven for a time longer than a predetermined time. The exemplary method may further comprise: determining that the primary controller is in a high consumption mode; and adjusting the delay time in response to the primary controller being in the high consumption mode. The exemplary method may further comprise: detecting that the amplitude variation of the input voltage exceeds a predetermined amount for a predetermined period of time; and adjusting the delay time in response to a change in the amplitude of the input voltage. The exemplary method may further comprise: recording an amount of time to charge the control voltage capacitor with the first current as a supply time interval; and adjusting the delay time in response to the input voltage being greater than the reference voltage throughout the power supply time interval. Adjusting the delay time may also include increasing the delay time by the power-on interval.
Another exemplary embodiment is a power converter. The power converter includes a primary side including: an AC input including a line terminal and a neutral terminal for receiving AC input power; an input rectifier for providing rectified AC power to an input sense node, wherein the rectified AC power has an input voltage that periodically varies below a first starting threshold voltage to define a valley; a primary winding of a transformer; an auxiliary winding of the transformer; and a primary controller defining a control voltage terminal coupled to the control voltage capacitor and to the auxiliary winding of the transformer, and a monitor terminal coupled to the input sense node. The primary controller is configured to: driving a first current from the monitor terminal to the control voltage terminal in response to the input voltage being less than a first starting threshold voltage; and charging the control voltage capacitor with the first current.
The primary controller in the exemplary power converter is further configured to drive a second current from the monitor terminal to the control voltage terminal in response to the input voltage being less than the second starting threshold voltage, wherein the second current is less than the first current.
The exemplary power converter may further include a delay timer configured to delay driving the first current from the monitor terminal to the control voltage terminal for a delay time after the input voltage drops below the first start threshold voltage. The exemplary power converter may further include: a valley timer configured to determine a valley time as a length of time from when the input voltage drops below a first starting threshold voltage until the input voltage is less than a reference voltage; a switching power supply timer configured to record an amount of time to charge the control voltage capacitor with the first current as a supply time interval; and wherein the delay time is half the valley time minus the power-on time interval. The delay time may be adjusted in response to at least one of: the first current is driven for a time longer than a predetermined time, or the primary controller is in a high consumption mode, or the magnitude of the input voltage varies by more than a predetermined amount during a predetermined period of time, or the input voltage is greater than the reference voltage during the entire supply time interval when the control voltage capacitor is charged by the first current.
Another exemplary embodiment is a primary controller for a power converter, comprising: a control voltage terminal; monitoring the terminal; and a supplementary power controller. The supplementary power controller may include: a monitor circuit defining a monitor input coupled to the monitor terminal and a first control output, the monitor circuit configured to measure an input voltage on the monitor terminal and validate the first control output when the input voltage is less than a first start threshold voltage; and a first current source defining a first current input, a first current output, and a first control input, the first current input coupled to the monitor terminal, the first current output coupled to the control voltage terminal, and the first control input coupled to the first control output, the first current source configured to drive a first current from the monitor terminal to the control voltage terminal in response to an assertion of the first control input.
The supplemental power controller of the example primary controller may further comprise: a monitor circuit defining a second control output, the monitor circuit configured to validate the second control output when the input voltage is less than a second onset threshold voltage that is higher than the onset threshold voltage; and a second current source defining a second current input coupled to the monitor terminal, a second current output coupled to the control voltage terminal, and a second control input coupled to the second control output, the second current source configured to drive a second current from the monitor terminal to the control voltage terminal in response to an assertion of the second control input, wherein the second current is less than the first current.
The supplemental power controller of the example primary controller may further comprise: a delay timer configured to delay the assertion of the first control input of the first current source for a delay time after the assertion of the first control output by the monitoring circuit.
The supplemental power controller of the example primary controller may further comprise: a control voltage sensor defining a sensor input and a sensor output, the sensor input coupled to a control voltage terminal, the control voltage sensor configured to measure a control voltage on the control voltage terminal and validate the sensor output when the control voltage is greater than a first control voltage threshold; a monitor circuit defining a third control output, the monitor circuit configured to validate the third control output when the input voltage is less than the reference voltage; a valley timer configured to determine a valley time as a length of time from the monitor circuit validating the first control output until the monitor circuit validating the third control output; a switching power supply timer configured to record a power supply time interval from an assertion of a first control input of the first current source until a sensor output of the control voltage sensor; and wherein the delay time is half the valley time minus the power-on time interval.
The supplemental power controller of the example primary controller may further comprise: a delay time adjuster configured to change a length of delay time between assertion of the first control input of the first current source after assertion of the first control output by the monitoring circuit. The primary controller may further comprise at least one of: a timeout comparator defining a timeout output, the timeout comparator configured to validate the timeout output in response to the power-on interval being greater than a predetermined on-time; a consumption monitor defining a consumption output, the consumption monitor configured to validate the consumption output when the primary controller is in a high consumption mode; or an input amplitude sensor defining an amplitude variation output, the input amplitude sensor being configured to validate the amplitude variation output in response to the amplitude of the input voltage varying more than a predetermined amount over a predetermined period of time; a valley absence sensor defining a valley absence output, the valley absence sensor being configured to validate the valley absence output in response to a power supply time interval passing from a validation of the first control input of the first current source until a sensor output of the control voltage sensor, and the third control output not being present; and wherein the delay time adjuster is configured to change the length of the delay time in response to at least one of: timeout output, or consumption output, or amplitude change output, or no output in the valley.
Drawings
For a detailed description of exemplary embodiments, reference will now be made to the accompanying drawings in which:
FIG. 1 shows a schematic diagram of a power converter in accordance with at least some embodiments;
FIG. 2 shows a block diagram of a primary controller in accordance with at least some embodiments;
FIG. 3 illustrates a partial schematic, partial block diagram of a primary controller in accordance with at least some embodiments;
FIG. 4 shows a plot of voltage over time; and
FIG. 5 shows a timing diagram in accordance with at least some embodiments;
FIG. 6 shows a timing diagram in accordance with at least some embodiments;
FIG. 7 shows a timing diagram in accordance with at least some embodiments; and
Fig. 8 illustrates method steps in accordance with at least some embodiments.
Definition of the definition
Various terms are used to refer to particular system components. Different companies may refer to a component by different names-this document is not intended to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus, such terms should be interpreted to mean "include, but are not limited to …". In addition, the term "coupled" or "coupled" means an indirect or direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections.
"Controller" shall mean a separate circuit component configured to read signals and take action in response to such signals, an Application Specific Integrated Circuit (ASIC) constructed on a substrate, a microcontroller constructed on a substrate with or without control software stored on the substrate, a Field Programmable Gate Array (FPGA), or a combination thereof.
In terms of electrical devices, the terms "input" and "output" refer to electrical connections to the electrical device and should not be considered verbs requiring operation. For example, the controller may have a gate output and one or more sense inputs.
Detailed Description
The following discussion is directed to various embodiments of the invention. While one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims. In addition, those skilled in the art will appreciate that the following description has broad application and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.
The use of an auxiliary power supply to provide control power to the control voltage terminal of the primary controller has several disadvantages. For example, the auxiliary power supply may not be able to supply enough power to maintain the control voltage terminal at a voltage sufficient to enable the primary controller to function. Related art solutions for supplementing the power supplied to the control voltage terminal also have drawbacks. Such a related art solution may utilize a high voltage monitor terminal of the primary controller, which may enable the control voltage terminal and the circuitry connected thereto to be constructed using more expensive processes capable of withstanding higher voltages, such as 80 volts. The system and method of the present disclosure provides supplemental power from the high voltage monitor terminal of the primary controller to the control voltage terminal while the input voltage of the high voltage monitor terminal is in a valley with a relatively low voltage. The system and method of the present disclosure also provides for the high voltage monitor terminal to have a reduced impedance when the input voltage of the high voltage monitor terminal is in the valley, thereby enabling a more accurate measurement of the input voltage, while also providing energy efficiency due to the high voltage monitor terminal having a greater impedance value when the input voltage of the high voltage monitor terminal is relatively high.
Fig. 1 shows a schematic circuit diagram of a power converter 100 in accordance with at least some embodiments. In particular, the power converter 100 includes a primary side 102 for acting on incoming Alternating Current (AC) power. The primary side 102 includes an AC input 104 that includes a line terminal L and a neutral terminal N for receiving incoming AC power that may be received from an AC source, such as a utility line or household outlet. The AC input 104 is electrically coupled to an input power rectifier 108 to provide DC input power to a primary winding 110 of a transformer 112. More specifically, the input power rectifier 108 provides DC input power to the rectified input node 114 and the input reference node 116, which ultimately provide DC input power to the primary winding 110 of the transformer 112. In at least some embodiments, and as shown in fig. 1, the input power rectifier 108 includes four power rectifier diodes D100, D101, D102, D103 configured as a full bridge rectifier, although other rectifier arrangements (e.g., half bridge) may also be used. In the exemplary system of fig. 1, electronically controlled switch Q1 is configured to selectively provide or interrupt current flowing through primary winding 110 between rectified input node 114 and input reference node 116. The electronically controlled switch Q1 may take any suitable form (e.g., a Field Effect Transistor (FET), as shown, or a bipolar junction transistor), and is hereinafter referred to as simply switch device Q1.
In accordance with at least some embodiments, the primary side 102 of the power converter 100 further includes a primary controller 120 to coordinate the operation of the power converter 100. In the exemplary system of fig. 1, the primary controller 120 defines a control voltage terminal 122 for receiving low voltage power for powering the primary controller 120 to function. Control voltage capacitor C2 may be connected between control voltage terminal 122 and input reference node 116 for maintaining a voltage on control voltage terminal 122 of primary controller 120. The control voltage terminal 122 is supplied with power by an auxiliary power supply 123, which in the exemplary system includes an auxiliary winding 124 of the transformer 112 and a rectifier diode D2 that performs half-bridge rectification. In other words, the auxiliary power supply 123 supplies DC current to the control voltage capacitor C2 and the control voltage terminal 122 of the primary controller 120.
In the exemplary system of fig. 1, the switching device Q1 may be controlled by a driving output DRV of the primary controller 120. The first shunt resistor R2 may be connected in series with the electronically controlled switch Q1 to generate a current sense voltage across the first shunt resistor R2. The first shunt resistor R2 may be electrically connected to the current sense input CS of the primary controller 120, thereby enabling the primary controller 120 to monitor the current through the electronically controlled switch Q1.
In the exemplary system of fig. 1, the input rectifier 130 includes two input rectifying diodes D104, D105 electrically connected between a corresponding one of the line terminal L and the neutral terminal N and the input sense node 128 to provide an input voltage V HV on the input sense node 128. More specifically, the input voltage V HV generated by the input rectifier 130 corresponds to the rectified voltage of the incoming AC power on the AC input 104 and periodically varies below the first starting threshold voltage V HV_I1(on). Examples of periodic input voltages V HV are shown graphically in the timing diagrams of fig. 5-7, discussed in more detail below. In accordance with at least some embodiments, the primary controller 120 further includes a monitor terminal 126 electrically coupled to an input sense node 128 to enable the primary controller 120 to monitor the input voltage V HV. Thus, the primary controller 120 is able to monitor the voltage of the incoming AC power via the monitor terminal 126.
Snubber network 156 may be connected to primary winding 110 of transformer 112 to dissipate transient high voltages that may be generated by the collapsing magnetic field when switching device Q1 interrupts current flow through primary winding 110. As shown in fig. 1, the snubber network 156 may include snubber resistors R1 and snubber capacitors C5 connected in series with each other. The snubber network 156 may also include a snubber diode D3 connected in series with both the snubber resistor R1 and the snubber capacitor C5. Snubber diode D3 may be connected to block current flow through snubber network 156 during normal operation where current flows through primary winding 110. The snubber diode D3 may become conductive when subjected to a voltage having a polarity opposite to that experienced during normal operation. In other words, snubber diode D3 causes snubber network 156 to conduct current only when subjected to a reverse-biased electromotive force (EMF), also referred to as a back EMF, such as a transient high voltage that may be generated by a collapsing magnetic field in primary winding 110.
In accordance with at least some embodiments, the power converter 100 further includes a secondary side 140 configured to provide output power to a Direct Current (DC) output 142 that includes a positive output terminal + and a negative output terminal. In the exemplary system of fig. 1, the secondary side 140 includes a secondary rectifier 144 electrically connected between a secondary winding 146 of the transformer 112 and the positive output terminal + of the DC output 142. In the exemplary system of fig. 1, the secondary rectifier 144 includes a single diode D1; however, in other cases, the secondary rectifier 144 may take other forms. For example, the secondary rectifier 144 may be a synchronous rectifier in the form of an electronically controlled switch driven by a secondary side controller. As shown, the secondary winding 146 of the transformer 112 is configured for flyback operation. In the exemplary system of fig. 1, an output capacitor C3 is connected between the positive output terminal + and the negative output terminal-of the DC output 142 to reduce ripple in the output voltage.
In accordance with at least some embodiments, the power converter 100 may include a feedback circuit 160 that provides a feedback signal to the primary controller 120 to monitor the operation of the secondary side 140 and control the voltage of the DC output 142. In the exemplary system of fig. 1, the feedback circuit 160 includes a first voltage divider 162 that includes two first resistors R6, R7 connected in series between the positive output terminal + and the negative output terminal-of the DC output 142. The first voltage divider 162 defines an intermediate node 164 between the two first resistors R6, R7, wherein the intermediate node 164 has a first fractional voltage that is a predetermined fraction of the voltage of the DC output 142. The predetermined fraction depends on the relative values of the first resistors R6, R7 within the voltage divider 162. Shunt regulator IC2 is connected between the negative output terminal-and regulation node 166, with the reference input connected to intermediate node 164 to maintain regulation node 166 at a regulated voltage proportional to the voltage on the intermediate node. A feedback capacitor C6 may be connected between intermediate node 164 and regulation node 166 to stabilize the voltage on regulation node 166.
In the exemplary system of fig. 1, feedback circuit 160 includes optocoupler OK1, which includes a Light Emitting Diode (LED) and a photosensitive switch. Second shunt resistor R3 and series resistor R4 are connected in series between regulation node 166 and positive output terminal + of DC output 142. The LED of optocoupler OK1 is connected across the second shunt resistor R3 and lights up to activate the photosensitive switch when the output of the secondary rectifier 144 is above a predetermined voltage threshold. In the exemplary system of fig. 1, the photosensitive switch of optocoupler OK1 is electrically connected to the feedback input FB of primary controller 120. Thus, optocoupler OK1 may allow primary controller 120 to monitor the operation of secondary side 140 while being electrically isolated from that secondary side. In some embodiments, a hold capacitor C4 is connected between the feedback input FB of the primary controller 120 and the input reference node 116. After deactivation of the photosensitive switch, the holding capacitor C4 holds the voltage on the feedback input FB. Accordingly, the hold capacitor C4 may allow the primary controller 120 to sense the activation of the optocoupler OK1, which may otherwise proceed too fast to be sensed.
In accordance with at least some embodiments, the power converter 100 may include a decoupler 150 disposed between the primary side 102 and the secondary side 140 to provide electrical isolation and reduce interference transmitted therebetween. More specifically, and as shown in fig. 1, the decoupler 150 may include a decoupling capacitor CY1 electrically connected between the input reference node 116 and the negative output terminal of the DC output 142. The decoupler 150 may include a bleeder resistor R8 to discharge any residual voltage from the decoupler capacitor CY1 after power is removed from the power converter 100. In some embodiments, the bleeder resistor R8 may have a relatively high resistance to reduce energy loss due to current flowing during normal operation.
Still referring to fig. 1, the power converter 100 may further include an input filter 152 electrically connected between the line terminal L and the neutral terminal N of the AC input 104. More specifically, and as shown in fig. 1, the input filter 152 may include first filter capacitors CY2, CY3, each electrically connected between a common node 154 (such as a ground node) and a corresponding one of the line terminal L and the neutral terminal N. Additionally or alternatively, the input filter 152 may include a second filter capacitor CX2 electrically connected between the line terminal L and the neutral terminal N of the AC input 104. The input filter 152 may be used to reduce electromagnetic interference transmitted between the power converter 100 and a line source connected to the AC input 104 by suppressing any transient voltages on either or both of the line terminal L and/or the neutral terminal N of the AC input 104.
Fig. 2 shows a partial block diagram of a primary controller 120 in accordance with at least some embodiments. The primary controller 120 of the power converter 100 includes a control voltage terminal 122 for being energized with a control voltage V CC to power the primary controller 120. The primary controller 120 also includes a monitor terminal 126 for monitoring the input voltage V HV that is powering the power converter 100.
The primary controller 120 shown in fig. 2 also includes a supplemental power controller 200 configured to provide power from the monitor terminal 126 to the control voltage terminal 122. In other words, when auxiliary power supply 123 (fig. 1) is unable to provide a sufficient amount of DC current to operate primary controller 120 and charge control voltage capacitor C2, supplemental power controller 200 may provide power to charge control voltage capacitor C2 (fig. 1) and/or operate primary controller 120.
In accordance with at least some embodiments, the supplemental power controller 200 includes a regulator circuit 202 having a regulator input 203 and a regulator output 204. The regulator input 203 is in electrical communication with the monitor terminal 126 for receiving current to produce a regulated voltage on the regulator output 204. The supplemental power controller 200 also includes a reference current generator 206 having a reference generator input 207 and a reference current output 208. The reference generator input 207 is electrically connected to the regulator output 204 of the regulator circuit 202 for receiving power therefrom. The reference generator 206 is configured to provide a regulated and constant current to a reference current output 208.
In accordance with at least some embodiments, the supplemental power controller 200 includes a first current source 210 configured to drive a first current I DSS1 from the monitor terminal 126 to the control voltage terminal 122 in response to the input voltage V HV being less than a first starting threshold voltage V HV_I1(on). The first current I DSS1 may be used by the primary controller 120, for example, to provide power to operate one or more of the circuits. Alternatively or additionally, the first current I DSS1 may be operable to charge a control voltage capacitor C2 (fig. 1). In one exemplary embodiment, the first current I DSS1 may be 33 milliamps (mA). In another exemplary embodiment, the first current I DSS1 may be 38mA.
Driving the first current I DSS1 from the monitor terminal 126 to the control voltage terminal 122 when the input voltage V HV is less than the first starting threshold voltage V HV_I1(on) may reduce construction costs. For example, circuitry connected to control voltage terminal 122 may not need to withstand higher voltage levels that may be present on monitor terminal 126. Accordingly, the circuit connected to the control voltage terminal 122 may have a lower cost configuration than a circuit that must withstand a higher voltage. For example, by using the method described above, the circuit connected to the control voltage terminal 122 may be constructed using a silicon process rated at 40 volts, wherein an alternative design in which current is always supplied from the monitor terminal 126 may require that the circuit connected to the control voltage terminal 122 be constructed using a more expensive process capable of withstanding higher voltages (such as 80 volts).
In accordance with at least some embodiments, and as shown in fig. 2, the first current source 210 includes a first current input 212, a first current output 214, a first control input 216, and a first current reference input 218. The first current input 212 is electrically connected to the regulator output 204 of the regulator circuit 202 to supply a first current I DSS1 from the monitor terminal 126 to the first current source 210. The first current source 210 is configured to output a first current I DSS1 from the first current output 214 in response to assertion of the first control input 216. The first current source 210 is configured to regulate an amount of the first current I DSS1 using the first current reference input 218.
In accordance with at least some embodiments, and as shown in fig. 2, the second current source 220 includes a second current input 222, a second current output 224, a second control input 226, and a second current reference input 228. The second current input 222 is electrically connected to the regulator output 204 of the regulator circuit 202 to supply a second current I DSS2 from the monitor terminal 126 to the second current source 220. The second current source 220 is configured to output a second current I DSS2 from the second current output 224 in response to assertion of the second control input 226. The second current source 220 is configured to regulate an amount of the second current I DSS2 using the second current reference input 228. In accordance with at least some embodiments, the second current I DSS2 is less than the first current I DSS1 and provides a beneficial result of reducing the effective impedance of the monitor terminal 126 when the input voltage V HV is in the valley. The impedance reduction of the monitor terminal 126 thereby limits the ripple of the input voltage V HV on the monitor terminal 126 to enable the primary controller 120 to more accurately measure the DC input voltage or the rectified AC input voltage on the rectified input node 114 and the input reference node 116. In one exemplary embodiment, the second current I DSS2 may be 500 microamps (μa).
The supplemental power controller 200 may also include a delay circuit 230 configured to delay the driving of the first current I DSS1 by the first current source 210. More specifically, and as shown in fig. 2, delay circuit 230 includes a first delay input 232, a second delay input 234, a third delay input 236, and a delay output 238, wherein delay output 238 is coupled to first control input 216 of first current source 210. Delay circuit 230 includes a delay timer 240 having a delay trigger input 242 and a timer output 244 and a delay setting input 246. Delay timer 240 is configured to monitor delay trigger input 242 to wait delay time t delay after delay trigger input 242 has been asserted and to assert timer output 244 after delay time t delay has elapsed. In some embodiments, and as shown in fig. 2, the timer output 244 is connected to the first control input 216 of the first current source 210, thereby providing for the delay timer 240 a delayed validation of the first control input 216 of the first current source 210 within a delay time t delay after the delay trigger input 242 is validated. In some embodiments, delay timer 240 may be configured to modify the length of the delay time in response to one or more signals provided on delay setting input 246.
The supplemental power controller 200 may also include a valley timer 250 that includes first and second valley trigger inputs 252 and 254 and a valley time output 256. The valley timer 250 may be configured to determine the valley time t valley as a length of time from when the input voltage V HV falls below the first start threshold voltage V HV_I1(on) until the input voltage V HV is less than the reference voltage V HV(min). This is graphically illustrated in the timing diagram of fig. 6, discussed more below. More specifically, and as shown in fig. 2, the valley timer 250 is configured to monitor the valley trigger inputs 252, 254 to determine a valley time t valley between the assertion of the first valley trigger input 252 (corresponding to the input voltage V HV falling below the first start threshold voltage V HV_I1(on)) until the assertion of the second valley trigger input 254 (corresponding to the input voltage V HV being less than the reference voltage V HV(min)) and to output a signal on the valley time output 256 corresponding to the valley time t valley. In some embodiments, and as shown in fig. 2, the valley time output 256 is connected to the second delay input 234 of the delay circuit 230 to provide the valley time t valley to the delay circuit 230.
The supplemental power controller 200 may also include a switching power supply timer 260 that includes a first switching power supply trigger input 262, a second switching power supply trigger input 264, and a switching power supply time output 266. The switching power supply timer 260 may be configured to determine the power supply time interval t IDSS as the length of time from the first switching power supply trigger input 262 to the second switching power supply trigger input 264. In some embodiments, and as shown in fig. 2, the first switching power supply trigger input 262 is connected to a first control input 216 of the first current source 210 that is asserted to drive the first current I DSS1, and the second switching power supply trigger input 264 is configured to be asserted in response to the control voltage V CC exceeding the first control voltage threshold V CC(on). In other words, the switching power supply timer 260 may record the power supply time interval t IDSS during which the control voltage capacitor C2 (fig. 1) is charged by the first current I DSS1 by measuring the length of time when the first current I DSS1 is driven and when the control voltage V CC is less than the first control voltage threshold V CC(on).
The supplemental power controller 200 may also include a control voltage sensor 270 that includes a voltage sensor input 272 and a voltage sensor output 274, wherein the voltage sensor input 272 is connected to the control voltage terminal 122. Control voltage sensor 270 may be configured to measure control voltage V CC on control voltage terminal 122 and validate voltage sensor output 274 in response to control voltage V CC exceeding a predetermined value. In some embodiments, and as shown in fig. 2, the voltage sensor output 274 may be connected to the second switching power supply trigger input 264 of the switching power supply timer 260 to validate the second switching power supply trigger input 264 in response to the control voltage V CC exceeding the first control voltage threshold V CC(on).
In some embodiments, and as shown in fig. 2, the supplemental power controller 200 may also include a monitoring circuit 280 that includes a monitoring input 282 connected to the monitoring terminal 126 for monitoring the input voltage V HV. The monitor circuit 280 may also include a first monitor output 284, a second monitor output 286, and a third monitor output 288. The monitor circuit 280 is configured to independently validate each of the monitor outputs 284, 286, 288 in response to the input voltage V HV being below a predetermined value associated with each of the monitor outputs 284, 286, 288.
More specifically, and as shown in fig. 2, the first monitor output 284 is connected to the delay trigger input 242 of the delay timer 240 via the first delay input 232 of the delay circuit 230, and the monitor circuit 280 is configured to assert the first monitor output 284 when the input voltage V HV is less than the first start threshold voltage V HV_I1(on). This configuration causes the delay timer 240 to begin counting in response to the input voltage V HV being less than the first start threshold voltage V HV_I1(on). In other words, the delay timer 240 delays driving the first current I DSS1 for a period of time t delay after the input voltage V HV drops below the first start threshold voltage V HV_I1(on). In some embodiments, the first monitor output 284 is also connected to the first valley trigger input 252 of the valley timer 250.
In some embodiments, and as also shown in fig. 2, the second monitor output 286 is connected to the second control input 226 of the second current source 220, and the monitor circuit 280 is configured to assert the second monitor output 286 when the input voltage V HV is less than a second start threshold voltage V HV_I2(on), which in the exemplary embodiment is higher than the first start threshold voltage V HV_I1(on). In addition, the third monitor output 288 is connected to the second valley trigger input 254 of the valley timer 250, and the monitor circuit 280 is configured to validate the third monitor output 288 when the input voltage V HV is below the reference voltage V HV(min). This configuration may allow the valley timer 250 to stop counting when the input voltage V HV is at or near a local minimum (discussed in more detail below with reference to fig. 4 and 7). The reference voltage V HV(min) may be the expected minimum value of the input voltage V HV. The reference voltage V HV(min) may be slightly greater than the expected minimum value of the input voltage V HV to ensure that the valley is reliably detected during each cycle. In one embodiment, the input voltage V HV drops periodically in each valley to a value of about 0.0V, and the reference voltage V HV(min) is 5.0V.
Fig. 3 shows a partial schematic, partial block diagram of a primary controller 120 in accordance with at least some embodiments. More specifically, FIG. 3 shows a partial block diagram of FIG. 2, with additional details.
In the embodiment shown in fig. 3, the monitor circuit 280 includes a second voltage divider 306 having two resistors connected in series between the monitor input 282 and a ground plane having a defined reference (such as 0V) to define a monitor node 308 between the resistors of the second voltage divider 306. The second voltage divider 306 is operable to energize the monitor node 308 with a voltage that is a predetermined fraction of the input voltage V HV on the monitor terminal 126, where the predetermined fraction is dependent on the relative values of the resistors within the second voltage divider 306. The resistors of the second voltage divider 306 each have a relatively high resistance value, which may be greater than 1 megaohm (mΩ), to provide a relatively high impedance at the monitor input 282, thereby reducing the current flowing from the monitor terminal 126 into the monitor circuit 280 while enabling the monitor circuit 280 to measure the input voltage V HV at the monitor terminal 126.
In some embodiments, and as shown in fig. 3, the monitoring circuit 280 further includes a reference generator 310 that includes a reference input 312 and a reference output 314. The reference generator 310 is configured to generate a reference voltage on a reference output 314 based on a command signal applied to a reference input 312. The monitor circuit 280 also includes a monitor comparator 320 having a non-inverting input 322 and an inverting input 324 and a comparison output 326. The monitor comparator 320 may be configured to validate the comparison output 326 in response to the voltage on the non-inverting input 322 exceeding the voltage on the inverting input 324. As shown in fig. 3, the non-inverting input 322 is connected to the reference output 314 of the reference generator 310 and the inverting input 324 is connected to the monitor node 308. The monitor comparator 320 may be implemented using an operational amplifier (op-amp) as shown. However, in other cases, the monitor comparator 320 may take other forms. The monitor comparator 320 may include other inputs (not shown), such as inputs for power and ground.
In some embodiments, and as shown in fig. 3, the monitoring circuit 280 also includes a monitoring controller 328 having a controller input 330 and a command output 332, and first and second controller outputs 334, 336 and a third controller output 338. The monitor controller 328 is configured to output a series of values to the command output 332 and simultaneously monitor the controller input 330 to determine if the voltage on the reference output 314 of the reference generator 310 exceeds the voltage of the monitor node 308. By outputting a series of different voltages on command output 332, monitor circuit 280 is able to measure the voltage of monitor node 308. Therefore, the monitoring circuit 280 may also measure the input voltage V HV.
The supervisory controller 328 may also be configured to validate the various controller outputs 334, 336, 338 in response to the input voltage V HV having a particular associated value or range of values. The first controller output 334 is connected to the first monitor output 284 of the monitor circuit 280 such that the monitor controller 328 asserts the first monitor output 284 when the input voltage V HV is less than the first start threshold voltage V HV_I1(on). Likewise, the second controller output 336 is connected to the second monitor output 286 such that the monitor controller 328 validates the second monitor output 286 when the input voltage V HV is less than the second start threshold voltage V HV_I2(on). Similarly, the third controller output 338 is connected to the third monitor output 288 such that the monitor controller 328 validates the third monitor output 288 when the input voltage V HV is below the reference voltage V HV(min).
In accordance with at least some embodiments, and as also shown in fig. 3, regulator circuit 202 includes a zener diode 340 connected between the ground plane and a first reference node 342 for maintaining a predetermined voltage on first reference node 342. A first bias current source 344 is connected between the first reference node 342 and the regulator output 204. Regulator transistor 346 includes a gate terminal connected to first reference node 342, a source terminal connected to regulator output 204, and a drain terminal connected to regulator input 203. Thus, regulator transistor 346 is used to generate a regulated voltage on regulator output 204 and is regulated by the combination of zener diode 340 and first bias current source 344. In some exemplary embodiments, regulator transistor 346 is an n-channel junction gate field effect transistor (n-JFET), as shown in fig. 3. However, in other cases, regulator transistor 346 may take other forms, such as another type of Field Effect Transistor (FET) or Bipolar Junction Transistor (BJT).
In accordance with at least some embodiments, and as also shown in fig. 3, the reference current generator 206 includes a second bias current source 347 connected between the ground plane and the reference current output 208. The reference current generator 206 may also include a current reference transistor 348, wherein a source terminal is connected to the reference generator input 207 and wherein a gate terminal and a drain terminal are each connected together and to the reference current output 208. In some exemplary embodiments, and as shown in fig. 3, the current reference transistor 348 is an enhancement mode P-type metal oxide semiconductor field effect transistor (P-MOSFET). However, in other cases, the current reference transistor 348 may take other forms, such as another type of Field Effect Transistor (FET) or Bipolar Junction Transistor (BJT).
In accordance with at least some embodiments, and as also shown in fig. 3, the first current source 210 includes a first current regulating transistor 350 having a source terminal connected to the first current input 212, the source terminal connected to receive current from the regulator output 204 of the regulator circuit 202. The source terminal of the first current regulating transistor 350 is also connected to the source terminal of a current reference transistor 348 within the reference current generator 206. The first current regulating transistor 350 may also have a gate terminal connected to the first current reference input 218, which is connected to a gate terminal of a current reference transistor 348 within the reference current generator 206. When connected as indicated, at an equivalent gate-to-source voltage, the current reference transistor 348 and the first current regulation transistor 350 together form a "current mirror" that drives the source-to-drain current of the first current regulation transistor 350 to a predetermined first current I DSS1 that is proportional to the source-to-drain current of the current reference transistor 348 (i.e., the current through the second bias current source 347). In some exemplary embodiments, and as shown in fig. 3, the first current regulating transistor 350 is an enhancement mode P-type metal oxide semiconductor field effect transistor (P-MOSFET). However, in other cases, the first current adjusting transistor 350 may take other forms, such as another type of Field Effect Transistor (FET) or Bipolar Junction Transistor (BJT).
In at least some embodiments, the first current source 210 further includes a first switching transistor 352 configured to selectively switch the first current I DSS1 in response to assertion of the first control input 216. More specifically, and as shown in fig. 3, the first switching transistor 352 may be an enhancement mode P-type metal oxide semiconductor field effect transistor (P-MOSFET), wherein its source terminal is connected to the drain terminal of the first current regulating transistor 350, and wherein its drain and gate terminals are connected to the first current output 214 and the first control input 216, respectively, of the first current source 210. However, in other cases, the first switching transistor 352 may take other forms, such as another type of Field Effect Transistor (FET) or Bipolar Junction Transistor (BJT).
In accordance with at least some embodiments, and as also shown in fig. 3, the second current source 220 includes a second current regulating transistor 354 having a source terminal connected to the second current input 222, the source terminal connected to receive current from the regulator output 204 of the regulator circuit 202. The source terminal of the second current regulating transistor 354 is also connected to the source terminal of a current reference transistor 348 within the reference current generator 206. The second current regulating transistor 354 may also have a gate terminal connected to a second current reference input 228 that is connected to a gate terminal of a current reference transistor 348 within the reference current generator 206. When connected as indicated, at an equivalent gate-to-source voltage, the current reference transistor 348 and the second current regulating transistor 354 together form a "current mirror" that drives the source-to-drain current of the second current regulating transistor 354 to a predetermined second current I DSS2 that is proportional to the source-to-drain current of the current reference transistor 348 (i.e., the current through the second bias current source 347). In some exemplary embodiments, and as shown in fig. 3, the second current regulating transistor 354 is an enhancement mode P-type metal oxide semiconductor field effect transistor (P-MOSFET). However, in other cases, the second current regulating transistor 354 may take other forms, such as another type of Field Effect Transistor (FET) or Bipolar Junction Transistor (BJT). In some embodiments, the second current I DSS2 may be different from the first current I DSS1 due to the physical difference between the second current regulating transistor 354 and the first current regulating transistor 350.
In at least some embodiments, the second current source 220 further includes a second switching transistor 356 configured to selectively switch the second current I DSS2 in response to assertion of the second control input 226. More specifically, and as shown in fig. 3, the second switching transistor 356 may be an enhancement-type P-type metal oxide semiconductor field effect transistor (P-MOSFET), wherein its source terminal is connected to the drain terminal of the second current regulating transistor 354, and wherein its drain and gate terminals are connected to the second current output 224 and the second control input 226, respectively, of the second current source 220. However, in other cases, the second switching transistor 356 may take other forms, such as another type of Field Effect Transistor (FET) or Bipolar Junction Transistor (BJT).
In some embodiments, and as shown in fig. 3, the control voltage sensor 270 includes a Control Voltage (CV) comparator 360 having a non-inverting input 362 and an inverting input 364 and a CV comparison output 326. The control voltage comparator 360 may be configured to validate the comparison output 366 in response to the voltage on the non-inverting input 362 exceeding the voltage on the inverting input 364. As shown in fig. 3, the non-inverting input 362 is connected to the control voltage terminal 122 via the voltage sensor input 272. A threshold voltage source 368 is connected between the ground plane and the inverting input 364 to drive the inverting input 364 to a first control voltage threshold V CC(on). In other words, the Control Voltage (CV) comparator 360 is configured to validate the voltage sensor output 274 in response to the control voltage V CC exceeding the first control voltage threshold V CC(on). The control voltage comparator 360 may be implemented using an operational amplifier (op-amp) as shown. However, in other cases, the control voltage comparator 360 may take other forms. The control voltage comparator 360 may include other inputs (not shown), such as inputs for power and ground.
In some embodiments, and as shown in fig. 3, delay circuit 230 includes a computation block 370 having a computation output 372 and two inputs connected to second delay input 234 and third delay input 236. The calculation block 370 may be configured to calculate the setting of the delay time t delay based on the valley time t valley and the power supply time interval t IDSS. The calculation block 370 may be configured to transmit the delay time t delay to the delay timer 240 via a calculation output 372, which is connected to the delay setting input 246 of the delay timer 240. Further, and in accordance with at least some embodiments, the delay time t delay may be set to the valley time t valley minus half of the power supply time interval t IDSS. This setting of the delay time t delay serves to center the supply time interval t IDSS around the reference voltage V HV(min), wherein half of the supply time interval t IDSS precedes the input voltage V HV being at its minimum value, and wherein half of the supply time interval t IDSS follows the input voltage V HV being at its minimum value.
In accordance with at least some embodiments, and as shown in fig. 3, the delay circuit 230 of the supplemental power controller 200 may further include a delay time adjuster 378 having a delay adjustment output 380 coupled to the delay timer 240 and configured to vary the length of the delay time t delay between the assertion of the delay trigger input 242 until the assertion of the timer output 244 by the delay timer 240. The delay time adjuster 378 may include one or more of a first adjuster input 382, a second adjuster input 386, a third adjuster input 390, and a fourth adjuster input 394, wherein the delay time adjuster 378 is configured to cause a change in a length of the delay time t delay by signaling the delay timer 240 via the delay adjustment output 380 in response to an assertion of any of the adjuster inputs 382, 386, 390, 394. The delay time adjuster 378 may be configured to change the length of the delay time t delay by different amounts or in different ways in response to the assertion of different ones of the adjuster inputs 382, 386, 390, 394. For example, the delay time t delay may be reset to zero or a predetermined value, or incremented or decremented by a predetermined amount in response to one or more of the regulator inputs 382, 386, 390, and 394.
The delay circuit 230 may also include a timeout comparator 384 configured to validate the first regulator input 382 of the delay time regulator 378 in response to the power-on time interval t IDSS being greater than the predetermined on-time t IDSS(max). The delay circuit 230 may also include a consumption monitor 388 configured to validate the second regulator input 386 in response to the primary controller 120 being in a high consumption mode, for example, wherein the number of drive clock drv_clk pulses exceeds a certain number within a given period of time. More specifically, the consumption monitor 388 may assert the second regulator input 386 in response to the number of drive clock drv_clk pulses being greater than a predetermined margin value within an HV period, where the HV period is a period of time since the last start of driving the first current I DSS1 by the first current source 210.
Still referring to fig. 3, the delay circuit 230 may further include an input amplitude sensor 392 configured to validate the third regulator input 390 in response to the amplitude of the input voltage V HV varying more than a predetermined amount over a predetermined period of time. For example, the input amplitude sensor 392 may validate the third regulator input 390 in response to the amplitude of the input voltage V HV varying more than an absolute value and/or more than a predetermined percentage between subsequent HV cycles. The delay circuit 230 may also include a valley absence sensor 396 configured to assert the fourth regulator input 394 and not present the third monitor output 288 in response to a power supply time interval t IDSS passing from assertion of the first control input 216 of the first current source 210 until assertion of the voltage sensor output 274 of the control voltage sensor 270. In other words, the valley absence sensor 396 may assert the fourth regulator input 394 in response to the valley not being detected during the power time interval t IDSS.
Fig. 4 shows a graph of voltage over time in accordance with at least some embodiments. More specifically, fig. 4 shows a graph of the input voltage V HV of the power converter 100, where the values periodically change to define the valley 400 as to the time in which the input voltage HV is at the first local minimum 402a, the second local minimum 402b, the third local minimum 402c, and the fourth local minimum 402 d. Fig. 4 shows a case where the input voltage V HV at the local minimum 402 is irregular between cycles. More specifically, the first local minimum 402a and the third local minimum 402c are each above 0V, the second local minimum 402b is approximately equal to 0V, and the fourth local minimum 402d is below 0V line (i.e., it has a negative voltage value). Such irregularities in the value of the input voltage V HV between the local minima 402 may result from the combination of the first filter capacitors CY2, CY3 and the decoupling capacitor CY1 together with the relatively high impedance of the monitor terminal 126. Such irregularities in the value of the input voltage V HV between the local minima 402 may have an adverse effect. For example, such irregularities may make it difficult to detect the valleys 400. In other words, because the input voltage V HV is different at different local minima of the local minimum 402, it may be difficult to detect when the input voltage V HV reaches the local minimum 402.
Fig. 5 shows a timing diagram in accordance with at least some embodiments. In particular, fig. 5 shows a graph of the input voltage V HV of the power converter 100, where the value varies periodically to define the valley 400 as to when the input voltage V HV is at the local minimum 402 and where the input voltage V HV is equal to the reference voltage V HV(min). Fig. 5 also shows a graph of the control voltage V CC during the same period of time.
As shown in fig. 5, each valley 400 includes a sharply increasing control voltage V CC until the control voltage V CC reaches the first control voltage threshold V CC(on), at which point the control voltage V CC remains at the first control voltage threshold V CC(on) until the input voltage V HV exceeds the first stop threshold voltage V HV_I1(off), after which the control voltage V CC gradually decreases until the next valley 400 begins. The sharply increased control voltage V CC is due to the control voltage capacitor C2 being charged by the first current I DSS1. Once the control voltage capacitor C2 is charged, the control voltage V CC may remain at the first control voltage threshold V CC(on), with the first current I DSS1 still being driven from the monitor terminal 126 to the control voltage terminal 122.
Fig. 6 shows a timing diagram in accordance with at least some embodiments. In particular, fig. 6 shows a diagram of the input voltage V HV of the power converter 100 and a diagram of the control voltage V CC over the same period of time.
Fig. 6 graphically illustrates a number of cycles of the input voltage V HV of the power converter 100. The shaded area under the curve of the input voltage V HV represents the period of time that the supplemental power controller 200 is actively charging the control voltage capacitor C2 (fig. 1). More specifically, the shaded areas each represent a corresponding one of the power supply time intervals t IDSS, which starts when the first current I DSS1 starts to drive from the monitor terminal 126 to the control voltage terminal 122 (fig. 1). When the control voltage V CC reaches the first control voltage threshold V CC(on), the shaded areas (and the corresponding supply time interval t IDSS) each end, at which time the control voltage V CC remains constant and the control voltage capacitor C2 is no longer charged.
In some exemplary embodiments, and as shown in the first or leftmost valley 400 of fig. 6, the delay time t delay is initially set to zero to cause the power-on time interval t IDSS to begin immediately when the input voltage V HV falls below the first starting threshold voltage V HV_I1(on). In the subsequent valley 400, the delay time t delay may be a non-zero amount of time such that the power-up time interval t IDSS begins after the input voltage V HV falls below the first starting threshold voltage V HV_I1(on). In other words, the two valleys 400 shown on the right side of fig. 6 show that the delay timer 240 delays driving the first current I DSS1 from the monitor terminal 126 to the control voltage terminal 122 for a non-zero delay time t delay after the input voltage V HV drops below the first starting threshold voltage V HV_I1(on). The delay time t delay is used to center the supply time interval t IDSS within the valley 400 with approximately the same amount of time before and after the input voltage V HV is at the local minimum 402.
As also shown in fig. 6, centering the supply time interval within the valley 400 may cause the first current I DSS1 to be driven when the input voltage V HV is at the substantially local minimum 402. In other words, the first supply time interval t IDSS shown in fig. 6 begins with the input voltage V HV at a higher voltage than the beginning input voltage V HV of the subsequent supply time interval t IDSS, which are centered within their respective valleys 400.
Having the center of the power supply time interval t IDSS within the valley 400 may result in energy savings and reduced associated heat generation compared to alternative solutions where current is provided from the monitor terminal 126 to the control voltage terminal 122 when the input voltage V HV is at a higher voltage. Alternatively or additionally, centering the power-on time interval within the valley 400 may cause reduced impact on other circuitry within the primary controller 120, which may depend on accurate measurement of the input voltage V HV on the monitor terminal 126, particularly at higher voltages. In other words, by having the center of the supply time interval t IDSS within the valley, the effect on the input voltage V HV on the monitor terminal 126 due to the driving of the first current I DSS1 from the monitor terminal 126 may be reduced, particularly when the input voltage V HV is at a relatively high value.
In some embodiments, and as shown in fig. 6, the primary controller 120 may be configured to stop driving the first current I DSS1 from the monitor terminal 126 to the control voltage terminal 122 in response to the input voltage V HV being greater than the first starting threshold voltage V HV_I1(on). This is an alternative to the condition shown in fig. 5 for stopping driving the first current I DSS1, wherein the first current I DSS1 is driven until the input voltage V HV exceeds the first stopping threshold voltage V HV_I1(off), which is greater than the first starting threshold voltage V HV_I1(on).
As discussed above with reference to fig. 2, the second current source 220 may be configured to drive the second current I DSS2 from the monitor terminal 126 to the control voltage terminal 122 in order to reduce the effective impedance of the monitor terminal 126 for reasons described in detail below. The second current source 220 may be configured to drive the second current I DSS2 in response to the input voltage V HV being less than the second starting threshold voltage V HV_I2(on). In at least some embodiments, and as shown in the timing diagram of fig. 6, the second start threshold voltage V HV_I2(on) can be greater than the first start threshold voltage V HV_I1(on).
More specifically, the second current I DSS2 may reduce the effective impedance of the monitor terminal 126 around the time that the input voltage V HV is in the valley 400. The impedance of monitor terminal 126 decreases, thereby limiting the ripple of input voltage V HV on monitor terminal 126. In other words, the reduced impedance of monitor terminal 126 stabilizes input voltage V HV. The stabilized input voltage V HV enables the primary controller 120 to use a comparator to detect the valley 400 as relative to the time in which the input voltage V HV is at the local minimum 402 to determine that the input voltage V HV is less than the reference voltage V HV(min). The stabilized input voltage V HV also enables the primary controller 120 to detect that the input voltage V HV is less than the first starting threshold voltage V HV_I1(on) with a higher accuracy than in an alternative design where the effective impedance of the monitor terminal 126 generated by the second current I DSS2 is reduced without the second current I DSS2.
As described above, the second current I DSS2 driven from the monitor terminal 126 to the control voltage terminal 122 when the input voltage V HV is less than the second starting threshold voltage V HV_I2(on) provides an efficiency advantage over an alternative in which the monitor terminal 126 is configured to always have a reduced impedance. By providing the monitor terminal 126 with a relatively high impedance when the input voltage V HV is relatively high (e.g., when the input voltage V HV is higher than the second starting threshold voltage V HV_I2(on)), energy consumption and waste heat generation may be reduced.
Further, a second current I DSS2 from the monitor terminal 126 to the control voltage terminal 122 and driven when the input voltage V HV is less than the second starting threshold voltage V HV_I2(on) may provide additional advantages. For example, if the second current I DSS2 is driven when the input voltage V HV is significantly higher (such as when the input voltage V HV is greater than the second starting threshold voltage V HV_I2(on)), the control voltage terminal 122 may not need to withstand the higher voltage levels that may be present on the monitor terminal 126. Accordingly, the structure of the control voltage terminal 122 may be cheaper than a structure that must withstand higher voltages. For example, by using the method described above, the control voltage terminal 122 may be constructed using a silicon process rated at 40 volts, wherein an alternative design of always supplying current from the monitor terminal 126 may require the control voltage terminal 122 to be constructed using a more expensive process capable of having a higher voltage (such as 80 volts).
Fig. 7 shows a timing diagram in accordance with at least some embodiments. In particular, fig. 7 is an enlarged portion of fig. 6, showing a supply time interval t IDSS when the first current I DSS1 is driven and when the control voltage V CC is less than the first control voltage threshold V CC(on), and the center of the supply time interval residing within the valley 400 for approximately the same amount of time before and after the input voltage V HV is at the local minimum 402. In other words, fig. 7 shows the effect of the delay timer 240 set such that the delay time t delay is equal to half of the valley time t valley minus the power supply time interval t IDSS, so that the center of the power supply time interval t IDSS is centered within the valley 400.
According to at least some embodiments, the delay time t delay may be adjusted in response to one or more different conditions. The adjustment may take the form of resetting the delay time t delay to zero or a predetermined value. Alternatively or additionally, the adjustment may take the form of an increasing or decreasing delay time t delay. Different types of adjustments may be used in response to different ones of the conditions.
According to at least some embodiments, the delay time t delay can be adjusted in response to the first current I DSS1 being driven longer than the predetermined on-time t IDSS(max). This condition may provide protection against overheating if the control voltage capacitor C2 is not fully charged by the first current I DSS1 or if the first current I DSS1 fails to turn off, for example if the first current I DSS1 remains on with the input voltage V HV exceeding the first stop threshold voltage V HV_I1(off). In other words, the delay time t delay may be adjusted in response to a failure of the off-comparison that should stop the first current I DSS1.
According to at least some embodiments, the delay time t delay may be adjusted in response to the primary controller 120 being in the high-consumption mode. There may be a high consumption mode, for example, where the primary controller 120 performs a plurality of driving clock drv_clk pulses greater than a predetermined margin value within an HV period, where the HV period is a period of time since the second current source 220 continuously starts driving the first current I DSS1.
According to at least some embodiments, the delay time t delay may be adjusted in response to a change in the magnitude of the input voltage V HV exceeding a predetermined amount within a predetermined period of time.
According to at least some embodiments, the delay time t delay may be adjusted in response to the input voltage V HV being greater than the reference voltage V HV(min) throughout the power supply time interval t IDSS when the control voltage capacitor C2 is charged by the first current I DSS1. In other words, the delay time t delay may be adjusted in response to the valley 400 not being detected during the power-on time interval t IDSS.
Fig. 8 illustrates a method in accordance with at least some embodiments. In particular, the method begins (block 800) and includes: monitoring an input voltage on a monitor terminal of the primary controller, the input voltage being a rectified AC signal periodically varying below a first starting threshold voltage to define a valley; (block 802); driving a first current from the monitor terminal to a control voltage terminal of the primary controller in response to the input voltage being less than a first starting threshold voltage (block 804); charging a control voltage capacitor coupled to the control voltage terminal with a first current (block 806); driving a second current, less than the first current, from the monitor terminal to the control voltage terminal in response to the input voltage being less than a second starting threshold voltage that is higher than the starting threshold voltage (block 808); and delaying driving the first current from the monitor terminal to the control voltage terminal for a delay time after the input voltage drops below the first starting threshold voltage (block 810); thereafter, the method ends (block 812).
In some implementations, delaying the driving of the first current from the monitor terminal to the control voltage terminal for a delay time after the input voltage drops below the first starting threshold voltage (block 810) further includes: determining a valley time as a length of time from when the input voltage drops below a first starting threshold voltage until the input voltage is less than a reference voltage; recording an amount of time to charge the control voltage capacitor with the first current as a supply time interval; and calculating the delay time as the valley time minus half of the power supply time interval. In other words, the delay time t delay can be calculated according to the following formula: t delay＝tvalley–tIDSS/2. A graphical example of this embodiment is shown in the timing diagram of fig. 6.
In some implementations, delaying the driving of the first current from the monitor terminal to the control voltage terminal for a delay time after the input voltage drops below the first starting threshold voltage (block 810) further includes: the delay time is adjusted in response to the first current being driven for a time longer than a predetermined time. For example, the delay time may be reset to zero or a predetermined value, or incremented or decremented by a predetermined amount.
In some implementations, delaying the driving of the first current from the monitor terminal to the control voltage terminal for a delay time after the input voltage drops below the first starting threshold voltage (block 810) further includes: determining that the primary controller is in a high consumption mode; and adjusting the delay time in response to the primary controller being in the high consumption mode. For example, the delay time may be reset to zero or a predetermined value, or incremented or decremented by a predetermined amount. The primary controller may be determined to be in a high consumption mode, for example, if the plurality of drive clock pulses exceeds a predetermined margin value within a given period of time. For example, if the number of drive pulses is greater than a predetermined margin value within the HV period since a previous start time of driving the first current from the monitor terminal to the control voltage terminal of the primary controller.
In some implementations, delaying the driving of the first current from the monitor terminal to the control voltage terminal for a delay time after the input voltage drops below the first starting threshold voltage (block 810) further includes: detecting that the amplitude of the input voltage varies by more than a predetermined amount over a predetermined period of time; and adjusting the delay time in response to a change in the amplitude of the input voltage. For example, the delay time may be reset to zero or a predetermined value, or incremented or decremented by a predetermined amount.
In some implementations, delaying the driving of the first current from the monitor terminal to the control voltage terminal for a delay time after the input voltage drops below the first starting threshold voltage (block 810) further includes: recording an amount of time to charge the control voltage capacitor (i.e., the period of time during which block 806 is active) by the first current as a power supply time interval; and adjusting the delay time in response to the input voltage being greater than the reference voltage throughout the power supply time interval. For example, the delay time may be reset to zero or a predetermined value, or incremented or decremented by a predetermined amount. In other words, the delay time may be reset or otherwise adjusted in response to the valley not being detected during the power-on time interval. In one embodiment, the step of adjusting the delay time includes increasing the delay time by the power-on time interval t IDSS of the previous cycle. In other words, the delay time t delay (n) may be set according to the following formula: t delay(n)＝tdelay(n-1)+tIDSS (n-1)/2, where n is a number of given periods within a regularly repeating cycle, such as the HV period of the input voltage V HV.
The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.

Claims (11)

1. A method of operating a power converter, comprising:
Monitoring an input voltage on a monitor terminal of a primary controller, the input voltage being a rectified AC signal that periodically varies below a first starting threshold voltage to define a valley;
driving a first current from the monitor terminal to a control voltage terminal of the primary controller in response to the input voltage being less than the first starting threshold voltage; and
A control voltage capacitor coupled to the control voltage terminal is charged by the first current.
2. The method of claim 1, further comprising:
Driving a second current from the monitor terminal to the control voltage terminal in response to the input voltage being less than a second starting threshold voltage that is higher than the first starting threshold voltage; and
Wherein the second current is less than the first current.
3. The method of claim 1, further comprising:
the driving of the first current from the monitor terminal to the control voltage terminal is delayed for a delay time after the input voltage drops below the first starting threshold voltage.
4. A power converter, comprising:
A primary side, the primary side comprising:
an AC input including a line terminal and a neutral terminal for receiving AC input power;
an input rectifier for providing rectified AC power to an input sense node, wherein the rectified AC power has an input voltage that periodically varies below a first starting threshold voltage to define a valley;
A primary winding of a transformer;
an auxiliary winding of the transformer;
a primary controller defining a control voltage terminal coupled to a control voltage capacitor and to the auxiliary winding of the transformer, and a monitor terminal coupled to the input sense node;
wherein the primary controller is configured to:
driving a first current from the monitor terminal to the control voltage terminal in response to the input voltage being less than the first starting threshold voltage; and
The control voltage capacitor is charged by the first current.
5. The power converter of claim 4, wherein the primary controller is further configured to drive a second current from the monitor terminal to the control voltage terminal in response to the input voltage being less than a second starting threshold voltage, wherein the second current is less than the first current.
6. The power converter of claim 4, further comprising:
A delay timer configured to delay driving the first current from the monitor terminal to the control voltage terminal for a delay time after the input voltage drops below the first start threshold voltage.
7. A primary controller for a power converter, comprising:
a control voltage terminal;
Monitoring the terminal; and
A supplemental power controller, the supplemental power controller comprising:
A monitor circuit defining a monitor input coupled to the monitor terminal and a first control output, the monitor circuit configured to measure an input voltage on the monitor terminal and validate the first control output when the input voltage is less than a first start threshold voltage; and
A first current source defining a first current input, a first current output, and a first control input, the first current input coupled to the monitor terminal, the first current output coupled to the control voltage terminal, and the first control input coupled to the first control output, the first current source configured to drive a first current from the monitor terminal to the control voltage terminal in response to assertion of the first control input.
8. The primary controller of claim 7, wherein the supplemental power controller further comprises:
A monitor circuit defining a second control output, the monitor circuit configured to validate the second control output when the input voltage is less than a second onset threshold voltage that is higher than the first onset threshold voltage; and
A second current source defining a second current input coupled to the monitor terminal, a second current output coupled to the control voltage terminal, and a second control input coupled to the second control output, the second current source configured to drive a second current from the monitor terminal to the control voltage terminal in response to assertion of the second control input, wherein the second current is less than the first current.
9. The primary controller of claim 7, wherein the supplemental power controller further comprises:
A delay timer configured to delay the assertion of the first control input of the first current source for a delay time after the monitor circuit asserts the first control output.
10. The primary controller of claim 9, wherein the supplemental power controller further comprises:
A control voltage sensor defining a sensor input and a sensor output, the sensor input coupled to the control voltage terminal, the control voltage sensor configured to measure a control voltage on the control voltage terminal and validate the sensor output when the control voltage is greater than a first control voltage threshold;
a monitor circuit defining a third control output, the monitor circuit configured to validate the third control output when the input voltage is less than a reference voltage;
a valley timer configured to determine a valley time as a length of time from when the monitoring circuit validates the first control output until when the monitoring circuit validates the third control output;
A switching power supply timer configured to record a power supply time interval from an assertion of the first control input of the first current source until the sensor output of the control voltage sensor; and
Wherein the delay time is half the valley time minus the power supply time interval.
11. The primary controller of claim 10, wherein the supplemental power controller further comprises:
A delay time adjuster configured to change a length of the delay time between assertion of the first control input of the first current source after assertion of the first control output by the monitoring circuit;
wherein the primary controller further comprises at least one of:
A timeout comparator defining a timeout output, the timeout comparator configured to validate the timeout output in response to the power-on interval being greater than a predetermined on-time;
A consumption monitor defining a consumption output, the consumption monitor configured to validate the consumption output when the primary controller is in a high consumption mode; or (b)
An input amplitude sensor defining an amplitude variation output, the input amplitude sensor configured to validate the amplitude variation output in response to the amplitude of the input voltage varying by more than a predetermined amount over a predetermined period of time;
A valley absence sensor defining a valley absence output, the valley absence sensor configured to validate the valley absence output and not present the third control output in response to passing the power supply time interval from validation of the first control input of the first current source until the sensor output of the control voltage sensor; and
Wherein the delay time adjuster is configured to change the length of the delay time in response to at least one of: the timeout output, or the consumption output, or the amplitude variation output, or the valley absence output.
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