CN110634436B - Grid driving circuit and display panel - Google Patents
Grid driving circuit and display panel Download PDFInfo
- Publication number
- CN110634436B CN110634436B CN201910917547.0A CN201910917547A CN110634436B CN 110634436 B CN110634436 B CN 110634436B CN 201910917547 A CN201910917547 A CN 201910917547A CN 110634436 B CN110634436 B CN 110634436B
- Authority
- CN
- China
- Prior art keywords
- signal
- pull
- node
- circuit
- compensation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention relates to the technical field of display, and provides a grid driving circuit and a display device. The driving circuit is arranged in a wiring area of the display panel and used for providing a grid driving signal for a grid line of the display panel; the compensation circuit is arranged in a display area of the display panel and used for providing compensation signals for grid lines of the display panel. The gate driving circuit provided by the disclosure can reduce the frame width of the display panel on the premise of satisfying the gate driving capability of the display panel.
Description
Technical Field
The invention relates to the technical field of display, in particular to a gate driving circuit and a display panel.
Background
The display panel generally includes a gate driving circuit for supplying a gate driving signal to gate lines of the display panel. In a conventional display panel, a gate driving circuit is usually integrated at a frame position of the display panel. Due to the voltage drop and parasitic capacitance of the gate line, the gate driving signal received by the sub-pixel unit far away from the gate driving circuit has the phenomenon of increasing the width of the falling edge, so that the data signal of the current row may be mistakenly flushed to the sub-pixel unit of the next row.
In the related art, the gate driving circuit includes an output circuit, and the turn-on capability of a transistor in the output circuit can be enhanced by increasing the size of the transistor, so as to reduce the width of the falling edge of the gate driving signal.
However, increasing the size of the transistors in the output circuit increases the size of the gate driving circuit, thereby increasing the width of the display panel.
It is to be noted that the information invented in the above background section is only for enhancing the understanding of the background of the present invention, and therefore, may include information which does not constitute prior art known to those skilled in the art.
Disclosure of Invention
The invention aims to provide a gate driving circuit and a display panel. The gate driving circuit can solve the technical problem that the falling edge width of a gate driving signal received by a sub-pixel unit far away from a source driving circuit in the related art is wide.
Additional features and advantages of the invention will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the invention.
According to an aspect of the present invention, there is provided a gate driving circuit for driving a display panel, the display panel including a display region and a routing region located around the display region, the gate driving circuit including a driving circuit and a compensation circuit. The driving circuit is used for providing a grid driving signal for grid lines of the display panel; the compensation circuit is arranged in a display area of the display panel and used for providing compensation signals for grid lines of the display panel.
In an exemplary embodiment of the present invention, the compensation circuit includes a plurality of sub-compensation circuits, the sub-compensation circuits are disposed in one-to-one correspondence with the gate lines in each row, each sub-compensation circuit includes a first switch unit, a second switch unit, and a first capacitor, the first switch unit is connected to a last gate line, a first node, and a first control signal terminal, and is configured to transmit a signal of the last gate line to the first node in response to a signal of the first control signal terminal; the second switch unit is connected with the first node, the compensation signal end and the grid line of the current row and is used for responding to the signal of the first node and transmitting the compensation signal of the compensation signal end to the grid line of the current row; the first capacitor is connected between the first node and the grid line of the current row.
In one exemplary embodiment of the present invention, the driving circuit includes a plurality of shift register units cascaded; the shift register unit comprises a first output circuit, wherein the first output circuit is connected with a pull-up node, a first clock signal end and a first output end and is used for responding to a signal of the pull-up node to transmit a signal of the first clock signal end to the first output end; the first control signal end of the line sub-compensation circuit and the first clock signal end of the first output circuit in the previous line have the same time sequence signal, and the compensation signal end of the line sub-compensation circuit and the first clock signal end of the first output circuit in the current line have the same time sequence signal.
In an exemplary embodiment of the present invention, the shift register unit further includes an input circuit, a second output circuit, an inverter, a pull-down circuit, and a reset circuit. The input circuit is connected with an input signal end, a first power supply signal end and a pull-up node and is used for responding to a signal of the input signal end and transmitting a signal of the first power supply signal end to the pull-up node; the second output circuit is connected with a pull-up node, a second clock signal end and a second output end and used for responding to a signal of the pull-up node to transmit a signal of the second clock signal end to the second output end, wherein the time sequence of the second clock signal end is the same as that of the first clock signal end; the input end of the phase inverter is connected with the pull-up node, and the output end of the phase inverter is connected with the pull-down node; the pull-down circuit is connected with the pull-down node, the first output end, the second output end, the pull-up node and the second power signal end and is used for responding to a signal of the pull-down node and transmitting a signal of the second power signal end to the first output end, the second output end and the pull-up node; the reset circuit is connected with the second power supply signal end, the pull-up node and the reset signal end and used for responding to the signal of the reset signal end to transmit the signal of the second power supply signal end to the pull-up node.
In an exemplary embodiment of the present invention, the input circuit includes a third switching unit connected to the input signal terminal, the first power signal terminal, and a pull-up node for transmitting a signal of the first power signal terminal to the pull-up node in response to a signal of the input signal terminal.
The first output end circuit comprises a fourth switching unit and a second capacitor, wherein the fourth switching unit is connected with a pull-up node, a first clock signal end and a first output end and is used for responding to a signal of the pull-up node and transmitting a signal of the first clock signal end to the first output end; the second capacitor is connected between the first output end and the pull-up node.
The second output circuit comprises a fifth switch unit, wherein the fifth switch unit is connected with a pull-up node, a second clock signal end and a second output end and is used for responding to a signal of the pull-up node to transmit a signal of the second clock signal end to the second output end.
The pull-down circuit comprises a sixth switch unit, a seventh switch unit and an eighth switch unit. The sixth switching unit is connected with the pull-down node, the second power supply signal end and the first output end, and is used for responding to the signal of the pull-down node and transmitting the signal of the second power supply signal end to the first output end; the seventh switching unit is connected to the pull-down node, a second power signal terminal and a second output terminal, and is configured to respond to the signal of the pull-down node to transmit the signal of the second power signal terminal to the second output terminal; the eighth switching unit is connected to the pull-down node, the second power signal terminal and the pull-up node, and configured to transmit a signal of the second power signal terminal to the pull-up node in response to a signal of the pull-down node;
the reset circuit comprises a ninth switch unit, wherein the ninth switch unit is connected with the second power supply signal end, the pull-up node and the reset signal end and is used for responding to a signal of the reset signal end to transmit a signal of the second power supply signal end to the pull-up node.
In an exemplary embodiment of the present invention, the compensation circuit is disposed on a side away from the driving circuit.
In an exemplary embodiment of the present invention, the driving circuit includes a first driving circuit and a second driving circuit located at opposite sides of the routing area, and the compensation circuit is disposed at a middle position between the first driving circuit and the second driving circuit.
In an exemplary embodiment of the present invention, the display area of the display panel includes a plurality of sub-pixel units, and the compensation circuit is disposed in the sub-pixel units.
In one exemplary embodiment of the present invention, the sub-pixel unit provided with the compensation circuit is driven by a pixel driving circuit in an adjacent sub-pixel unit.
According to an aspect of the present invention, a display panel is provided, which includes the gate driving circuit.
The utility model provides a grid drive circuit, display panel, this grid drive circuit is used for driving display panel, display panel includes the display area and is located wiring area around the display area, and this grid drive circuit includes drive circuit, compensating circuit. The driving circuit is used for providing a grid driving signal for grid lines of the display panel; the compensation circuit is arranged in a display area of the display panel and used for providing compensation signals for grid lines of the display panel. On one hand, the compensation circuit can compensate the grid driving signal on the grid line, so that the falling edge of the grid driving signal on the side, far away from the driving circuit, of the grid line is prevented from widening, the grid driving circuit does not need to be provided with a transistor with an overlarge size, and the frame width of the display panel is reduced on the premise that the grid driving capability of the display panel is met; on the other hand, the compensation circuit can also compensate the voltage of the gate driving signal, so that the technical problem that the voltage of the gate driving signal on the side of the gate line far away from the driving circuit is low is solved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
FIG. 1 is a diagram of a shift register unit according to the related art;
FIG. 2 is a schematic diagram of a gate driving circuit in the related art;
FIG. 3 is a timing diagram of nodes of a shift register unit according to the related art;
FIG. 4 is a schematic diagram of an exemplary embodiment of a gate driving circuit according to the present disclosure;
FIG. 5 is a schematic diagram of an exemplary embodiment of a gate driving circuit according to the present disclosure;
FIG. 6 is a schematic diagram of a driving circuit in a compensation circuit according to an exemplary embodiment of the gate driving circuit of the present disclosure;
FIG. 7 is a schematic diagram of an exemplary embodiment of a gate driving circuit according to the present disclosure;
FIG. 8 is a schematic diagram of an exemplary embodiment of a gate driving circuit according to the present disclosure;
fig. 9 is a schematic structural diagram of an exemplary embodiment of the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus a detailed description thereof will be omitted.
Although relative terms, such as "upper" and "lower," may be used herein to describe one element of an icon relative to another, these terms are used herein for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". Other relative terms, such as "high," "low," "top," "bottom," "left," "right," and the like are also intended to have similar meanings. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," and the like are used to denote the presence of one or more elements/components/parts/or the like; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.
As shown in fig. 1, the shift register unit in the related art includes a first transistor T1, a second transistor T2, a third transistor T3, a third transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a capacitor C, and an inverter PI. The first output terminal OUT1 inputs a gate driving signal to the gate line, and the second output terminal OUT2 is used for cascading with other shift register units.
Fig. 2 is a schematic structural diagram of a gate driving circuit in the related art, where the gate driving circuit includes a plurality of cascaded shift register units GOA shown in fig. 1. The second output end OUT2 of the nth stage shift register unit is connected to the signal input end STV of the (n + 1) th stage shift register; the second output end of the (n + 3) th stage shift register unit is connected with the reset signal end RST of the nth stage shift register unit, and n is an integer greater than or equal to 1. The gate driving circuit supplies a clock signal to a clock signal terminal CLKA of the shift register unit through four clock signal lines CLKA1, CLKA2, CLKA3, CLKA 4. The clock signal line CLKA1 is connected to the 4 th +1 th stage shift register unit, the clock signal line CLKA2 is connected to the 4 th +2 th stage shift register unit, the clock signal line CLKA3 is connected to the 4 th +3 th stage shift register unit, the clock signal line CLKA4 is connected to the 4 th +4 th stage shift register unit, and m is an integer greater than or equal to 0. The gate driving circuit supplies a clock signal to a clock signal terminal CLKB of the shift register unit through four clock signal lines CLKB1, CLKB2, CLKB3, CLKB 4. The clock signal line CLKB1 is connected to the 4m +1 th stage shift register unit, the clock signal line CLKB2 is connected to the 4m +2 th stage shift register unit, the clock signal line CLKB3 is connected to the 4m +3 th stage shift register unit, the clock signal line CLKB4 is connected to the 4m +4 th stage shift register unit, and m is an integer greater than or equal to 0.
Fig. 3 is a timing diagram of each node of a shift register unit in the related art. The shift register unit operation includes four stages: a charging phase T1, a pull-up phase T2, a pull-down phase T3, a reset phase T4. Taking the first stage shift register unit in fig. 2 as an example, in the charging stage T1, the input signal is an active level signal, CLKA1 and CLKB1 are inactive level signals, the transistor T1 is turned on, and the active power signal terminal VGH pre-flushes the active level signal to the capacitor C; in the pull-up stage T2, the input signal is an invalid level signal, CLKA1 and CLKB1 are valid level signals, transistors T2 and T3 are turned on under the action of the pull-up node PU, and the valid level signals of CLKA1 and CLKB1 are transmitted to the second output terminals OUT2 and OUT1 through transistors T3 and T2, respectively; in the pull-down stage T3, the pull-up node PU is at a low level, the pull-down node PD is at a high level, the transistors T4, T5 and T6 are turned on, and the inactive power signal terminal VGL transmits an inactive level signal to the pull-up node PU, the first output terminal OUT1 and the second output terminal OUT 2; in the reset period T4, the reset signal terminal RET is at the active level, the transistor T7 is turned on, and the inactive power signal terminal VGL transmits an inactive level signal to the pull-up node PU.
Because the gate line of the display panel has a voltage drop and a parasitic capacitance, the gate driving signal received by the sub-pixel unit far away from the gate driving circuit has a phenomenon of increasing the width of the falling edge, so that the data signal of the current row may be mistakenly rushed to the sub-pixel unit of the next row. In the related art, the on-capability of the transistor T2 is usually enhanced by increasing the size of the transistor, so as to reduce the width of the falling edge of the gate driving signal. However, increasing the size of the transistors in the output circuit increases the size of the gate driving circuit, thereby increasing the width of the display panel.
Based on this, the present exemplary embodiment provides a gate driving circuit, which is used for driving a display panel, where the display panel includes a display area 1 and a routing area 2 located around the display area, as shown in fig. 4, and is a schematic structural diagram of an exemplary embodiment of the gate driving circuit of the present disclosure. The gate driving circuit includes a driving circuit 3 and a compensation circuit 4. The driving circuit 3 is disposed in the wiring region 2 and configured to provide a gate driving signal to a gate line GL of the display panel; the compensation circuit 4 is disposed in the display region 1 of the display panel and configured to provide a compensation signal to a gate line of the display panel.
The present disclosure provides a gate driving circuit for driving a display panel, the display panel including a display region and a routing region located around the display region, the gate driving circuit including a driving circuit and a compensation circuit. The drive circuit is used for providing a grid drive signal for grid lines of the display panel; the compensation circuit is arranged in a display area of the display panel and used for providing compensation signals for grid lines of the display panel. On one hand, the compensation circuit can compensate the grid driving signal on the grid line, so that the falling edge of the grid driving signal on the side, far away from the driving circuit, of the grid line is prevented from widening, the grid driving circuit does not need to be provided with a transistor with an overlarge size, and the frame width of the display panel is reduced on the premise that the grid driving capability of the display panel is met; on the other hand, the compensation circuit can also compensate the voltage of the gate driving signal, so that the technical problem that the voltage of the gate driving signal on the side of the gate line far away from the driving circuit is low is solved.
In the present exemplary embodiment, as shown in fig. 5, a schematic structural diagram of an exemplary embodiment of the gate driving circuit of the present disclosure is shown. The compensation circuit comprises a plurality of sub-compensation circuits, the sub-compensation circuits are arranged in one-to-one correspondence with the gate lines GL in each row, each sub-compensation circuit comprises a first switch unit 5, a second switch unit 6 and a first capacitor C1, the first switch unit 5 is connected with the gate line in the previous row, a first node N1 and a first control signal terminal CN1, and is used for responding to a signal of the first control signal terminal CN1 to transmit a signal of the gate line in the previous row to the first node N1; the second switch unit 6 is connected to the first node N1, the compensation signal terminal CN2, and the gate line of the current row, and is configured to transmit the compensation signal of the compensation signal terminal CN2 to the gate line of the current row in response to the signal of the first node N1; the first capacitor C1 is connected between the first node and the gate line. The compensation circuit works in two stages: a pre-charge phase and a compensation phase. In the pre-charging stage, the last row of gate lines is in the stage of outputting gate driving signals, the first control signal terminal CN1 outputs an effective level signal to turn on the first switch unit, and the last row of gate lines is pre-charged to the first capacitor C1; in the compensation stage, the gate line of the current row is in the stage of outputting the gate driving signal, the second switch unit is turned on under the action of the first node, and the compensation signal terminal CN2 outputs an effective level signal to input the compensation signal to the gate line of the current row. In the present exemplary embodiment, as shown in fig. 5, the first and second switching units may be N-type switching transistors or P-type switching transistors.
In the present exemplary embodiment, as shown in fig. 6, a schematic structural diagram of a driving circuit in a compensation circuit in an exemplary embodiment of a gate driving circuit of the present disclosure is shown. The driving circuit may include a plurality of shift register units cascaded; the shift register unit includes a first output circuit 72, the first output circuit 72 is connected to a pull-up node PU, a first clock signal terminal CLKB, and a first output terminal OUT1, and is configured to transmit a signal of the first clock signal terminal CLKB to the first output terminal OUT1 in response to a signal of the pull-up node PU. As shown in fig. 6, the shift register unit may further include an input circuit 71, a second output circuit 73, an inverter PI, a pull-down circuit 74, and a reset circuit 75. The input circuit is connected with an input signal end STV, a first power supply signal end VGH and a pull-up node PU and is used for responding to a signal of the input signal end STV and transmitting a signal of the first power supply signal end VGH to the pull-up node PU; a second output circuit is connected with a pull-up node PU, a second clock signal terminal CLKA and a second output terminal OUT1, and is used for responding to the signal of the pull-up node PU to transmit the signal of the second clock signal terminal CLKA to the second output terminal OUT2, wherein the timing sequence of the second clock signal terminal CLKA is the same as that of the first clock signal terminal CLKA; the input end of the inverter PI is connected with the pull-up node PU, and the output end of the inverter PI is connected with the pull-down node PD; the pull-down circuit is connected with the pull-down node PD, the first output end OUT1, the second output end OUT2, the pull-up node PU and the second power supply signal end VGL, and is used for responding to a signal of the pull-down node PD, transmitting a signal of the second power supply signal end VGL to the first output end OUT1, the second output end OUT2 and the pull-up node PU; the reset circuit is connected with the second power supply signal end VGL, the pull-up node PU and the reset signal end RST and is used for responding to a signal of the reset signal end RST to transmit a signal of the second power supply signal end VGL to the pull-up node PU.
The shift register unit may have the same structure as the shift register unit in fig. 1. As shown in fig. 6, the input circuit includes a third switching unit T3, which is connected to the input signal terminal, the first power supply signal terminal VGH, and the pull-up node PU, for transmitting a signal of the first power supply signal terminal VGH to the pull-up node PU in response to a signal of the input signal terminal. The first output terminal OUT1 circuit comprises a fourth switch unit T4 and a second capacitor C2, the fourth switch unit is connected with a pull-up node PU, a first clock signal terminal CLKB, a first output terminal OUT1, and is used for transmitting the signal of the first clock signal terminal CLKB to the first output terminal OUT1 in response to the signal of the pull-up node PU; a second capacitor is connected between the first output terminal OUT1 and the pull-up node PU. The second output circuit includes a fifth switch unit T5 connected to a pull-up node PU, a second clock signal terminal CLKA, and a second output terminal OUT2, for transmitting a signal of the second clock signal terminal CLKA to the second output terminal OUT2 in response to a signal of the pull-up node PU. The pull-down circuit includes a sixth switching unit T6, a seventh switching unit T7, and an eighth switching unit T8. The sixth switching unit is connected to the pull-down node PD, the second power signal terminal VGL, and the first output terminal OUT1, and is configured to transmit a signal of the second power signal terminal VGL to the first output terminal OUT1 in response to a signal of the pull-down node PD; the seventh switching unit is connected to the pull-down node PD, a second power signal terminal VGL, and a second output terminal OUT2, and is configured to transmit a signal of the second power signal terminal VGL to the second output terminal OUT2 in response to a signal of the pull-down node PD; the eighth switching unit is connected to the pull-down node PD, the second power signal terminal VGL, and the pull-up node PU, and configured to transmit a signal of the second power signal terminal VGL to the pull-up node PU in response to a signal of the pull-down node PD; the reset circuit comprises a ninth switch unit, the ninth switch unit is connected with the second power supply signal end VGL, the pull-up node PU and the reset signal end, and is used for responding to the signal of the reset signal end to transmit the signal of the second power supply signal end VGL to the pull-up node PU. The third to ninth switching units may be switching transistors.
In the exemplary embodiment, the first control signal terminal CN1 of the present row sub compensation circuit and the first clock signal terminal CLK of the previous row first output circuit have the same timing signal, and the compensation signal terminal CN2 of the present row sub compensation circuit and the first clock signal terminal CLKB of the present row first output circuit have the same timing signal. For example, in the present exemplary embodiment, the structure and driving timing of the driving circuit may be the same as those of the driving circuit shown in fig. 2, as shown in fig. 7, which is a schematic structural diagram of an exemplary embodiment of the gate driving circuit of the present disclosure, in which the first control signal terminal CN1 of the second row sub-compensation circuit and the clock signal line CLKB1 of the first row first output circuit have the same timing signal, and the compensation signal terminal CN2 of the second row sub-compensation circuit and the clock signal line CLKB2 of the second row first output circuit have the same timing signal. By analogy, the first control signal terminal CN1 of the third row of sub-compensation circuits and the clock signal line CLKB2 of the second row of first output circuits have the same timing signals, and the compensation signal terminal CN2 of the third row of sub-compensation circuits and the clock signal line CLKB3 of the third row of first output circuits have the same timing signals.
In the present exemplary embodiment, the compensation circuit is disposed on a side away from the driving circuit. For example, as shown in fig. 8, a schematic structural diagram of an exemplary embodiment of the gate driving circuit of the present disclosure is shown. When the driving circuit includes a first driving circuit 31 and a second driving circuit 32 located at two opposite sides of the wiring area, the compensation circuit 4 is disposed at a middle position of the first driving circuit 31 and the second driving circuit 32. For another example, as shown in fig. 4, when the driving circuit 3 is disposed on one side of the display panel, the compensation circuit 4 may be disposed on one side of the display region away from the driving circuit 3.
In the present exemplary embodiment, as shown in fig. 9, which is a schematic structural diagram of an exemplary embodiment of the present disclosure, a display area of the display panel includes a plurality of sub-pixel units 8, and each sub-pixel unit 8 includes a pixel driving circuit area 82 provided with a pixel driving circuit, and a light emitting unit area 81 provided with a light emitting unit R, G, B, W. The compensation circuit may be disposed in the pixel driving circuit region 82 within the sub-pixel unit. Wherein the sub-pixel unit provided with the compensation circuit can be driven by the pixel driving circuit in the adjacent sub-pixel unit.
The present exemplary embodiment also provides a display panel including the gate driving circuit described above.
The display panel provided by the present disclosure has the same technical features and working principles as the gate driving circuit, and the details have been already described above, and are not described herein again.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is to be limited only by the terms of the appended claims.
Claims (9)
1. A gate driving circuit for driving a display panel, the display panel including a display region and a routing region located around the display region, comprising:
the driving circuit is arranged in the wiring area and used for providing gate driving signals to different grid lines of the display panel line by line at different time intervals;
the compensation circuit is arranged in the display area and used for providing compensation signals for grid lines of the display panel;
the compensation circuit comprises a plurality of sub-compensation circuits, the sub-compensation circuits are arranged corresponding to the grid lines in each row one by one, and the sub-compensation circuits comprise:
a first switching unit connected to a previous row of gate lines, a first node, and a first control signal terminal, for transmitting a signal of the previous row of gate lines to the first node in response to a signal of the first control signal terminal;
the second switch unit is connected with the first node, the compensation signal end and the grid line of the line and used for responding to the signal of the first node to transmit the compensation signal of the compensation signal end to the grid line of the line;
and the first capacitor is connected between the first node and the grid line of the current row.
2. A gate drive circuit according to claim 1, wherein the drive circuit comprises a cascade of a plurality of shift register cells;
the shift register unit comprises a first output circuit, wherein the first output circuit is connected with a pull-up node, a first clock signal end and a first output end and is used for responding to a signal of the pull-up node to transmit a signal of the first clock signal end to the first output end;
the first control signal end of the line sub-compensation circuit and the first clock signal end of the first output circuit in the previous line have the same time sequence signal, and the compensation signal end of the line sub-compensation circuit and the first clock signal end of the first output circuit in the current line have the same time sequence signal.
3. The gate driving circuit according to claim 2, wherein the shift register unit further comprises:
the input circuit is connected with an input signal end, a first power supply signal end and a pull-up node and is used for responding to a signal of the input signal end and transmitting a signal of the first power supply signal end to the pull-up node;
the second output circuit is connected with a pull-up node, a second clock signal end and a second output end and used for responding to a signal of the pull-up node to transmit a signal of the second clock signal end to the second output end, wherein the time sequence of the second clock signal end is the same as that of the first clock signal end;
the input end of the inverter is connected with the pull-up node, and the output end of the inverter is connected with the pull-down node;
the pull-down circuit is connected with the pull-down node, the first output end, the second output end, the pull-up node and the second power signal end and is used for responding to a signal of the pull-down node and transmitting a signal of the second power signal end to the first output end, the second output end and the pull-up node;
and the reset circuit is connected with the second power signal end, the pull-up node and the reset signal end and is used for responding to the signal of the reset signal end and transmitting the signal of the second power signal end to the pull-up node.
4. A gate drive circuit as claimed in claim 3,
the input circuit includes:
the third switching unit is connected with the input signal terminal, the first power supply signal terminal and a pull-up node and is used for responding to a signal of the input signal terminal to transmit a signal of the first power supply signal terminal to the pull-up node;
the first output-side circuit includes:
the fourth switch unit is connected with a pull-up node, a first clock signal end and a first output end and used for responding to a signal of the pull-up node to transmit a signal of the first clock signal end to the first output end;
the second capacitor is connected between the first output end and the pull-up node;
the second output circuit includes:
the fifth switch unit is connected with a pull-up node, a second clock signal end and a second output end and used for responding to the signal of the pull-up node to transmit the signal of the second clock signal end to the second output end;
the pull-down circuit includes:
the sixth switching unit is connected with the pull-down node, a second power supply signal end and a first output end, and is used for responding to a signal of the pull-down node to transmit a signal of the second power supply signal end to the first output end;
the seventh switch unit is connected with the pull-down node, a second power supply signal end and a second output end, and is used for responding to the signal of the pull-down node to transmit the signal of the second power supply signal end to the second output end;
the eighth switch unit is connected with the pull-down node, the second power supply signal end and the pull-up node, and is used for responding to the signal of the pull-down node and transmitting the signal of the second power supply signal end to the pull-up node;
the reset circuit includes:
and the ninth switch unit is connected with the second power signal end, the pull-up node and the reset signal end and is used for responding to the signal of the reset signal end to transmit the signal of the second power signal end to the pull-up node.
5. A gate driver circuit as claimed in claim 1, wherein the compensation circuit is disposed on a side away from the driver circuit.
6. A gate driver circuit as claimed in claim 1, wherein the driver circuit comprises a first driver circuit and a second driver circuit disposed on opposite sides of the routing region, and the compensation circuit is disposed in the middle of the first driver circuit and the second driver circuit.
7. A gate driving circuit as claimed in claim 1, wherein the display area of the display panel comprises a plurality of sub-pixel units, and the compensation circuit is disposed in the sub-pixel units.
8. The gate drive circuit of claim 1,
the sub-pixel unit provided with the compensation circuit is driven by the pixel driving circuit in the adjacent sub-pixel unit.
9. A display panel comprising the gate driver circuit according to any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910917547.0A CN110634436B (en) | 2019-09-26 | 2019-09-26 | Grid driving circuit and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910917547.0A CN110634436B (en) | 2019-09-26 | 2019-09-26 | Grid driving circuit and display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110634436A CN110634436A (en) | 2019-12-31 |
| CN110634436B true CN110634436B (en) | 2022-09-23 |
Family
ID=68973036
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910917547.0A Active CN110634436B (en) | 2019-09-26 | 2019-09-26 | Grid driving circuit and display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110634436B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111223449B (en) * | 2020-03-23 | 2021-04-27 | 合肥京东方显示技术有限公司 | Display panel, driving method thereof and display device |
| CN111564132A (en) * | 2020-05-29 | 2020-08-21 | 厦门天马微电子有限公司 | Shift register, display panel and display device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103280201A (en) * | 2013-04-27 | 2013-09-04 | 京东方科技集团股份有限公司 | Grid driving device and display device |
| CN103366690A (en) * | 2012-03-30 | 2013-10-23 | 群康科技(深圳)有限公司 | An image display system and a display panel |
| CN104952409A (en) * | 2015-07-07 | 2015-09-30 | 京东方科技集团股份有限公司 | Gate drive unit, drive method of gate drive unit, gate drive circuit and display device |
| CN106356015A (en) * | 2016-10-31 | 2017-01-25 | 合肥鑫晟光电科技有限公司 | Shifting register, driving method and display device |
| CN108597438A (en) * | 2018-07-03 | 2018-09-28 | 京东方科技集团股份有限公司 | Shift register cell, gate driving circuit and its driving method, display device |
| CN110010078A (en) * | 2019-03-14 | 2019-07-12 | 合肥京东方卓印科技有限公司 | Shift register cell, gate driving circuit and display device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI330820B (en) * | 2006-01-26 | 2010-09-21 | Au Optronics Corp | Flat panel display and display panel thereof |
| KR101154338B1 (en) * | 2006-02-15 | 2012-06-13 | 삼성전자주식회사 | Shift register, and scan drive circuit and display device having the same |
| BRPI0822030A2 (en) * | 2008-01-24 | 2015-07-21 | Sharp Kk | Monitor device and method for triggering monitor device |
| KR102191977B1 (en) * | 2014-06-23 | 2020-12-18 | 엘지디스플레이 주식회사 | Scan Driver and Display Device Using the same |
| CN107731170B (en) * | 2017-10-31 | 2020-03-17 | 京东方科技集团股份有限公司 | Compensation module, gate driving unit, circuit, driving method of circuit and display device |
| CN109616041B (en) * | 2019-02-13 | 2021-04-16 | 合肥京东方卓印科技有限公司 | Shifting register unit, driving method, grid driving circuit and display device |
-
2019
- 2019-09-26 CN CN201910917547.0A patent/CN110634436B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103366690A (en) * | 2012-03-30 | 2013-10-23 | 群康科技(深圳)有限公司 | An image display system and a display panel |
| CN103280201A (en) * | 2013-04-27 | 2013-09-04 | 京东方科技集团股份有限公司 | Grid driving device and display device |
| CN104952409A (en) * | 2015-07-07 | 2015-09-30 | 京东方科技集团股份有限公司 | Gate drive unit, drive method of gate drive unit, gate drive circuit and display device |
| CN106356015A (en) * | 2016-10-31 | 2017-01-25 | 合肥鑫晟光电科技有限公司 | Shifting register, driving method and display device |
| CN108597438A (en) * | 2018-07-03 | 2018-09-28 | 京东方科技集团股份有限公司 | Shift register cell, gate driving circuit and its driving method, display device |
| CN110010078A (en) * | 2019-03-14 | 2019-07-12 | 合肥京东方卓印科技有限公司 | Shift register cell, gate driving circuit and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110634436A (en) | 2019-12-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20190206503A1 (en) | Shift register and method of driving the same, gate driving circuit and display device | |
| US20190156778A1 (en) | Shift register unit, gate driving circuit, and driving method | |
| US20160125955A1 (en) | Shift Register, Driving Method Thereof and Gate Driving Circuit | |
| JP3851302B2 (en) | Buffer circuit and active matrix display device using the same | |
| US20150302936A1 (en) | Shift register unit, gate driving circuit, and display device | |
| US20170309243A1 (en) | Shift register unit and driving method thereof, gate driving apparatus and display apparatus | |
| CN110120200B (en) | Display device | |
| US20120133392A1 (en) | Multiplex gate driving circuit | |
| CN110797070B (en) | Shift register and display panel | |
| KR20080008800A (en) | Shift registers for gate driver of flat panel displays | |
| CN109616041B (en) | Shifting register unit, driving method, grid driving circuit and display device | |
| US20150161958A1 (en) | Gate driver | |
| EP3742424B1 (en) | Shift register, driving method therefor and gate drive circuit | |
| CN110634436B (en) | Grid driving circuit and display panel | |
| CN111429830A (en) | Shifting register unit and driving method thereof, grid driving circuit and display panel | |
| CN101393775B (en) | Shift register | |
| CN112542198A (en) | Shift register and display panel | |
| US6630930B2 (en) | Drive circuit and display unit for driving a display device and portable equipment | |
| CN111243649B (en) | Shift register unit and display panel | |
| CN110189676B (en) | Shifting register unit, driving method, grid driving circuit and display panel | |
| CN109741700B (en) | Shift register unit and driving method | |
| KR101346901B1 (en) | Liquid crystal display device | |
| US11908373B2 (en) | Display driving circuit and display device | |
| CN110111717B (en) | Gate drive circuit, gate drive method, array substrate and display panel | |
| US20220309988A1 (en) | Gate driving circuit and display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |