CN110632588B - Zero intermediate frequency secondary radar direct current offset compensation algorithm based on FPGA - Google Patents
Zero intermediate frequency secondary radar direct current offset compensation algorithm based on FPGA Download PDFInfo
- Publication number
- CN110632588B CN110632588B CN201910870508.XA CN201910870508A CN110632588B CN 110632588 B CN110632588 B CN 110632588B CN 201910870508 A CN201910870508 A CN 201910870508A CN 110632588 B CN110632588 B CN 110632588B
- Authority
- CN
- China
- Prior art keywords
- noise
- data
- offset
- secondary radar
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/74—Systems using reradiation of radio waves, e.g. secondary radar systems; Analogous systems
- G01S13/76—Systems using reradiation of radio waves, e.g. secondary radar systems; Analogous systems wherein pulse-type signals are transmitted
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/74—Systems using reradiation of radio waves, e.g. secondary radar systems; Analogous systems
- G01S13/76—Systems using reradiation of radio waves, e.g. secondary radar systems; Analogous systems wherein pulse-type signals are transmitted
- G01S13/767—Responders; Transponders
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
Landscapes
- Engineering & Computer Science (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Radar Systems Or Details Thereof (AREA)
Abstract
The invention relates to the field of signal processing, and discloses a zero intermediate frequency secondary radar direct current offset compensation algorithm based on an FPGA (field programmable gate array). according to the characteristics of noise and signals in a secondary radar system, a corresponding data model is established, a data discrimination sliding window is designed, the type (noise or signal) of input baseband data is identified, and direct current offset carried by an I/Q (input/output) path in the baseband data is accurately extracted and eliminated in real time. The invention can effectively and accurately restore the amplitude-phase characteristics of signals in baseband data in real time on the premise that data output by the ADC is not saturated; the problems of system identification probability reduction, high false alarm rate, detection precision reduction and the like caused by direct current bias are solved while other adverse effects on the system are avoided, and the reliability of secondary radar equipment is improved.
Description
Technical Field
The invention relates to the field of signal processing, in particular to a zero intermediate frequency secondary radar direct current offset compensation algorithm based on an FPGA.
Background
Zero Intermediate Frequency (ZIF) architectures have emerged since the inception of the radio, which have the advantages of lowest cost, lowest power consumption, and smallest size. With the development of scientific technology, a plurality of common defects existing in the early stage of a zero intermediate frequency architecture can be solved through the combination of process, design, partition and algorithm, so that a new product brought by the method achieves breakthrough in performance, the novel application of the traditional technology which is expected to be dusty can be realized, and inevitably, some problems also exist in the zero intermediate frequency architecture, including flicker noise (1/f), direct current offset (DC-offset), I/Q imbalance, even harmonic and the like. Only the problem and solution of dc biasing is described herein.
The zero intermediate frequency receiver converts the radio frequency signal to zero intermediate frequency, a large amount of bias voltage can deteriorate the signal, and more seriously, the direct current bias signal can cause the saturation of the mixing rear stage, signal distortion and the like.
Local oscillator leakage appears as an increased dc offset in the I or Q signal path. The reason for this is that the LO is coupled directly into the radio frequency signal path and is down-converted to the output in a coherent manner. The result is a mixer product, which appears as a dc offset, added to any residual dc offset present in the signal chain, as shown in fig. 1 a.
The isolation between the local oscillator port, the mixer port and the LNA is poor, local oscillator signals, environmental electromagnetic interference signals and the like can directly pass through the LNA and the mixer, and the phenomenon that local oscillator leakage occurs is that the coupled local oscillator signals and interference signals reach the mixer through the LNA due to coupling of a capacitor and a substrate in a chip and are mixed (self-mixing) with the input local oscillator signals, so that direct current components are generated behind the low-pass filter; in the similar case as in fig. 1b, the signal from the LNA, the jammer signal, is coupled to the local oscillator input of the mixer, thereby generating a dc component.
The method for eliminating the direct current offset comprises a mode of compensating data by using an algorithm calibration and a demodulation chip calibration compensation interface, a mode of combining the algorithm calibration and the demodulation chip calibration compensation interface, and the like.
The blind calibration method of representative TI company is briefly described.
Direct current accumulation:
updating the direct current bias:
ΔOffset＝2-shift·OffsetACC
updating and counting direct current offset:
Offset(n+1)＝Offset(n)+ΔOffset
DC offset compensation:
y(i)＝x(i)-Offset(n)
the way in which the demodulation chip self-calibration interface is used for compensation is shown in fig. 2.
The existing scheme for solving the problem of direct current offset is basically based on direct statistics of baseband data, channel direct current offset extraction and one-time or cyclic compensation.
The defect of a one-off compensation mode is very obvious, and fixed parameter compensation can only solve the direct current bias caused by local oscillator leakage to a certain extent, but cannot solve the direct current bias caused by factors such as equipment electromagnetic environment change and the like.
The cyclic compensation method needs to extract the dc offset accurately, and needs to count a large amount of data to implement the cyclic compensation method, so that the dc cancellation process is slow, and the influence of the signal on the dc offset extraction cannot be avoided, which causes an error between the actually obtained dc offset value and the true value, which is shown in the dc cancellation effect that a small offset may still exist after the cancellation is completed, that is, the cancellation is not thorough.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the existing problems, the zero intermediate frequency secondary radar direct current offset compensation algorithm based on the FPGA is provided, a corresponding model is established according to the characteristics of noise and signals in a secondary radar system, a data discrimination sliding window is designed, the type (noise and signals) of input data is identified, direct current offset carried by an I/Q path in baseband data is accurately extracted and eliminated in real time, and the reliability and the stability of equipment are improved.
The technical scheme adopted by the invention is as follows: the utility model provides a zero intermediate frequency secondary radar DC offset compensation algorithm based on FPGA which characterized in that includes:
step 1: establishing a corresponding noise data model and a corresponding signal data model according to the characteristics of noise data and signal data in a secondary radar system;
step 2: designing a data type discrimination sliding window model according to the noise data model and the signal data model, wherein a data cache space is arranged in the data type discrimination sliding window model, and a bias attribute is defined for each group of data input into the data cache space;
and step 3: sequentially inputting N groups of zero intermediate frequency secondary radar baseband data into a data type discrimination sliding window model, transferring N groups of data into an original cache library for caching, and then identifying and judging the types of the N groups of input data according to the offset attribute of the input data; n is a natural number more than or equal to 1;
and 4, step 4: if the noise data exist in the N groups of input data judged in the sliding window, the noise data are moved into a noise cache library from an original cache library for caching;
if signal data exist in the N groups of input data judged in the sliding window, the signal data are removed from an original cache library; after the signal data are eliminated, noise mean value of the noise data in the noise buffer library at the previous moment is calculated to be used as substitute data of the signal data, and the substitute data is transferred into the noise buffer library for buffering;
and 5: calculating the mean value of all noise data in the current noise cache library, and defining the mean value as a direct current offset value carried in current secondary radar baseband data;
step 6: and subtracting the quantization values of the N groups of secondary radar baseband data before being input into the sliding window model from the extracted direct current offset value to eliminate the direct current offset and output data.
Further, in step 1, the noise data model and the signal data model include: and the secondary radar system receives a noise model, a secondary radar response signal model and a noise model carrying direct current offset in channel baseband data.
Further, in step 2, the detailed process of defining the bias attribute is as follows:
when the input data is larger than the noise maximum positive offset value, indicating that the input data is positive offset;
when the input data is smaller than the maximum negative bias value of the noise, the input data is represented as negative bias;
when the input data is greater than or equal to the noise maximum negative bias value and less than or equal to the noise maximum positive bias value, the input data is not positively biased or negatively biased.
Further, the process of calculating the maximum positive offset and the maximum negative offset of the noise is divided into two cases:
if the noise data does not exist in the current noise cache library, the initial noise data group is input in a user-defined mode and the average value of the initial noise data group is obtained to serve as the initial noise average value; extracting maximum noise data in the custom noise data group as a noise maximum value; extracting minimum noise data in the custom noise data group as a noise minimum value;
the expression of the maximum noise positive offset value is as follows:
NMPOinit＝MAXnoise+AVAnoise；
the expression of the maximum negative offset value of the noise is as follows:
NMNOinit＝MINnoise-AVAnoise；
wherein, NMPOinitRepresenting the maximum positive offset value of the initial noise, NMNOinitRepresenting the maximum negative offset, AVA, of the initial noisenoiseRepresenting the mean value of the noise, MAXnoiseRepresenting the initial noise maximum, MINnoiseRepresents the initial noise minimum;
if the noise data exists in the current noise cache library, averaging the noise data in the current noise cache library to be used as a real-time noise average value;
the expression of the maximum positive offset value of the real-time noise is as follows:
xMPO(n)＝mN(n)+NMPOinit；
the expression of the maximum negative offset value of the real-time noise is as follows:
xMNO(n)＝mN(n)-NMNOinit；
wherein x isMPO(n) represents the maximum positive offset value of real-time noise, xMNO(n) represents the maximum negative bias value of real-time noise, mN(n) means real time noise mean, NMPOinitRepresenting the maximum positive offset value of the initial noise, NMNOinitRepresenting the initial noise maximum negative bias value.
Further, in step 3, the detailed process of data determination is as follows:
if the N groups of input data are all represented as positive bias or negative bias in the sliding window, the N groups of input data are all noise data carrying direct current bias;
if the N groups of input data are not represented as positive offset or negative offset in the sliding window, the N groups of input data are all noise data which do not carry direct current offset;
if the N groups of input data are partially presented as positive bias and partially presented as negative bias in the sliding window, and the rest of the input data are not presented as positive bias or negative bias, the signal data in the N groups of input data are present.
Further, in the detailed process of the data determination, if it is identified that the data carries the dc offset, a cancellation flag is set on the data to indicate a state of the dc cancellation process.
Further, the width of a sliding window of the data type discrimination sliding window model is larger than the effective pulse width of the secondary radar response signal.
Furthermore, the algorithm is described by a Verilog language and is configured into an FPGA for implementation.
Compared with the prior art, the beneficial effects of adopting the technical scheme are as follows: aiming at the defects of the existing direct current bias processing scheme, the invention provides a direct current bias accurate compensation algorithm based on an FPGA (field programmable gate array), which can be used for efficiently and accurately restoring the amplitude-phase characteristics of signals in baseband data in real time on the premise that data output by an ADC (analog to digital converter) is not saturated, ensuring that other adverse effects on a system are not brought, solving the problems of reduced system identification probability, high false alarm rate, reduced detection accuracy and the like caused by direct current bias and improving the reliability of secondary radar equipment.
Drawings
Fig. 1a and 1b are schematic diagrams of dc offset generation for a zero if architecture;
FIG. 2 is a schematic diagram of a demodulation chip self-calibration interface compensation mode;
FIG. 3 is a DC compensation algorithm architecture based on FPGA of the present invention;
FIG. 4 is a secondary radar response signal format;
FIG. 5 is a simulation diagram of the process of eliminating DC offset by the present algorithm.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
Example 1
As shown in fig. 3, a zero intermediate frequency secondary radar dc offset compensation algorithm based on FPGA includes the following steps.
Firstly, establishing a corresponding data model according to the characteristics of noise data and signal data in a secondary radar system, namely, positive bias or negative bias of continuous data change;
preferably, the data model comprises: and the secondary radar system receives a noise model, a secondary radar response signal model and a noise model carrying direct current offset in channel baseband data.
A noise model in the baseband data of a receiving channel of the secondary radar system is as follows:
additive white Gaussian noise can be defined as a mathematical model of the noise in the baseband signal of the receiving channel of a secondary radar device, and the orthogonal component n of the mathematical modelI(t) and nQ(t) is uncorrelated zero mean gaussian noise with equal variance.
Secondary radar response signal model:
as shown in fig. 4, according to the requirement of the international civil aviation accessory ten, the standard pulse width of each pulse in the secondary radar response signal sequence is 0.45us, the minimum interval between two adjacent pulses is 1us, and when 4 groups of response signals are interleaved, the condition of no interval between adjacent pulses can be formed to synthesize a wide pulse, considering the coding rule of the secondary radar response signal, the pulse sequence can have the condition that part of position codes are '0', and simultaneously considering the problem of FPGA resources, so the effective pulse width of the secondary radar response signal is set to 10us, and according to the definition of tangential sensitivity, the current secondary radar equipment only needs to identify signals with power greater than noise.
Noise model carrying dc bias:
the direct current bias and the signal can be discriminated on the time domain through the positive and negative bias characteristics and the holding time, the pulse width of the signal is basically fixed and predictable, the holding time of the direct current bias is longer, and the phenomenon of violent change can not exist after the equipment is powered on or receives and transmits and switches are completed every time.
Secondly, according to the difference of noise, signals and direct current bias characteristics, a data type discrimination sliding window model is arranged, a data cache space is arranged in the sliding window model, bias attributes are defined for each group of data, and the type of the cache data is discriminated by counting all data bias attributes in the cache space.
The width of the sliding window is set according to the effective width of the secondary radar response signal, and in order to ensure accurate discrimination of the signal and the direct current bias, the width of the sliding window is larger than the pulse width of the secondary radar response signal.
And sequentially inputting zero intermediate frequency secondary radar baseband data into the sliding window, caching the input data, and positioning the original cache library in a data cache space in the sliding window.
Then, designing according to the data model expansion algorithm:
(1) noise initialization parameters are obtained through statistical characteristics, and 4096 groups of data x are acquired after 10 times of electrification in a receiving channel no-signal input states(n) obtaining the arithmetic mean value AVA by operationnoiseMAX, MAXnoiseAnd minimum MINnoiseAnd indirectly calculating to obtain the maximum noise positive offset value NMPO without DC offsetinitInitial value of maximum negative bias value NMNOinit；
NMPOinit＝MAXnoise+AVAnoise；………………………………………………(2)
NMNOinit＝MINnoise-AVAnoise；………………………………………………(3)
(2) Since the DC offset is averaged from the real-time noise data, the noise data x is then determinedN(t) is shown.
First, input data is defined as xI(n) defining the noise mean as mN(n) definition of xMPO(n) is the maximum positive offset value of noise (including noise when carrying DC offset), xMNO(n) is the noise maximum negative bias, defining xT(n) to mark input data xIAnd (n) positive and negative bias types.
The noise maximum positive offset expression is as follows:
xMPO(n)＝mN(n)+NMPOinit……………………………………………………(4)
the noise maximum negative offset expression is as follows:
xMNO(n)＝mN(n)-NMNOinit……………………………………………………(5)
the input data positive and negative bias type expression is as follows:
xT(n) ═ 0, meaning that the data is neither positively nor negatively biased, xT(n) 1, indicating that the data is positive biased, xT(n) ═ 2, and indicates that the data is negatively biased.
The input data type (signal or noise) is identified by the forward and reverse bias properties of a consecutive 256 sets (based on resource consumption and design requirements) of data:
a)、xT(n)、xT(n-1)、...、xTthe value of (n-255) is 1 at the same time, that is, 256 groups of continuous data are forward biased at the same time, which means that the 256 groups of continuous data are noise data carrying direct current bias (there is forward offset from the current bias value);
b)、xT(n)、xT(n-1)、...、xTthe value of (n-255) is 2 at the same time, that is, 256 groups of continuous data are negative at the same time, which indicates that the 256 groups of continuous data are noise data carrying direct current offset (reverse offset exists relative to the current offset value);
c)、xT(n)、xT(n-1)、...、xTthe values of (n-255) are all 0, namely the data are neither positively biased nor negatively biased, which means that 256 groups of data are all noise data which do not carry direct current bias (no offset relative to the current bias value);
d)、xT(n)、xT(n-1)、...、xTthe value of (n-255) is partially 1 or 2, and the rest is 0, which indicates that a partial signal (the bias type is not 0, and the partial signal is not required to be judged as a valid signal or an interference signal) exists in the data, and the noise data is replaced by the real-time noise mean value.
If it is determined that there is noise data in the input data, the noise data is moved from the original database into a noise buffer bank (a place where the noise data is buffered is referred to as a noise buffer bank), and if it is determined that there is signal data in the input data, the signal data is removed from the original database.
In order to accurately restore the amplitude and phase of the signal, when the data is the signal, the data cannot be moved into a noise buffer library for averaging, and the average value obtained by the buffered noise data is used as the substitute data and is moved into the noise buffer library for real-time noise averaging.
In the process of eliminating direct current, due to the change of the noise mean value, the positive and negative bias characteristics of 256 groups of continuous data are changed from 1 (or 2) to 0 one by one, and in order to ensure the integrity of the whole process, an elimination mark x must be set after the direct current bias is identifiedflag(n) indicating the state of the dc removal process.
Accordingly, we obtain:
xflagwhen (n) is 1, it means that the dc offset is not completely removed, and xflagWhen (n) is 0, it indicates the front side DC biasThe set is not erased and the oldest data in the original cache bank is 0.
Further obtaining noisy data xN(n)：
When x isflagWhen (n-1) ═ 1, xN(n)＝xI(n-255), which means that the data in the original database are all noisy data carrying a dc offset;
when x isflag(n-1) ═ 0, and xIWhen (n-255) ═ 0, xN(n)＝xI(n-255), which means that the data in the original database are all noisy data carrying no dc offset;
in other cases, xN(n)＝mN(n) indicating that there is signal data in the original database, and that the current noise data needs to be averaged in real time.
3. The noise mean expression is:
4. the input data is output after being compensated in real time to obtain xO(n)：
xO(n)＝xI(n)-mN(n)……………………………………………………………(10)
And subtracting the unprocessed secondary radar baseband data before the input sliding window and the extracted direct current offset value, and outputting the data after the elimination of the direct current offset is completed.
According to factors of a processing clock and a data model, the time delay is calculated, namely 3.2us (256 × 12.5 ns-3.2 us) is required for the baseband data to be actually subjected to direct current bias until algorithm detection and judgment, and 3.2us is required for the baseband data to be subjected to bias elimination after the time delay is detected; i.e. the dc offset cancellation process only needs 6.4us while ensuring no data delay.
The algorithm verilog language is described according to the above, and the target program is configured in the FPGA for implementation.
According to the invention, a corresponding model is established according to the characteristics of noise and signals in the secondary radar system, a data discrimination sliding window is designed, the type (noise and signals) of input data is identified, direct current offset carried by an I/Q path in baseband data is accurately extracted and eliminated in real time, and the reliability and the stability of equipment are improved.
The invention is not limited to the foregoing embodiments. The invention extends to any novel feature or any novel combination of features disclosed in this specification and any novel method or process steps or any novel combination of features disclosed. Those skilled in the art to which the invention pertains will appreciate that insubstantial changes or modifications can be made without departing from the spirit of the invention as defined by the appended claims.
Claims (8)
1. The utility model provides a zero intermediate frequency secondary radar DC offset compensation algorithm based on FPGA which characterized in that includes:
step 1: establishing a corresponding noise data model and a corresponding signal data model according to the characteristics of noise data and signal data in a secondary radar system;
step 2: designing a data type discrimination sliding window model according to the noise data model and the signal data model, wherein a data cache space is arranged in the data type discrimination sliding window model, and a bias attribute is defined for each group of data input into the data cache space;
and step 3: sequentially inputting N groups of zero intermediate frequency secondary radar baseband data into a data type discrimination sliding window model, transferring N groups of data into an original cache library for caching, and then identifying and judging the types of the N groups of input data according to the offset attribute of the input data; n is a natural number more than or equal to 1;
and 4, step 4: if the noise data exist in the N groups of input data judged in the sliding window, the noise data are moved into a noise cache library from an original cache library for caching;
if signal data exist in the N groups of input data judged in the sliding window, the signal data are removed from an original cache library; after the signal data are eliminated, noise mean value of the noise data in the noise buffer library at the previous moment is calculated to be used as substitute data of the signal data, and the substitute data is transferred into the noise buffer library for buffering;
and 5: calculating the mean value of all noise data in the current noise cache library, and defining the mean value as a direct current offset value carried in current secondary radar baseband data;
step 6: and subtracting the quantization values of the N groups of secondary radar baseband data before being input into the sliding window model from the extracted direct current offset value to eliminate the direct current offset and output data.
2. The FPGA-based zero intermediate frequency secondary radar DC offset compensation algorithm according to claim 1, wherein in the step 1, the noise data model and the signal data model comprise: and the secondary radar system receives a noise model, a secondary radar response signal model and a noise model carrying direct current offset in channel baseband data.
3. The FPGA-based zero intermediate frequency secondary radar DC offset compensation algorithm according to claim 1, wherein in the step 2, the detailed process of defining the offset attribute is as follows:
when the input data is larger than the noise maximum positive offset value, indicating that the input data is positive offset;
when the input data is smaller than the maximum negative bias value of the noise, the input data is represented as negative bias;
when the input data is greater than or equal to the noise maximum negative bias value and less than or equal to the noise maximum positive bias value, the input data is not positively biased or negatively biased.
4. The FPGA-based zero intermediate frequency secondary radar DC offset compensation algorithm of claim 3, wherein the process of calculating the maximum positive offset value and the maximum negative offset value of the noise is divided into two cases:
if the noise data does not exist in the current noise cache library, the initial noise data group is input in a user-defined mode and the average value of the initial noise data group is obtained to serve as the initial noise average value; extracting maximum noise data in the custom noise data group as an initial noise maximum value; extracting minimum noise data in the custom noise data group as an initial noise minimum value;
the expression of the initial noise maximum positive offset value is:
NMPOinit＝MAXnoise+AVAnoise；
the expression for the maximum negative bias value of the initial noise is:
NMNOinit＝MINnoise-AVAnoise；
wherein, NMPOinitRepresenting the maximum positive offset value of the initial noise, NMNOinitRepresenting the maximum negative offset, AVA, of the initial noisenoiseRepresenting the initial noise mean, MAXnoiseRepresenting the initial noise maximum, MINnoiseRepresents the initial noise minimum;
if the noise data exists in the current noise cache library, averaging the noise data in the current noise cache library to be used as a real-time noise average value;
the expression of the maximum positive offset value of the real-time noise is as follows:
xMPO(n)＝mN(n)+NMPOinit；
the expression of the maximum negative offset value of the real-time noise is as follows:
xMNO(n)＝mN(n)-NMNOinit；
wherein x isMPO(n) represents the maximum positive offset value of real-time noise, xMNO(n) represents the maximum negative bias value of real-time noise, mN(n) means real time noise mean, NMPOinitRepresenting the maximum positive offset value of the initial noise, NMNOinitRepresenting the initial noise maximum negative bias value.
5. The FPGA-based zero intermediate frequency secondary radar DC offset compensation algorithm according to claim 1, wherein in the step 3, the detailed process for identifying and determining the data type is as follows:
if the N groups of input data are all represented as positive bias or negative bias in the sliding window, the N groups of input data are all noise data carrying direct current bias;
if the N groups of input data are not represented as positive offset or negative offset in the sliding window, the N groups of input data are all noise data which do not carry direct current offset;
if the N groups of input data are partially presented as positive bias and partially presented as negative bias in the sliding window, and the rest of the input data are not presented as positive bias or negative bias, the signal data in the N groups of input data are present.
6. The FPGA-based zero intermediate frequency secondary radar DC offset compensation algorithm as claimed in claim 5, wherein in the detailed data determination process, if the data is identified to carry the DC offset, a cancellation flag is set on the data to indicate the state of the DC cancellation process.
7. The FPGA-based zero intermediate frequency secondary radar DC offset compensation algorithm as recited in claim 1, wherein the data type discrimination sliding window model has a sliding window width larger than an effective pulse width of a secondary radar response signal.
8. The FPGA-based zero intermediate frequency secondary radar DC offset compensation algorithm as claimed in claim 1, wherein the algorithm is described by Verilog language and configured into FPGA for implementation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910870508.XA CN110632588B (en) | 2019-09-16 | 2019-09-16 | Zero intermediate frequency secondary radar direct current offset compensation algorithm based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910870508.XA CN110632588B (en) | 2019-09-16 | 2019-09-16 | Zero intermediate frequency secondary radar direct current offset compensation algorithm based on FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110632588A CN110632588A (en) | 2019-12-31 |
| CN110632588B true CN110632588B (en) | 2021-05-11 |
Family
ID=68972541
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910870508.XA Active CN110632588B (en) | 2019-09-16 | 2019-09-16 | Zero intermediate frequency secondary radar direct current offset compensation algorithm based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110632588B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114915524B (en) * | 2022-04-21 | 2023-09-22 | 中国电子科技集团公司第十研究所 | DC offset real-time compensation method, device, equipment and storage medium |
| CN115276840A (en) * | 2022-07-29 | 2022-11-01 | 深圳市思码逻辑技术有限公司 | Calibration method and device for zero intermediate frequency signal transceiver and electronic equipment |
| CN117220713B (en) * | 2023-09-06 | 2024-04-12 | 上海力通通信有限公司 | TX direct current tracking correction method without co-local oscillation |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6459889B1 (en) * | 2000-02-29 | 2002-10-01 | Motorola, Inc. | DC offset correction loop for radio receiver |
| CN1114304C (en) * | 1998-05-06 | 2003-07-09 | 皇家菲利浦电子有限公司 | DC offset compensation for zero IF quadrature demodulator |
| CN101453435A (en) * | 2007-12-04 | 2009-06-10 | 中兴通讯股份有限公司 | Method and apparatus for DC offset correction in zero intermediate frequency receiver |
| CN203104424U (en) * | 2013-01-30 | 2013-07-31 | 四川九洲电器集团有限责任公司 | Adjusting device for elimination of zero intermediate frequency direct current offset signal |
| CN104035079A (en) * | 2014-06-12 | 2014-09-10 | 浙江大学 | Novel zero intermediate frequency pulse compression radar system and signal performance compensation method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7502603B2 (en) * | 2005-06-03 | 2009-03-10 | Maxim Integrated Products, Inc. | DC cancellation in zero-IF receivers |
| KR101656266B1 (en) * | 2009-06-15 | 2016-09-12 | 삼성전자 주식회사 | Apparatus and Method for compensating DC-offset in Radio Frequency Integrated Circuit of direct conversion receiver in wireless communication system |
-
2019
- 2019-09-16 CN CN201910870508.XA patent/CN110632588B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1114304C (en) * | 1998-05-06 | 2003-07-09 | 皇家菲利浦电子有限公司 | DC offset compensation for zero IF quadrature demodulator |
| US6459889B1 (en) * | 2000-02-29 | 2002-10-01 | Motorola, Inc. | DC offset correction loop for radio receiver |
| CN101453435A (en) * | 2007-12-04 | 2009-06-10 | 中兴通讯股份有限公司 | Method and apparatus for DC offset correction in zero intermediate frequency receiver |
| CN203104424U (en) * | 2013-01-30 | 2013-07-31 | 四川九洲电器集团有限责任公司 | Adjusting device for elimination of zero intermediate frequency direct current offset signal |
| CN104035079A (en) * | 2014-06-12 | 2014-09-10 | 浙江大学 | Novel zero intermediate frequency pulse compression radar system and signal performance compensation method thereof |
Non-Patent Citations (3)
| Title |
|---|
| DC offset calibration method for zero-IF receiver removing the PGA-gain-correlated offset residue;LingweiZhang et al.;《AEU - International Journal of Electronics and Communications》;20130731;第67卷(第7期);第578-584页 * |
| 一种零中频接收机的直流偏置校准技术;梁晓峰 等;《现代信息科技》;20190525;第3卷(第10期);第38-41页 * |
| 零中频直流偏移消除技术比较与分析;唐琴 等;《微电子学》;20081231;第38卷(第6期);第811-816页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110632588A (en) | 2019-12-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110632588B (en) | Zero intermediate frequency secondary radar direct current offset compensation algorithm based on FPGA | |
| WO2018188228A1 (en) | High-precision frequency measuring system and method | |
| CN109490862B (en) | Carrier frequency estimation method based on phase difference statistical spectrum | |
| Barkat | Instantaneous frequency estimation of nonlinear frequency-modulated signals in the presence of multiplicative and additive noise | |
| CN110138385B (en) | Non-linear background calibration of samplers and amplifiers in an ADC | |
| Gupta et al. | Multi-Bit Digital Receiver Design For Radar Signature Estimation | |
| Chen et al. | Design and performance evaluation of a 2.5-GSPS digital receiver | |
| CN110596652B (en) | FPGA-based zero intermediate frequency secondary radar response pulse extraction method | |
| CN111562438A (en) | Sinusoidal signal frequency estimation method and device based on FFT and phase difference | |
| CN110568415A (en) | signal detection method based on Arctan function under Gaussian mixture model | |
| George et al. | Extension of two-signal spurious-free dynamic range of wideband digital receivers using Kaiser window and compensation method | |
| CN111865865A (en) | Frequency offset and phase offset estimation method suitable for high-sensitivity satellite-borne ADS-B receiver | |
| CN112883787B (en) | Short sample low-frequency sinusoidal signal parameter estimation method based on spectrum matching | |
| US11646836B2 (en) | System and method of coherent averaging of repetitive signals for measurement | |
| CN111289948B (en) | Pulse weather radar echo weak signal detection method and electronic equipment | |
| Benson et al. | Adaptive thresholding for high dual-tone signal instantaneous dynamic range in digital microwave receiver | |
| Lee et al. | Enhanced pulse amplitude estimation for electronic warfare systems | |
| CN107347042B (en) | Multi-stage digital channelized sub-channel output judgment method | |
| Miller et al. | Numerical results on the convergence of relative efficiencies | |
| Rogozhnikov et al. | The study of correlation receivers | |
| CN113406386A (en) | Signal frequency accurate estimation method based on digital down-conversion | |
| US9374246B2 (en) | Radio frequency digital receiver system and method | |
| CN114337707B (en) | Harmonic/intermodulation signal judging circuit and method of superheterodyne receiver | |
| CN101622611B (en) | Use the high speed digital waveform identification of higher order statistical signal process | |
| Chen et al. | An FFT-based Algorithm for I/Q Imbalance Correction of Radar Sensors |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |