CN110619918A - FTL power failure test method, system, device and storage medium - Google Patents
FTL power failure test method, system, device and storage medium Download PDFInfo
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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Abstract
The invention relates to an FTL power failure test method, a system, a device and a storage medium, wherein the FTL is divided into a data overwriting area for writing logic data and an information recording area for writing characteristic data, the information recording area is divided into two sub-partitions, the characteristic data, data addresses and data lengths generated each time are accumulated and alternately written into the two sub-partitions of the information recording area to play a backup role, the sub-partition of the latest data writing is selected from the two sub-partitions of the information recording area during verification, and the characteristic data, the data addresses and the data lengths of the sub-partitions are used as verification data, so that only the data written during power failure is lost during verification, the integrity of the verification data is effectively improved, the safety of key data is improved, and the test efficiency is improved.
Description
Technical Field
The invention relates to the field of flash memories, in particular to a method, a system and a device for testing power failure of an FTL (flash translation layer) and a storage medium.
Background
NAND Flash is increasingly used as a non-volatile storage device. The design of the NAND Flash algorithm needs to fully consider the power failure scene because of the self physical characteristics and the product application field. Electronic products using NANDFlash allow page data being programmed to be lost when power is lost. However, if the FTL continues to program the page after the next power-up, the data will not be guaranteed to be correct. Whether the NAND Flash FTL algorithm can correctly process the programmed page in the power failure condition directly influences the data security of the product.
The NAND Flash feature only supports continuous page programming, and each cell within a page can be programmed only once before the next erase. If power is lost during programming, the FTL generally fills invalid data into the page when starting next time, and continues to use the page from the next unprogrammed page. For the SLC mode of SLC NAND or TLC NAND, the NAND Flash can only lose the data of the currently programmed page at most when the power is abnormally cut off. The existing FTL power failure test generally adopts product-level file test or PC end simulation test. The existing scheme lacks pertinence, the NAND characteristic under the real power failure scene cannot be verified through PC end simulation test, in addition, the problem that the FTL cannot be measured at the first time due to the fact that a verification function of a file system is added in product-level power failure test is solved, and the phenomenon that key data are lost easily occurs when the FTL is powered down, so that the power failure test of the FTL is influenced.
Disclosure of Invention
The invention provides an FTL power failure test method, system, device and storage medium, which can improve the security of key data and improve the test efficiency.
In a first aspect, an embodiment of the present invention provides a method for testing a power failure of an FTL, where the method includes the following steps:
dividing the FTL into a data overwriting area and an information recording area, and dividing the information recording area into two subintervals;
generating a data address and a data length, and writing logic data in a data overwriting area according to the data address and the data length;
generating characteristic data;
accumulating and alternately writing the characteristic data, the data address and the data length generated each time into two subintervals of the information recording area;
and powering down and powering up again at any time point, selecting a subinterval of the latest write-in data from the two subintervals of the information recording area, sequentially reading the characteristic data, the data address and the data length of each write-in, and verifying the data with the corresponding logic data in the data overwriting area.
Further, the logic data includes a sector number and a power-down number.
Further, the characteristic data comprises the number of write operations and the number of power failures.
Further, the FTL is also divided into a static data area, and the entire logic space is fully written with logic data at the time of initial power-on.
Further, the logic data of the static data area is verified every fixed power-down times.
In a second aspect, an embodiment of the present invention further provides an FTL power down testing system, including:
a dividing unit for dividing the FTL into a data overwriting area and an information recording area, and dividing the information recording area into two sub-sections;
a generating unit for generating a data address and a data length, and generating characteristic data;
a writing unit for writing logical data in the data overwriting area, and accumulating and alternately writing the characteristic data, the data address and the data length generated each time into two subintervals of the information recording area;
and the checking unit is used for selecting the subinterval of the latest write-in data from the two subintervals of the information recording area, sequentially reading the characteristic data, the data address and the data length written in each time, and checking the data with the corresponding logic data in the data overwriting area.
Further, the partitioning unit further partitions the FTL into a static data area, and the writing unit writes logic data in the entire logic space when initially powered on.
Further, the check unit checks the logic data of the static data area every fixed power-down times.
In a third aspect, an embodiment of the present invention further provides a computer apparatus, including a memory, a processor, and a computer program stored in the memory and capable of running on the processor, where the processor executes the computer program to implement the FTL power down testing method according to the first aspect of the present invention.
In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the FTL power down testing method according to the first aspect of the present invention.
The embodiment of the invention at least has the following beneficial effects: according to the FTL power failure testing method, the FTL power failure testing system, the FTL power failure testing device and the FTL power failure testing storage medium, the FTL is divided into the data overwriting area for writing logic data and the information recording area for writing characteristic data, the data in the information recording area and the data in the data overwriting area are read for verification, other IO (input/output) paths are not needed, an FTL interface is directly called for testing, other interference factors can be eliminated, the independence of verification data is guaranteed, and the testing accuracy is improved; meanwhile, the information recording area is divided into two sub-partitions, the characteristic data, the data address and the data length which are generated each time are accumulated and alternately written into the two sub-intervals of the information recording area to play a backup role, the sub-interval of which data is written at the latest time is selected from the two sub-intervals of the information recording area during verification, and the characteristic data, the data address and the data length of the sub-interval are used as verification data, so that only the data written during power failure is lost during verification, the integrity of the verification data is effectively improved, the safety of key data is improved, and the testing efficiency is improved.
Drawings
FIG. 1 is a flow chart of a method for testing power down of an FTL in a first embodiment of the present invention;
FIG. 2 is a flow chart of a FTL power down test method in a second embodiment of the present invention;
fig. 3 is an architecture diagram of FTL power down test system in a third embodiment and a fourth embodiment of the present invention.
Detailed Description
The conception, the specific structure and the technical effects of the present invention will be clearly and completely described in conjunction with the embodiments and the accompanying drawings to fully understand the objects, the schemes and the effects of the present invention.
It should be noted that, unless otherwise specified, when a feature is referred to as being "fixed" or "connected" to another feature, it may be directly fixed or connected to the other feature or indirectly fixed or connected to the other feature. Furthermore, the descriptions of upper, lower, left, right, etc. used in the present disclosure are only relative to the mutual positional relationship of the constituent parts of the present disclosure in the drawings. As used in this disclosure, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any combination of one or more of the associated listed items.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element of the same type from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. The use of any and all examples, or exemplary language ("e.g.," such as "or the like") provided herein, is intended merely to better illuminate embodiments of the invention and does not pose a limitation on the scope of the invention unless otherwise claimed.
Referring to fig. 1, a first embodiment of the present invention provides a method for testing power down of an FTL, which includes, but is not limited to, the following steps:
s110, dividing the FTL into a data overwriting area and an information recording area, and dividing the information recording area into two subintervals;
s120, generating a data address and a data length, and writing logic data in the data overwriting area according to the data address and the data length;
s130, generating characteristic data;
s140, accumulating the characteristic data, the data address and the data length generated each time and alternately writing the characteristic data, the data address and the data length into two subintervals of the information recording area;
and S150, powering down and powering up again at any time point, selecting a subinterval of the latest written data from the two subintervals of the information recording area, sequentially reading the characteristic data, the data address and the data length written each time, and verifying the data with the corresponding logic data in the data overwriting area.
The logic data comprises sector numbers and power failure times, and the characteristic data comprises write operation times and power failure times.
In this embodiment, the specific data structures of the logic data and the feature data may be simply combined, for example: the sector number is X, the power-down frequency is Y, and the write operation frequency is Z, then the logic data may be XY, the characteristic data may be YZ, and the write operation frequency is added to the characteristic data to facilitate the determination of which subinterval data in the read information recording area. Of course, the elements included in the logic data and the feature data are not limited to those illustrated in the present embodiment, and may be freely increased or decreased in other embodiments according to actual circumstances. The data structure of the logic data and the feature data is not limited to a simple combination, and a simple operation method may be adopted, and a relatively convenient method such as a simple combination is explained in this embodiment.
Specifically, in S140, accumulating and alternately writing the characteristic data, the data address, and the data length generated each time into the two sub-sections of the information recording area means that, each time data is written into the information recording area, the characteristic data, the data address, and the data length generated this time and all the characteristic data, the data address, and the data length generated before are included, and two sub-sections are cyclically selected to be alternately written, for example:
a first generation of a data set to be written in the information recording area represented by 1, in which case 1 is written in the subinterval a, the number of write operations being 1;
a second generation of a data set to be written in the information recording area represented by 2, in which case 1 and 2 are written in the subinterval B simultaneously, the number of write operations being 2;
a third generation, in which 3 represents a data set to be written in the information recording area, and in this case, 1, 2, and 3 are simultaneously written in the subinterval a, and the number of write operations is 3;
a fourth generation of a data set to be written in the information recording area, denoted by 4, in which case 1, 2, 3 and 4 are written in the sub-zone B simultaneously, the number of write operations being 4;
by analogy … …
Therefore, if the power is lost when the information recording area is written for the fourth time, the data written into the subinterval B will be lost, the subinterval B only stores the data sets written for the second time, namely 1 and 2, and the subinterval a still stores the data written for the previous three times, namely 1, 2 and 3, so that the data sets in the subinterval a can be read, only the data written during the power failure is lost during verification, the integrity of the verification data is effectively improved, the security of the key data is improved, and the test efficiency is improved.
And selecting the subinterval of the latest data writing from the two subintervals of the information recording area during verification, which can be distinguished by the number of times of writing operation, for example, if the power is down when the information recording area is written for the fourth time, reading the number of times of writing operation of the subinterval a and the subinterval B after power is turned on again, at this time, the number of times of writing operation of the subinterval a is 3 times, the number of times of writing operation of the subinterval B is 2 times, at this time, selecting the subinterval with larger number of times of writing operation, namely, the subinterval a, and reading the data set in the subinterval a, so that all data sets, namely, 1, 2 and 3, written to the information recording area for several times before the power is down can.
Once the data in the data overwriting area is inconsistent with the data in the corresponding address of the information recording area, the FTL is proved to be abnormal.
The FTL is divided into a data overwriting area for writing logic data and an information recording area for writing characteristic data, the data in the information recording area is read and verified with the data in the data overwriting area, and the FTL interface is directly called for testing without other IO (input/output) channels, so that other interference factors can be eliminated, the independence of verification data is ensured, and the testing accuracy is improved; meanwhile, the information recording area is divided into two sub-partitions, the characteristic data, the data address and the data length which are generated each time are accumulated and alternately written into the two sub-intervals of the information recording area to play a backup role, the sub-interval of which data is written at the latest time is selected from the two sub-intervals of the information recording area during verification, and the characteristic data, the data address and the data length of the sub-interval are used as verification data, so that only the data written during power failure is lost during verification, the integrity of the verification data is effectively improved, the safety of key data is improved, and the test efficiency is improved.
Referring to fig. 2, on the basis of the first embodiment, a second embodiment of the present invention provides a method for testing power down of an FTL, which includes, but is not limited to, the following steps:
s1, dividing the FTL into a data overwriting area, an information recording area and a static data area, and dividing the information recording area into a subinterval A and a subinterval B;
s2, power-on starting, judging whether power is powered on for the first time, if so, jumping to S3, and if not, jumping to S4;
s3, writing the whole logic space with logic data, jumping to S6;
s4, selecting the sub-interval of the latest write data from the two sub-intervals of the information recording area, reading the characteristic data, the data address and the data length written each time in sequence, and checking the data with the corresponding logic data in the data overwriting area;
s5, checking the logic data of the static data area every fixed power-down times;
s6, generating data address and data length, writing logic data in the data overwriting area according to the data address and the data length, and generating characteristic data;
s7, writing the generated characteristic data, data address and data length into the subinterval A of the information recording area;
s8, generating data address and data length again, writing logic data in the data overwriting area according to the data address and the data length, and generating characteristic data;
s9, writing the generated characteristic data, data address and data length into the subinterval B of the information recording area;
and (6) circularly executing S6-S9, and jumping to S2 after power is down and power is up again in any time period.
In S3, the entire logical space includes a data overwriting area, an information recording area, and a static data area, the logical data includes a sector number and a power failure count, and the entire logical space is full of logical data, which is used to know the error address pointed by the mapping table if the FTL runs in error.
In S4, the characteristic data includes the number of write operations and the number of power-down operations, and the number of write operations is added in order to facilitate identification of the latest data when reading the information recording area data.
In S5, the static data area is used to verify the correctness of the cold data, which is a logical address that is read-only and not written. The principle of the verification is to read a complete static data area once every certain power-down times and judge the change of the data. In addition, since the data of the static data area is first electrically written, a combination of a sector number and 0 may be possible, where 0 represents the number of times of power-down.
In S6, the data address and the data length are randomly generated each time, with the data address and the data length as a format, and the sector number and the power-down number as specific contents. Similarly, the specific data structure of the logic data and the feature data may be simply combined, but is not limited to the simple combination.
And once the data in the data overwriting area is inconsistent with the data in the corresponding address of the information recording area or the data in the static data area is inconsistent, the FTL is proved to be abnormal.
On the basis of the first embodiment, in the embodiment, when the FTL is powered on for the first time, the entire logic space is fully written with logic data, so that an error address can be conveniently found out when the FTL has an error in operation, and the test efficiency is improved; and furthermore, a static data area is introduced, logic data in the static data area are verified at intervals of fixed power failure times, so that the dynamic data of the FTL can be tested, the static data of the FTL can also be tested, and the reliability of the test is improved. The data in the information recording area and the data in the data overwriting area are read for verification, and the FTL interface is directly called for testing without other IO access, so that other interference factors can be eliminated, the independence of the verification data is ensured, and the testing accuracy is improved; meanwhile, the information recording area is divided into two sub-partitions, the characteristic data, the data address and the data length which are generated each time are accumulated and alternately written into the two sub-intervals of the information recording area to play a backup role, the sub-interval of which data is written at the latest time is selected from the two sub-intervals of the information recording area during verification, and the characteristic data, the data address and the data length of the sub-interval are used as verification data, so that only the data written during power failure is lost during verification, the integrity of the verification data is effectively improved, the safety of key data is improved, and the test efficiency is improved.
Referring to fig. 3, a third embodiment of the present invention further provides a system for testing a power failure of an FTL, including:
a dividing unit 100 for dividing the FTL into a data overwriting area and an information recording area, and dividing the information recording area into two sub-sections;
a generating unit 200 for generating a data address and a data length, and generating feature data;
a writing unit 300 for writing logical data in the data overwriting area, and accumulating and alternately writing the characteristic data, the data address and the data length generated each time into two subintervals of the information recording area;
the verifying unit 400 is configured to select a sub-interval of the latest written data from the two sub-intervals of the information recording area, sequentially read the feature data, the data address, and the data length written each time, and verify the corresponding logical data in the data overwriting area.
The power failure test system in this embodiment is based on the same inventive concept as the first embodiment, and the principle of the power failure test system is not explained any more, the dividing unit 100 divides the FTL into a data overwriting area for writing logic data and an information recording area for writing characteristic data, and the verification unit 400 verifies the data in the data overwriting area by reading the data in the information recording area and the data in the data overwriting area, and directly calls an FTL interface for testing without passing through other IO paths, so that other interference factors can be eliminated, the independence of verification data can be ensured, and the test accuracy can be improved; meanwhile, the information recording area is divided into two sub-partitions, the characteristic data, the data address and the data length which are generated each time are accumulated and alternately written into the two sub-intervals of the information recording area to play a backup role, the sub-interval of which data is written at the latest time is selected from the two sub-intervals of the information recording area during verification, and the characteristic data, the data address and the data length of the sub-interval are used as verification data, so that only the data written during power failure is lost during verification, the integrity of the verification data is effectively improved, the safety of key data is improved, and the test efficiency is improved.
A fourth embodiment of the present invention further provides a system for testing a power failure of an FTL, which includes:
a dividing unit 100 for dividing the FTL into a data overwriting area, an information recording area, and a static data area, and dividing the information recording area into two sub-sections;
the generating unit 200 is configured to write logic data in the entire logic space at the time of initial power-on, generate a data address and a data length, and generate feature data;
a writing unit 300 for writing logical data in the data overwriting area, and accumulating and alternately writing the characteristic data, the data address and the data length generated each time into two subintervals of the information recording area;
the verification unit 400 is configured to select a subinterval where data is written most recently from two subintervals in the information recording area, sequentially read the feature data, the data address, and the data length written each time, verify the logical data corresponding to the data overwriting area, and verify the logical data in the static data area every fixed power-down times.
The power failure test system in the embodiment is based on the same inventive concept as the second embodiment, the principle of the power failure test system is not explained, and the write-in unit 300 is fully written with logic data in the whole logic space during initial power-on, so that an error address can be conveniently found out when the FTL has an error in operation, and the test efficiency is improved; the division unit 100 divides the FTL into a data overwriting area, an information recording area, and a static data area, and the verification unit 400 verifies the logic data in the static data area every fixed power down times, so that the FTL dynamic data can be tested, the FTL static data can be tested, and the reliability of the test is improved. The verification unit 400 verifies the data in the read information recording area and the data in the data overwriting area, directly calls the FTL interface to test without passing through other IO channels, can eliminate other interference factors, ensures the independence of verification data, and improves the test accuracy; meanwhile, the information recording area is divided into two sub-partitions, the characteristic data, the data address and the data length which are generated each time are accumulated and alternately written into the two sub-intervals of the information recording area to play a backup role, the sub-interval of which data is written at the latest time is selected from the two sub-intervals of the information recording area during verification, and the characteristic data, the data address and the data length of the sub-interval are used as verification data, so that only the data written during power failure is lost during verification, the integrity of the verification data is effectively improved, the safety of key data is improved, and the test efficiency is improved.
It should be recognized that the method steps in embodiments of the present invention may be embodied or carried out by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer readable memory. The method may use standard programming techniques. Each program may be implemented in a high level procedural or object oriented programming language to communicate with a computer system. However, the program(s) can be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language. Furthermore, the program can be run on a programmed application specific integrated circuit for this purpose.
Further, the operations of processes described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The processes described herein (or variations and/or combinations thereof) may be performed under the control of one or more computer systems configured with executable instructions, and may be implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) collectively executed on one or more processors, by hardware, or combinations thereof. The computer program includes a plurality of instructions executable by one or more processors.
Further, the method may be implemented in any type of computing platform operatively connected to a suitable interface, including but not limited to a personal computer, mini computer, mainframe, workstation, networked or distributed computing environment, separate or integrated computer platform, or in communication with a charged particle tool or other imaging device, and the like. Aspects of the invention may be embodied in machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, optically read and/or write storage medium, RAM, ROM, or the like, such that it may be read by a programmable computer, which when read by the storage medium or device, is operative to configure and operate the computer to perform the procedures described herein. Further, the machine-readable code, or portions thereof, may be transmitted over a wired or wireless network. The invention described herein includes these and other different types of non-transitory computer-readable storage media when such media include instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor. The invention also includes the computer itself when programmed according to the methods and techniques described herein.
A computer program can be applied to input data to perform the functions described herein to transform the input data to generate output data that is stored to non-volatile memory. The output information may also be applied to one or more output devices, such as a display. In a preferred embodiment of the invention, the transformed data represents physical and tangible objects, including particular visual depictions of physical and tangible objects produced on a display.
The above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiment, and any modifications, equivalent substitutions, improvements, etc. within the spirit and principle of the present invention should be included in the protection scope of the present invention as long as the technical effects of the present invention are achieved by the same means. The invention is capable of other modifications and variations in its technical solution and/or its implementation, within the scope of protection of the invention.
Claims (10)
1. A power-down testing method for an FTL is characterized by comprising the following steps:
dividing the FTL into a data overwriting area and an information recording area, and dividing the information recording area into two subintervals;
generating a data address and a data length, and writing logic data in a data overwriting area according to the data address and the data length;
generating characteristic data;
accumulating and alternately writing the characteristic data, the data address and the data length generated each time into two subintervals of the information recording area;
and powering down and powering up again at any time point, selecting a subinterval of the latest write-in data from the two subintervals of the information recording area, sequentially reading the characteristic data, the data address and the data length of each write-in, and verifying the data with the corresponding logic data in the data overwriting area.
2. The FTL power down test method of claim 1, wherein: the logical data includes a sector number and a power down number.
3. The FTL power down test method of claim 1, wherein: the characteristic data comprises the number of write operations and the number of power failures.
4. The FTL power down test method of claim 1, wherein: the FTL is also divided into static data areas, which are written full of logical data in the entire logical space upon initial power up.
5. The FTL power down test method of claim 4, further comprising: and checking the logic data of the static data area every other fixed power failure times.
6. An FTL power down test system, comprising:
a dividing unit for dividing the FTL into a data overwriting area and an information recording area, and dividing the information recording area into two sub-sections;
a generating unit for generating a data address and a data length, and generating characteristic data;
a writing unit for writing logical data in the data overwriting area, and accumulating and alternately writing the characteristic data, the data address and the data length generated each time into two subintervals of the information recording area;
and the checking unit is used for selecting the subinterval of the latest write-in data from the two subintervals of the information recording area, sequentially reading the characteristic data, the data address and the data length written in each time, and checking the data with the corresponding logic data in the data overwriting area.
7. The FTL power down test system of claim 6, wherein: the partitioning unit further partitions the FTL into static data areas, and the writing unit writes logic data in the entire logic space when initially powered on.
8. An FTL power down test system according to claim 7, wherein: and the checking unit checks the logic data of the static data area every fixed power failure times.
9. A computer apparatus comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the program when executed by the processor implements the FTL power down test method of any of claims 1-5.
10. A computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the FTL power down testing method of any of claims 1-5.
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