CN110619907B - Synapse circuit, synapse array and data processing method based on synapse circuit - Google Patents
Synapse circuit, synapse array and data processing method based on synapse circuit Download PDFInfo
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- CN110619907B CN110619907B CN201910806010.7A CN201910806010A CN110619907B CN 110619907 B CN110619907 B CN 110619907B CN 201910806010 A CN201910806010 A CN 201910806010A CN 110619907 B CN110619907 B CN 110619907B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/061—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using biological neurons, e.g. biological neurons connected to an integrated circuit
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
Abstract
The embodiment of the application relates to the field of neural networks. The synaptic circuit provided by the invention comprises: a first memory, a second memory and a switch assembly; the switch assembly comprises a first switch tube, a second switch tube and a third switch tube; the first end of the first switch tube is connected with the first end of the first memory, and the control end of the first switch tube is connected with the first bit line interface; the first end of the second switch tube is connected with the first end of the second memory, and the control end of the second switch tube is connected with the second bit line interface; the second end of the first memory is connected with the first end of the second memory; the first end of the third switching tube is connected with the second end of the second memory, the second end of the third switching tube is connected with the word line interface, and the third end of the third switching tube is grounded. Based on the embodiment of the application, the first switch tube and the second switch tube respectively control the first memory and the second memory which are connected in series, and cross interference among the memories can be reduced during data storage.
Description
Technical Field
The invention relates to the field of neural networks, in particular to a synaptic circuit, a synaptic array and a data processing method based on the synaptic circuit.
Background
The neural network is a large-scale parallel simple processing unit as a breakthrough foundation of the modern deep learning technology, can not only store data, but also analyze and make predictions according to the stored data. Many tasks that were previously considered unthinkable have now been accomplished with the continued development of neural network technology. Such as image recognition, voice recognition, finding depth relationships in the data set, and the like.
Synapses, which are structures in a neural network that connect different neurons, are the medium by which a neuron communicates with other neurons. In the prior art, a synaptic circuit formed by connecting a memristor and a switching tube in series is adopted, and although the layout area of the circuit is small, the resolution is very low when data is stored and read by adopting the synaptic circuit. In order to solve the problem of low resolution, the improved scheme adopts a synaptic circuit which is formed by connecting two memristors in parallel and then connecting the two memristors in series with a switching tube, as shown in fig. 2, however, since the two memristors are connected in parallel, the two memristors are controlled by one switching tube, the control mode is complex, and the power consumption is high.
Disclosure of Invention
The invention provides a synaptic circuit, a synaptic array and a data processing method based on the synaptic circuit, and aims to solve the problems that one switching tube controls two parallel memristors, the control mode is complex, and the power consumption is high.
An embodiment of the present application provides a synaptic electrical circuit, including: a first memory, a second memory and a switch assembly;
the switch assembly comprises a first switch tube, a second switch tube and a third switch tube;
the first end of the first switch tube is connected with the first end of the first memory, and the control end of the first switch tube is connected with the first bit line interface;
the first end of the second switch tube is connected with the first end of the second memory, and the control end of the second switch tube is connected with the second bit line interface;
the second end of the first memory is connected with the first end of the second memory;
the first end of the third switching tube is connected with the second end of the second memory, the second end of the third switching tube is connected with the word line interface, and the third end of the third switching tube is grounded.
Further, still include: a first pulse interface and a second pulse interface;
the first pulse interface is connected with the second end of the first switching tube;
the second pulse interface is connected with the second end of the second switch tube.
Furthermore, the first bit line interface is used for being connected with the first bit line and controlling the switch of the first switch tube; and the second bit line interface is used for being connected with a second bit line and controlling the switch of the second switch tube.
Further, still include: a read line interface; the read-out line interface is connected with the first end of the third switching tube.
Further, the first memory and the second memory are phase change memories or impedance random access memories or other memristor-like nonvolatile memory devices;
the switch component comprises any one of a gate tube, a diode, a triode or a switch.
Correspondingly, the embodiment of the application also provides a synapse array comprising the synapse circuit in any one of the above.
Furthermore, one end of the synapse array is connected with the signal input end, and the other end of the synapse array is connected with the signal output end;
the synapse array comprises n × m synapse circuits, wherein n is the number of rows of the synapse array, and m is the number of columns of the synapse array.
Further, a first bit line, a second bit line, a word line and a sense line are included;
the first bit line interfaces of the n x m synapse circuits are all connected with the first bit lines;
the second bit line interfaces of the n x m synapse circuits are all connected with a second bit line;
the word line interfaces of the n × m synapse circuits are all connected with the word lines;
the read line interfaces of the n × m synapse circuits are all connected with the read lines;
correspondingly, an embodiment of the present application further provides a data processing method based on a synaptic circuit, including:
receiving a data processing instruction;
if the data processing instruction is a low-bit data storage instruction, enabling the first bit line interface to receive a first working instruction; the first working instruction is used for controlling the first switching tube to be in a working state;
controlling a first pulse interface to apply a first pulse to a first memory; the first pulse is used for changing the conductance of the first memory to store low-order data;
if the data processing instruction is a high-bit data storage instruction, enabling the second bit line interface to receive a second working instruction; the second working instruction is used for controlling the second switching tube to be in a working state;
controlling a second pulse interface to apply a second pulse to a second memory; the second pulse is used to change the conductance of the second memory to store the high bit data.
Further, still include:
if the data processing instruction is a data reading instruction, enabling the first bit line interface to receive a first working instruction, wherein the first working instruction is used for controlling the first switching tube to be in a working state; controlling the word line interface to be in a working state;
the data reading instruction carries a word line address, the word line address is used for determining a word line for acquiring data, and the data is read by the word line from a bit line connected with a first bit line interface through a word line interface connected with the word line and the first bit line interface corresponding to the word line interface.
The embodiment of the invention has the following beneficial effects:
the invention discloses a synaptic circuit, a synaptic array and a data processing method based on the synaptic circuit, wherein the synaptic circuit comprises: a first memory, a second memory and a switch assembly; the switch assembly comprises a first switch tube, a second switch tube and a third switch tube; the first end of the first switch tube is connected with the first end of the first memory, and the control end of the first switch tube is connected with the first bit line interface; the first end of the second switch tube is connected with the first end of the second memory, and the control end of the second switch tube is connected with the second bit line interface; the second end of the first memory is connected with the first end of the second memory; the first end of the third switching tube is connected with the second end of the second memory, the second end of the third switching tube is connected with the word line interface, and the third end of the third switching tube is grounded. Based on the embodiment of the application, the switching tube assembly is added to be different from a traditional synapse array without the switching tube, so that the cross interference between synapses can be avoided and a current discharge loop can be provided in the data writing and erasing process. In addition, the synapse circuit effectively utilizes the circuit layout area during the design, can also expand the resolution of synapses and reduce the static loss of synapse arrays during the data processing, and has the advantage of low power consumption.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions and advantages of the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram of a synaptic electrical circuit in the prior art;
FIG. 2 is a schematic diagram of another synaptic electrical circuit of the prior art;
FIG. 3 is a schematic diagram of a synaptic electrical circuit according to an embodiment of the present application;
FIG. 4 is a graph of temperature versus time for a phase change material during a set process and a reset process;
FIG. 5 is a schematic diagram of an alternative synaptic electrical circuit based on FIG. 3 according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a synapse array according to an embodiment of the present disclosure;
FIG. 7 is a flow chart illustrating a data processing method based on synapse circuit according to an embodiment of the disclosure;
FIG. 8 is a schematic diagram of the connection of synapse circuit in low-bit data storage;
FIG. 9 is a schematic diagram of the connection of synapse circuit in high data storage.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in further detail with reference to the accompanying drawings. It should be apparent that the described embodiment is only one embodiment of the embodiments of the application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that "embodiment" as referred to herein refers to a particular feature, structure, or characteristic that may be included in at least one implementation of an embodiment of the present application. In the description of the embodiments of the present application, the terms "first", "second" and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit indicating the number of technical features indicated, whereby the features defined as "first", "second" and "third" may explicitly or implicitly include one or more such features. Also, the terms "first," "second," and "third" are used for distinguishing between similar elements and not for describing a particular sequential or chronological order, it being understood that such usage data may be interchanged where appropriate. Furthermore, the terms "comprising," "having," and "being," as well as any variations thereof, are intended to cover non-exclusive inclusions, e.g., comprising a list of elements or steps, not necessarily limited to those elements or steps explicitly listed, but may include elements or steps not explicitly listed or inherent to the modules and methods herein.
Referring to fig. 3, a schematic structural diagram of a synaptic circuit according to an embodiment of the present application is shown, wherein the schematic structural diagram includes: the memory comprises a first memory 4, a second memory 5 and a switch assembly, wherein the switch assembly comprises a first switch tube 1, a second switch tube 2 and a third switch tube 3, a first end 11 of the first switch tube 1 is connected with a first end 41 of the first memory 4, a control end of the first switch tube 1 is connected with a first bit line interface 8, a first end 21 of the second switch tube 2 is connected with a first end 51 of the second memory 5, a control end of the second switch tube 5 is connected with a second bit line interface 9, a second end 42 of the first memory 4 is connected with the first end 51 of the second memory 5, a first end 31 of the third switch tube 3 is connected with a second end 52 of the second memory 5, a second end 32 of the third switch tube 3 is connected with a word line interface 10, and a third end 33 of the third switch tube 3 is grounded.
By adopting the synapse circuit provided by the embodiment of the application, the first switch tube and the second switch tube respectively control the first memory and the second memory which are connected in series, so that the circuit structure is reduced and the cross interference among the memories is also reduced during data storage. In addition, the circuit power consumption is effectively reduced when data is read.
In the embodiment of the present application, the first memory 4 and the second memory 5 shown in fig. 3 may be phase change memories, impedance random access memories, or any memristor-type nonvolatile memory devices.
In the embodiment of the present application, the switch component shown in fig. 3 includes any one of a gate tube, a diode, a triode, or a switch.
In the embodiment of the present application, the initial states of the first memory 4 and the second memory 5 are described with respect to the resistance values, the initial state of the first memory 4 is low resistance, and the initial state of the second memory 5 is low resistance.
In an alternative embodiment, the first memory 4 and the second memory 5 are phase change memories, which are ovonic based elements that achieve writing, reading and erasing of information by changing the resistance difference through the mutual transformation of the phase change material between the crystalline and amorphous states. As shown in fig. 4, the temperature versus time of the phase change material during the set process and the reset process. And (c) applying the short and long pulse voltage shown in (a) to the memory cell, heating the phase change material to be above the melting point, and then suddenly cooling to complete the amorphous transformation of high resistance, thereby completing the reset operation. And (c) applying the pulse voltage with the length and the medium intensity shown in the step (b) to the storage unit, heating the phase change material to a temperature above the crystallization point and below the melting point, and then cooling to complete the low-resistance crystalline state conversion, thereby completing the set operation. The phase change material is not changed by applying short and weak pulse voltage to the memory cell, and the read-out operation of the phase change memory resistance is completed.
An alternative embodiment is described below based on the synaptic electrical circuit shown in fig. 3, and fig. 5 is a schematic structural diagram of an alternative synaptic electrical circuit provided in an embodiment of the present application, where the schematic structural diagram includes:
a first memory 4, a second memory 5, a switching component, a first pulse interface 6, a second pulse interface 7, a first bit line interface 8, a second bit line interface 9, a word line interface 10, and a sense line interface 13;
the switch assembly comprises a first switch tube 1, a second switch tube 2 and a third switch tube 3;
the first end 11 of the first switch tube 1 is connected with the first end 41 of the first memory 4, the control end of the first switch tube 1 is connected with the first bit line interface 8 and used for controlling the switching of the first switch tube 1, and the second end 12 of the first switch tube 1 is connected with the first pulse interface 6; the first end 21 of the second switch tube 2 is connected with the first end 51 of the second memory 5, the control end of the second switch tube 5 is connected with the second bit line interface 9 for controlling the switching of the second switch tube 2, and the second end 22 of the second switch tube 2 is connected with the second pulse interface 7; the second terminal 42 of the first memory 4 is connected to the first terminal 51 of the second memory 5, the first terminal 31 of the third switching tube 3 is connected to the second terminal 52 of the second memory 5, the first terminal 31 of the third switching tube 3 is further connected to the read line interface 13, the second terminal 32 of the third switching tube 3 is connected to the word line interface 10, and the third terminal 33 of the third switching tube 3 is grounded.
The synaptic electrical circuit provided by the embodiment of the application comprises: a first memory, a second memory and a switch assembly; the switch assembly comprises a first switch tube, a second switch tube and a third switch tube; the first end of the first switch tube is connected with the first end of the first memory, and the control end of the first switch tube is connected with the first bit line interface; the first end of the second switch tube is connected with the first end of the second memory, and the control end of the second switch tube is connected with the second bit line interface; the second end of the first memory is connected with the first end of the second memory; the first end of the third switching tube is connected with the second end of the second memory, the second end of the third switching tube is connected with the word line interface, and the third end of the third switching tube is grounded. Based on the embodiment of the application, the first switch tube and the second switch tube respectively control the first memory and the second memory which are connected in series, so that the data writing and erasing process is different from a traditional synapse array without the switch tubes, cross interference between synapses can be avoided, and a current discharging loop can be provided. In addition, the synapse circuit effectively utilizes the circuit layout area during the design, can also expand the resolution of synapses and reduce the static loss of synapse arrays during the data processing, and has the advantage of low power consumption.
Referring to fig. 3, fig. 6 is a schematic structural diagram of a synapse array according to an embodiment of the present disclosure, wherein one end of the synapse array is connected to a signal input end, and the other end of the synapse array is connected to a signal output end; the synapse array comprises n × m synapse circuits, where n is the number of rows of the synapse array and m is the number of columns of the synapse array, and the synapse circuits are the synapse circuits in fig. 5. The array of synapses further comprising a first bit line, a second bit line, a word line and a sense line; the first bit line interfaces 8 of the n x m synapse circuits are all connected with the first bit lines; the second bit line interfaces 9 of the n x m synapse circuits are all connected with the second bit lines; the word line interfaces 10 of the n × m synapse circuits are all connected with word lines; the sense line interfaces 13 of the n x m synapse circuits are all connected to sense lines.
By adopting the synapse array provided by the embodiment of the application, the first switch tube and the second switch tube respectively control the first memory and the second memory which are connected in series, so that the synapse array is different from a synapse circuit without a switch tube in a traditional cross array, cross interference between synapse circuits can be avoided, and a current leakage loop can be provided for writing and erasing data; in addition, the synaptic circuit effectively utilizes the circuit layout area during design, can expand the resolution of synapses and reduce the static loss of a synaptic array during data processing, and has the advantage of low power consumption
Referring to fig. 7-9, fig. 7 is a schematic flow chart of a data processing method based on a synapse circuit provided in an embodiment of the present application, fig. 8 is a schematic connection diagram of a synapse circuit during low-bit data storage, and fig. 9 is a schematic connection diagram of a synapse circuit during high-bit data storage, where the method includes:
s701: receiving a data processing instruction by synapse circuit;
s703: the synapse circuit judges according to the received data processing instruction, if the data processing instruction is a low-bit data storage instruction, transposing step 705; otherwise, transpose step 709;
s705: the synapse circuit causes the first bit line interface 8 to receive a first work instruction according to the received low-bit data storage instruction; the first working instruction is used for controlling the first switching tube 1 to be in a working state;
s707: the synapse circuit controls the first pulse interface 6 to apply a first pulse to the first memory 4; the first pulse is used to change the conductance of the first memory 4 to store the lower bits of data;
s709: the synapse circuit continues to judge according to the received data processing instruction, if the data processing instruction is a high-order data storage instruction, the transposition step 711; otherwise, transpose step 715;
s711: the synapse circuit causes the second bit line interface 9 to receive a second work instruction according to the received high-bit data storage instruction; the second working instruction is used for controlling the second switching tube 2 to be in a working state;
s713: the synapse circuit controls the second pulse interface 7 to apply a second pulse to the second memory 5; the second pulse is used to change the conductance of the second memory 5 to store the higher data.
S715: the synapse circuit determines that the data processing instruction is a data reading instruction;
s717: the synapse circuit enables the first bit line interface 8 to receive a first working instruction according to the received data reading instruction, wherein the first working instruction is used for controlling the first switching tube to be in a working state;
s719: the synapse circuitry controls the word line interface 10 to be in an operative state.
In this embodiment, the first memory 4 is a low-bit data memory, the second memory 5 is a high-bit data memory, the first bit line connected to the first bit line interface 8 for controlling the first switch transistor 1 is a low-bit line, and the second bit line connected to the second bit line interface 9 for controlling the second switch transistor 2 is a high-bit line.
In the embodiment of the application, before the synaptic circuit receives the data processing instruction, both the first switching tube 1 and the second switching tube 2 are in the non-working state.
In the embodiment of the present application, the data reading instruction carries a word line address, the word line address is used to determine a word line for obtaining data, and the data is read by the word line from a bit line connected to the first bit line interface 8 through a word line interface 10 connected to the word line and the first bit line interface 8 corresponding to the word line interface 10.
In the embodiment of the present application, the word lines, the bit lines and the sense lines are all the word lines, the bit lines and the sense lines in the synapse array shown in FIG. 6.
In this embodiment, when the third switch tube 3 is a gate tube or a transistor, the readout line may be an additional readout line connected to the first end of the gate tube or the transistor, or a source of the gate tube or the transistor may be used as the readout line.
In the embodiment of the present application, when the synapse circuit controls the first pulse interface 6 to apply the first pulse to the first memory 4, since the first memory 4 is connected in series with the second memory 5, the conductance of the second memory 5 will also change under the effect of the first pulse, but will not reach the conductance for storing data.
By adopting the data processing method provided by the embodiment of the application, the first switching tube or the second switching tube is controlled to be in a working state according to the data processing instruction received by the first bit line interface or the second bit line interface, and the first pulse is applied to the first memory or the second pulse is applied to the second memory, so that high and low bit data are stored. In addition, when data is read, the first bit line interface and the word line interface are controlled to be in an operating state, and data in the bit line of the address corresponding to the word line is read.
It should be noted that: the foregoing descriptions of the embodiments of the present application are provided for illustration only and not for the purpose of limiting the invention as defined by the appended claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be implemented.
All the embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment is described with emphasis on differences from other embodiments. In particular, as for the embodiment of the apparatus, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
Those skilled in the art will appreciate that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing associated hardware, and the program may be stored in a computer readable medium.
The foregoing is a preferred embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the embodiment of the present application, and these modifications and decorations are also considered to be the protection scope of the embodiment of the present application.
Claims (10)
1. A synaptic electrical circuit, comprising: a first memristor, a second memristor, and a switching component;
the switch assembly comprises a first switch tube, a second switch tube and a third switch tube;
the first end of the first switching tube is connected with the first end of the first memristor, and the control end of the first switching tube is connected with the first bit line interface;
the first end of the second switching tube is connected with the first end of the second memristor, and the control end of the second switching tube is connected with the second bit line interface;
a second end of the first memristor is connected with a first end of the second memristor;
the first end of the third switching tube is connected with the second end of the second memristor, the second end of the third switching tube is connected with the word line interface, and the third end of the third switching tube is grounded.
2. The circuit of claim 1, further comprising: a first pulse interface and a second pulse interface;
the first pulse interface is connected with the second end of the first switching tube;
the second pulse interface is connected with the second end of the second switch tube.
3. The circuit of claim 1,
the first bit line interface is used for being connected with a first bit line and controlling the switch of the first switch tube;
and the second bit line interface is used for being connected with a second bit line and controlling the switch of the second switch tube.
4. The circuit of claim 1, further comprising: a read line interface;
the readout line interface is connected with the first end of the third switching tube.
5. The circuit of claim 1, wherein the first memristor and the second memristor are any one of a phase change memory or an impedance random access memory or a memristor-like non-volatile memory;
the switch component comprises any one of a gate tube, a diode, a triode or a switch.
6. An array of synapses, comprising the synapse circuit of any of claims 1-5.
7. The synapse array of claim 6, wherein one end of the synapse array is connected to a signal input, and the other end of the synapse array is connected to a signal output;
the synapse array comprises n × m synapse circuits, wherein n is the number of rows of the synapse array, and m is the number of columns of the synapse array.
8. The array of synapses of claim 6, further comprising a first bit line, a second bit line, a word line, and a sense line;
the first bit line interfaces of the n x m synapse circuits are respectively connected with the corresponding first bit lines;
the second bit line interfaces of the n x m synapse circuits are respectively connected with the corresponding second bit lines;
word line interfaces of the n × m synapse circuits are respectively connected with the corresponding word lines;
and the readout line interfaces of the n × m synapse circuits are respectively connected with the corresponding readout lines.
9. A method of data processing based on synaptic electrical circuits, wherein the synaptic electrical circuits comprise the synaptic electrical circuits of any one of claims 1-5, comprising:
receiving a data processing instruction;
if the data processing instruction is a low-bit data storage instruction, enabling a first bit line interface to receive a first working instruction; the first working instruction is used for controlling the first switching tube to be in a working state;
control a first pulse interface to apply a first pulse to a first memristor; the first pulse is to change a conductance of the first memristor to store low bit data;
if the data processing instruction is a high-bit data storage instruction, enabling a second bit line interface to receive a second working instruction; the second working instruction is used for controlling a second switching tube to be in a working state;
controlling a second pulse interface to apply a second pulse to a second memristor; the second pulse is to change a conductance of the second memristor to store high bit data.
10. The method of claim 9, further comprising:
if the data processing instruction is a data reading instruction, enabling the first bit line interface to receive the first working instruction, wherein the first working instruction is used for controlling the first switching tube to be in a working state; controlling the word line interface to be in a working state;
the data reading instruction carries a word line address, the word line address is used for determining a word line for obtaining data, and the data is read by the word line from a bit line connected with a first bit line interface through a word line interface connected with the word line and the first bit line interface corresponding to the word line interface.
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