CN110619834B - Multi-clock potential conversion circuit and multi-clock gate driving circuit - Google Patents
Multi-clock potential conversion circuit and multi-clock gate driving circuit Download PDFInfo
- Publication number
- CN110619834B CN110619834B CN201910768317.2A CN201910768317A CN110619834B CN 110619834 B CN110619834 B CN 110619834B CN 201910768317 A CN201910768317 A CN 201910768317A CN 110619834 B CN110619834 B CN 110619834B
- Authority
- CN
- China
- Prior art keywords
- clock
- shift register
- circuit
- signals
- register unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 13
- 230000000630 rising effect Effects 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 12
- 239000013256 coordination polymer Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 101000975474 Homo sapiens Keratin, type I cytoskeletal 10 Proteins 0.000 description 2
- 102100023970 Keratin, type I cytoskeletal 10 Human genes 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
A multi-clock potential converting circuit and a multi-clock gate driving circuit. The multi-clock pulse potential conversion circuit comprises a shift register unit and a clock pulse voltage lifting circuit. The shift register unit is configured to output a plurality of shift register clock signals according to the control clock signal. The clock pulse voltage lifting circuit is connected with the shift register unit and correspondingly outputs the display clock pulse signals according to the shift register clock pulse signals. The multi-clock potential conversion circuit saves the clock control circuit from outputting the multi-clock display signals, saves the input and output interface resources of the clock control circuit, simplifies the external circuit of the gate driving circuit substrate and reduces the production cost of the display device.
Description
[ technical field ] A method for producing a semiconductor device
The present disclosure relates to the field of display technologies, and more particularly, to a multi-clock potential converting circuit and a multi-clock gate driving circuit.
[ background ] A method for producing a semiconductor device
With the development of Gate On Array (GOA) panels, multi-clock panel driving is becoming an important trend.
Please refer to fig. 1, fig. 2 and fig. 3, which are schematic diagrams of a conventional two-input-channel four-output-channel voltage converting circuit block, a conventional four-input-channel four-output-channel voltage converting circuit block, and a conventional twelve-input-twelve-output-channel voltage converting circuit block, respectively. In addition, the circuit architecture of fig. 1 and fig. 2 is difficult to meet the actual driving requirement, and further matching with a plurality of voltage level converters to perform voltage level conversion will increase the manufacturing cost of the gate driving circuit substrate.
Although the circuit structure of fig. 3 has enough output channels, it needs to occupy twelve input/output interfaces of the clock control circuit at the same time, and if the input/output interfaces are newly opened for the clock control circuit, the production cost of the display device will be greatly increased even if the input/output interfaces are newly opened.
Therefore, it is desirable to provide a clock control apparatus and a driving method thereof to solve the problems of the prior art.
[ summary of the invention ]
To solve the above problems, the present disclosure provides a multi-clock potential converting circuit and a multi-clock gate driving circuit, which can output multi-clock display signals, save the input/output interface resources of the clock control circuit, simplify the external circuit of the gate driving circuit substrate, and reduce the production cost of the display device.
To achieve the above object, the present disclosure provides a multi-clock level conversion circuit configured to output a plurality of display clock signals for controlling a display screen of a display device according to a control clock signal. Includes a shift register unit configured to output a plurality of shift register clock signals according to the control clock signal. And the clock pulse voltage lifting circuit is connected with the shift register unit and correspondingly outputs the display clock pulse signals according to the shift register clock pulse signals.
In one embodiment of the present disclosure, the shift register unit further includes a multiplexing interface device, and the multiplexing interface device is connected to the clock control circuit.
In one embodiment of the present disclosure, the multiplexing interface device comprises 2 input/output interfaces.
In one embodiment of the present disclosure, the shift register unit is composed of a plurality of D flip-flops.
In one embodiment of the present disclosure, the shift register unit further outputs other signals other than the shift register clock signal.
In one embodiment of the present disclosure, the shift register unit is connected to the clock voltage boost circuit through a plurality of shift register contacts.
To achieve the above object, the present disclosure also provides a multi-clock gate driving circuit configured to output a plurality of display clock signals for controlling a display screen of a display device, including:
a clock control circuit configured to output a control clock signal. A shift register unit comprising a multiplexing interface device, the shift register unit being connected to the clock control circuit through the multiplexing interface device, the shift register unit being configured to output a plurality of shift register clock signals according to the control clock signal. The clock voltage raising circuit is configured to be connected with the shift register unit, and the clock voltage raising circuit receives the plurality of shift register clock signals and correspondingly generates the plurality of display clock signals according to the initial clock signal. The shift register unit is composed of a plurality of D triggers.
In one embodiment of the present disclosure, the shift register unit is connected to the clock voltage boost circuit through a plurality of shift register contacts.
In one embodiment of the present disclosure, the shift register unit further outputs other signals than the shift register clock signal.
In one embodiment of the present disclosure, the multiplexing interface device includes two input/output interfaces.
In order to make the aforementioned and other aspects of the present disclosure more comprehensible, preferred embodiments accompanied with figures are described in detail below:
[ description of the drawings ]
FIG. 1 is a block diagram of a conventional dual-input-channel four-output-channel potential conversion circuit;
FIG. 2 is a block diagram of a conventional four-input-channel and four-output-channel voltage level shifting circuit;
FIG. 3 is a block diagram of a conventional twelve-input twelve-output channel level shift circuit;
FIG. 4 is a block diagram of a multi-clock level shift circuit according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a shift register cell layout according to an embodiment of the present disclosure;
FIG. 6 is a diagram illustrating clock waveforms output through a shift register unit according to an embodiment of the disclosure.
FIG. 7 is a block diagram of a multi-clock gate driving circuit according to an embodiment of the present disclosure.
[ detailed description ] embodiments
The following description of the embodiments refers to the accompanying drawings, which are included to illustrate specific embodiments in which the disclosure may be practiced. Directional phrases used in this disclosure, such as [ upper ], [ lower ], [ front ], [ back ], [ left ], [ right ], [ inner ], [ outer ], [ side ], etc., refer only to the directions of the attached drawings. Accordingly, the directional terms used are used for the purpose of illustration and understanding of the present disclosure, and are not used to limit the present disclosure.
In the drawings, elements having similar structures are denoted by the same reference numerals.
Referring to fig. 4, fig. 4 is a block diagram of a multi-clock voltage converting circuit according to an embodiment of the disclosure. Wherein, the multi-clock potential converting circuit 40 is configured to output a plurality of display clock signals for controlling the display screen of the display device according to the control clock signal. The plurality of display clock signals include a first display clock signal CK1, a second display clock signal CK2, a third display clock signal CK3, a fourth display clock signal CK4, a fifth display clock signal CK5, a sixth display clock signal CK6, a seventh display clock signal CK7, an eighth display clock signal CK8, a ninth display clock signal CK9, a tenth display clock signal CK10, an eleventh display clock signal CK11, and a twelfth display clock signal CK12. The multi-clock level shifter 40 includes a shift register unit 401 and a clock voltage raising circuit 402. The shift register unit 401 is configured to output a plurality of shift register clock signals according to the control clock signal, wherein the shift register clock signals include a first shift register clock signal CK1', a second shift register clock signal CK2', a third shift register clock signal CK3', a fourth shift register clock signal CK4', a fifth shift register clock signal CK5', a sixth shift register clock signal CK6', a seventh shift register clock signal CK7', an eighth shift register clock signal CK8', a ninth shift register clock signal CK9', a tenth shift register clock signal CK10', an eleventh shift register clock signal CK11', and a twelfth shift register clock signal CK12'. The clock voltage boosting circuit 402 is configured to be connected to the shift register unit 401, and the clock voltage boosting circuit 402 respectively boosts each of the shift register clock signals according to the shift register clock signals and correspondingly outputs the display clock signals.
In some embodiments of the present disclosure, the shift register unit 401 further outputs an OTHS signal other than the shift register clock signal.
In one embodiment of the present disclosure, the clock voltage boost circuit 402 processes signals only through the register clock signal contact that outputs the shift register clock signal, and does not process other signals OTHS output by the shift register unit 401, and the clock voltage boost circuit 402 outputs the other signals OTHS, thereby achieving the effect of filtering the register clock signal.
In one embodiment of the present disclosure, the clock voltage boost circuit 402 processes all signals output by the shift register unit 401, in other words, when the shift register unit 401 outputs other signals OTHS, the clock voltage boost circuit 402 boosts the other signals OTHS and then outputs the other signals OTHS, so that the effect of the clock voltage boost circuit 402 boosting all signals output by the shift register unit 401 is achieved.
Referring to fig. 5, fig. 5 is a schematic diagram of a shift register unit layout according to an embodiment of the present disclosure. The shift register unit 401 receives a control clock signal CK and a shift clock signal CP. The shift register unit consists of a plurality of D triggers, wherein the D triggers comprise a first D trigger D1, a second D trigger D2, a D interface of the second D trigger D2 is connected with a Q interface of the first D trigger D1, a third D trigger D3, a D interface of the third D trigger D3 is connected with a Q interface of the second D trigger D2, a fourth D trigger D4, a D interface of the fourth D trigger D4 is connected with a Q interface of the third D trigger D3, a fifth D trigger D5, a D interface of the fifth D trigger D5 is connected with a Q interface of the fourth D trigger D4, a sixth D trigger D6, a D interface of the sixth D trigger D6 is connected with a Q interface of the fifth D trigger D5, a seventh D trigger D7, a D interface of the seventh D trigger D7 is connected with a Q interface of the sixth D trigger D6, a D interface of the eighth D8 is connected with a Q interface of the ninth D trigger D8, a ninth D11, a ninth D interface of the eighth D8 is connected with a Q interface of the ninth D9, a ninth D11, a tenth D11 and a tenth D11. In other words, between the D flip-flops arranged adjacently, the Q interface of the D flip-flop arranged in the previous stage is connected to the D interface of the D flip-flop arranged in the next stage. The D flip-flops respectively receive the shift clock signal CP and are respectively connected with a return-to-zero point R.
In one embodiment of the present disclosure, the shift register unit further includes a multiplexing interface device, and the multiplexing interface device is connected to the clock control circuit.
In one embodiment of the present disclosure, the multiplexing interface device includes 2 input/output interfaces, and the shift register unit 401 receives the control clock signal CK and the shift clock signal CP through the multiplexing interface device, respectively.
Referring to fig. 4 and 5, the shift register unit is connected to the clock voltage boosting circuit through a plurality of shift register contacts. The shift register contacts comprise a first shift register contact arranged between the output end of the control clock signal CK and a D interface of the first D trigger D1, a second shift register contact arranged between a second D trigger D2 and a Q interface of the first D trigger D1, a third shift register contact arranged between a third D trigger D3 and a Q interface of the second D trigger D2, a fourth shift register contact arranged between a fourth D trigger D4 and a Q interface of the third D trigger D3, a fifth shift register contact arranged between a fifth D trigger D5 and a Q interface of the fourth D trigger D4, a sixth shift register contact arranged between a Q interface of the sixth D trigger D6 and a Q interface of the fifth D trigger D5, a seventh shift register contact arranged between a Q interface of the seventh D trigger D7 and a Q interface of the sixth D trigger D6, a ninth shift register contact arranged between a Q7 of the eighth D trigger D8 and the seventh D trigger D7, a tenth shift register contact arranged between a ninth D trigger D11 and a tenth shift register D11, and a ninth shift register contact arranged between a Q interface of the ninth D8 and the eleventh D trigger D11, and a tenth shift register D11 arranged between a ninth D trigger D interface of the eleventh D trigger D9 and a tenth D trigger D11. The number of D flip-flops is less than the number of shift register contacts.
In one embodiment of the present disclosure, the number of D flip-flops is 1 less than the number of shift register contacts.
Referring to fig. 5 and fig. 6, fig. 6 is a schematic diagram showing clock waveforms of output signals of shift register contacts of a shift register unit according to an embodiment of the present disclosure. As shown, the shift register unit 401 generates the shift register clock signals, and the phases of the shift register clock signals are determined by the rising edge of the shift clock signal CP and the control clock signal CK. More specifically, each time the shift clock signal CP reaches a rising edge, the shift register contacts sequentially output a control clock signal CK.
Referring to FIG. 7, FIG. 7 is a block diagram of a multi-clock gate driving circuit according to an embodiment of the present disclosure. The multi-clock gate driving circuit 70 is configured to output a plurality of display clock signals for controlling a display screen of the display device. The multi-clock gate driving circuit 70 includes a clock control circuit 703, a shift register unit 701 and a clock voltage boosting circuit 702. The clock control circuit 703 is configured to output a control clock signal CK, a shift clock signal CP and other signals OTHS. The shift register unit 701 includes a multiplexing interface device configured to output a plurality of shift register clock signals. The clock voltage boost circuit 702 is connected to the shift register unit 701, and the clock voltage boost circuit 702 receives the shift register clock signals and generates the display clock signals according to the initial clock signal, wherein the shift register unit is composed of a plurality of D flip-flops.
In one embodiment of the present disclosure, the shift register unit 701 is connected to the clock control circuit 703 through a multiplexing interface device.
In summary, the present disclosure provides a multi-clock level converting circuit and a multi-clock gate driving circuit for outputting a display clock signal for controlling a display screen of a display device. The multi-clock potential conversion circuit includes a shift register unit configured to output a plurality of shift register clock signals. And the clock pulse voltage lifting circuit is connected with the shift register unit, receives the plurality of shift register clock pulse signals and correspondingly generates the plurality of display clock pulse signals according to the initial clock pulse signal. Wherein the number of the shift register clock signals is the same as the number of the display clock signals. The multi-clock potential conversion circuit saves the clock control circuit from outputting the multi-clock display signals, saves the input and output interface resources of the clock control circuit, simplifies the external circuit of the gate driving circuit substrate and reduces the production cost of the display device.
The foregoing is merely a preferred embodiment of the present disclosure, and it should be noted that modifications and refinements may be made by those skilled in the art without departing from the principle of the present disclosure, and these modifications and refinements should also be construed as the protection scope of the present disclosure.
Claims (8)
1. A multi-clock potential converting circuit configured to output a plurality of display clock signals for controlling a display screen of a display device according to a control clock signal, comprising:
a shift register unit configured to output a plurality of shift register clock signals according to the control clock signal;
the shift register unit is also used for receiving a control clock pulse signal and a shift clock pulse signal; wherein the phases of the shift register clock signals are determined by the rising edge of the shift clock signal and the control clock signal; and
the clock voltage lifting circuit is configured to be connected with the shift register unit and correspondingly outputs the display clock signals according to the shift register clock signals;
the shift register unit is connected with the clock pulse voltage lifting circuit through a plurality of shift register contacts, and the shift register contacts output control clock pulse signals in sequence when the shift clock pulse signals reach a rising edge.
2. The multi-clock potential conversion circuit of claim 1, wherein the shift register unit further comprises a multiplexing interface device, the multiplexing interface device being connected to the clock control circuit.
3. The multi-clock potential conversion circuit of claim 2, wherein the multiplexing interface means comprises 2 input-output interfaces.
4. The multi-clock potential conversion circuit of claim 1, wherein the shift register unit is comprised of a plurality of D flip-flops.
5. The multi-clock potential conversion circuit of claim 1, wherein the shift register unit further outputs other signals than the shift register clock signal.
6. A multi-clock gate driving circuit configured to output a plurality of display clock signals for controlling a display screen of a display device, comprising:
a clock control circuit configured to output a control clock signal;
a shift register unit comprising a multiplexing interface device, the shift register unit configured to be connected with the clock control circuit through the multiplexing interface device, the shift register unit configured to output a plurality of shift register clock signals according to the control clock signal;
the shift register unit is also used for receiving a control clock pulse signal and a shift clock pulse signal; wherein the phase of the shift register clock signals is determined by the rising edge of the shift clock signal and the control clock signal; and
the clock voltage lifting circuit is configured to be connected with the shift register unit, receives the plurality of shift register clock signals and correspondingly generates the plurality of display clock signals according to the shift register clock signals;
the shift register unit is connected with the clock pulse voltage lifting circuit through a plurality of shift register contacts, and the shift register contacts output control clock pulse signals in sequence when the shift clock pulse signals reach a rising edge;
the shift register unit is composed of a plurality of D triggers.
7. The multi-clock gate driver circuit of claim 6, wherein the shift register unit further outputs other signals than the shift register clock signal.
8. The multi-clock gate driver circuit as claimed in claim 6, wherein the multiplexing interface device comprises 2 input/output interfaces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910768317.2A CN110619834B (en) | 2019-08-20 | 2019-08-20 | Multi-clock potential conversion circuit and multi-clock gate driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910768317.2A CN110619834B (en) | 2019-08-20 | 2019-08-20 | Multi-clock potential conversion circuit and multi-clock gate driving circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110619834A CN110619834A (en) | 2019-12-27 |
| CN110619834B true CN110619834B (en) | 2022-10-04 |
Family
ID=68922295
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910768317.2A Active CN110619834B (en) | 2019-08-20 | 2019-08-20 | Multi-clock potential conversion circuit and multi-clock gate driving circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110619834B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111128088A (en) * | 2020-01-17 | 2020-05-08 | Tcl华星光电技术有限公司 | Driving circuit and display panel applying same |
| CN111261093B (en) * | 2020-03-25 | 2021-08-24 | Tcl华星光电技术有限公司 | Display panel |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI233125B (en) * | 2004-06-24 | 2005-05-21 | Toppoly Optoelectronics Corp | Shift register and a shift register |
| TWI317920B (en) * | 2005-10-14 | 2009-12-01 | Toppoly Optoelectronics Corp | Systems for driving a display |
| TWI340941B (en) * | 2006-05-19 | 2011-04-21 | Chimei Innolux Corp | System for displaying image |
| CN100587785C (en) * | 2006-05-26 | 2010-02-03 | 统宝光电股份有限公司 | System for displaying image and liquid crystal display driving method |
| US20090146704A1 (en) * | 2007-12-05 | 2009-06-11 | Chih-Haur Huang | Delay locked loop circuit and method for eliminating jitter and offset therein |
| US7750715B2 (en) * | 2008-11-28 | 2010-07-06 | Au Optronics Corporation | Charge-sharing method and device for clock signal generation |
| CN101510443A (en) * | 2009-04-08 | 2009-08-19 | 友达光电股份有限公司 | Shift register capable of reducing coupling effect |
| TWI533272B (en) * | 2014-09-26 | 2016-05-11 | 友達光電股份有限公司 | Display device and driving method thereof |
-
2019
- 2019-08-20 CN CN201910768317.2A patent/CN110619834B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN110619834A (en) | 2019-12-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106683634B (en) | A kind of shift register, GOA circuit and its driving method, display device | |
| EP3270370A1 (en) | Shift register and driving method therefor, gate drive circuit and display apparatus | |
| CN108806571B (en) | Gate drive circuit and drive method thereof, array substrate and display device | |
| CN104966506B (en) | The driving method and relevant apparatus of a kind of shift register, display panel | |
| CN107633834B (en) | Shift register unit, driving method thereof, grid driving circuit and display device | |
| CN101937718B (en) | Bidirectional shift register | |
| CN106952602B (en) | Inverter module, shift register unit, array substrate and display device | |
| CN105161042B (en) | A kind of array base palte, display panel and display device | |
| CN104992661A (en) | Shift register circuit and driving method thereof, gate drive circuit and display apparatus | |
| EP3333842A1 (en) | Shift register, gate driving circuit, display panel and driving method therefor, and display device | |
| CN102903322B (en) | Shift register and driving method thereof and array base palte, display device | |
| CN105096902A (en) | Shift register, driving method thereof, gate drive circuit and display device | |
| CN105118417A (en) | Shifting register and driving method thereof as well as gate drive circuit and display device | |
| CN110619834B (en) | Multi-clock potential conversion circuit and multi-clock gate driving circuit | |
| CN108766340A (en) | Shift register cell and its driving method, gate driving circuit and display device | |
| CN105469738A (en) | Shift register, grid drive circuit and display device | |
| CN105096803A (en) | Shift register and driving method thereof, grid driving circuit, and display apparatus | |
| CN107154236B (en) | Shift register unit and driving method thereof, scanning driving circuit and display device | |
| CN105118418A (en) | Shifting register and driving method thereof as well as gate drive circuit and display device | |
| CN103151013B (en) | Gate driver circuit | |
| CN106373538B (en) | Shifting register and driving method thereof, grid driving circuit and array substrate | |
| CN106710510A (en) | Grid driving unit and driving method, grid driving circuit and display device | |
| CN105185412A (en) | Shifting register unit and driving method thereof, grid driving circuit and display device | |
| CN110322847A (en) | Gate driving circuit, display device and driving method | |
| US6621478B1 (en) | Semiconductor device and display module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant after: TCL China Star Optoelectronics Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |