CN110610936B - Bonding-based monolithic heterogeneous integrated Cascode gallium nitride high-mobility transistor and manufacturing method - Google Patents
Bonding-based monolithic heterogeneous integrated Cascode gallium nitride high-mobility transistor and manufacturing method Download PDFInfo
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Abstract
The invention discloses a monolithic heterogeneous integrated Cascode gallium nitride high mobility transistor based on bonding, which mainly solves the problem that the conventional Cascode gallium nitride high electron mobility transistor cannot be integrated on a large-area monolithic. It comprises from top to bottom: the GaN-based high-electron-mobility transistor comprises a substrate (1), a GaN buffer layer (2) and an AlGaN barrier layer (3), wherein an isolation groove (4) is formed in the middle of the AlGaN barrier layer (3) and used for electrically isolating a GaN-based high-electron-mobility transistor and a Si-based metal oxide semiconductor field effect transistor; and a Si active layer (5) is printed on the AlGaN barrier layer (3) on one side of the isolation groove to form a monolithic chip with silicon and gallium nitride heterointegrated. The invention can realize wafer-level manufacturing, enhances the reliability of devices, improves the integration level of chips, and can be used for power supply control and conversion scenes of power supply converters and inverters.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a Cascode gallium nitride high-mobility transistor based on a bonding technology and a manufacturing method thereof, which can be used as a power converter or a phase inverter of automobiles, aerospace and power stations.
Technical Field
In the background of the era of post moore's law, it has become very difficult to increase the degree of integration by means of conventional shrinking transistor dimensions. The current electronic systems are developing toward miniaturization, diversification and intellectualization, and finally form microsystems with functions of perception, communication, processing, transmission and the like. The core technology of microsystems is integration, and the integration technology is developing from planar integration to three-dimensional integration, from chip level to system integration with higher integration and complexity. In recent years, semiconductor process technology has been rapidly developed, and is embodied not only in conventional semiconductor processes such as radio frequency, analog, and mixed signal, but also in non-conventional semiconductor processes such as heterogeneous integration of systems. Heterogeneous integration is divided into hybrid integration and monolithic integration, wherein hybrid integration is an integration way realized by bonding chips of different substrate materials through packaging, and represents a technology of three-dimensional chip stacking, similar to the concept of system in package SiP; the monolithic integration is to integrate devices with different functions on a single chip, so that the packaging of the chips is omitted, but the manufacturing difficulty of the process for realizing the monolithic integration by growing heterogeneous materials through an epitaxial method is higher, the quality of the epitaxial materials is limited by the lattice mismatch degree between the epitaxial materials and a substrate material, if the lattice mismatch degree is too high, a large number of defects can be generated in the epitaxial layers, even single crystals can not be grown, and the performance and the service life of the devices are influenced.
In the late 20 th century and 80 s, scientists have grown high-quality GaN and AlGaN on silicon carbide and sapphire substrates by inserting a gallium nitride buffer layer, and then GaN high-electron-mobility transistors have entered the rapid development period. GaN hemt devices have many advantages: the high-voltage-resistant and high-frequency-resistant power supply has the advantages of high working voltage and working frequency, low on resistance, small input and output capacitance and high radiation resistance and high temperature resistance. Due to the above advantages, GaN hemts are often used in power electronics and microwave fields, and enhancement GaN hemts also have advantages of reducing design cost and expanding application fields compared to depletion GaN hemts. For example, when designing a microwave high-power chip, the enhancement mode GaN hemt device does not need a power supply design with negative gate voltage because of having a positive threshold voltage, which greatly reduces the design cost of the chip; in addition, enhancement mode GaN hemts are turned on only at positive gate voltages and thus can be used in low power digital circuits. Because of the many advantages of enhancement mode gan hemts, much research has been conducted on these devices. In order to realize enhancement-mode gan hemts, various manufacturing methods are used, wherein the common method is to use a Cascode structure composed of a low-voltage enhancement-mode mosfet and a high-voltage depletion-mode gan hemt. By the structure, the gallium nitride high-electron-mobility transistor device which is originally in a depletion mode can be more conveniently conducted to work when forward grid voltage is applied.
Currently, international rectifier corporation IR and Transform corporation are both working on developing enhancement GaN hemt devices based on this structure. However, until now, the fabrication of the gallium nitride hemt device with the Cascode structure is still based on hybrid integration, that is, the fabrication is realized by packaging and bonding a silicon chip and a gallium nitride chip, as shown in fig. 1, the chip fabricated based on hybrid integration has low integration level and large area, cannot meet the development requirements of miniaturization and high integration of the electronic system nowadays, and is not beneficial to the continuation of moore's law.
Disclosure of Invention
The invention aims to provide a Cascode gallium nitride high-mobility transistor based on a bonding technology and a manufacturing method thereof aiming at the defects of the prior art, so as to realize wafer-level heterogeneous integration, reduce the process cost of monolithic integration, enhance the reliability of devices and improve the integration level of chips.
The technical key point for realizing the aim is as follows: the SOI substrate and the AlGaN/GaN/substrate are bonded together by adopting a bonding technology, and the Cascode gallium nitride high mobility transistor is manufactured on the basis, and the realization scheme is as follows:
a semiconductor transistor of Cascode gallium nitride high mobility based on bonding technique and its manufacturing method, is formed by GaN high electron mobility transistor and Si metal oxide semiconductor field effect transistor, it includes: the GaN-based high-electron-mobility transistor comprises a substrate (1), a GaN buffer layer 2, an AlGaN barrier layer 3 and a Si active layer 4, wherein the substrate 1, the GaN buffer layer 2 and the AlGaN barrier layer 3 are distributed from bottom to top, and a source electrode 5, a gate electrode 6 and a drain electrode 7 of the GaN-based high-electron-mobility transistor are arranged on the AlGaN barrier layer 3 on one side of an isolation groove; a source electrode 8 and a drain electrode 11 of the Si metal oxide semiconductor field effect transistor are arranged on two sides of the Si active layer 4 on the other side of the isolation groove, a gate dielectric layer 9 is arranged between the source electrode and the drain electrode, and a gate electrode 10 is arranged on the gate dielectric layer 9; the method is characterized in that:
an isolation groove is formed in the middle of the AlGaN barrier layer 3 and used for electrically isolating the GaN high electron mobility transistor and the Si metal oxide semiconductor field effect transistor;
and a Si active layer 4 is bonded on the AlGaN barrier layer 3 on one side of the isolation groove to form a monolithic chip with silicon and gallium nitride heterointegrated.
Further, it is characterized in that: the AlGaN barrier layer 3 has an isolation groove in the middle thereof as deep as the GaN buffer layer 2 to cut off the two-dimensional electron gas and prevent leakage between devices.
Further, it is characterized in that: the drain electrode 11 of the Si metal oxide semiconductor field effect transistor is electrically connected with the source electrode 5 of the GaN high electron mobility transistor through a first metal interconnection bar 12; the source electrode 8 of the Si metal oxide semiconductor field effect transistor and the gate electrode 6 of the GaN high electron mobility transistor are electrically connected by a second metal interconnection bar 13.
Further, it is characterized in that:
the thickness of the substrate 1 is 400-500 mu m, and the material is sapphire, SiC or silicon;
further, it is characterized in that:
the thickness of the GaN buffer layer 2 is 1-2 μm;
the AlGaN barrier layer 3 has a thickness of 20-30 nm;
the thickness of the Si active layer 4 is 100-200 nm.
Further, it is characterized in that:
the thickness of the source electrode 5 and the drain electrode 7 of the GaN high electron mobility transistor are both 262 nm;
the thickness of the gate electrode 6 of the GaN high electron mobility transistor was 145 nm;
the thickness of the source electrode 8 and the drain electrode 11 of the Si metal oxide semiconductor field effect transistor are both 30-100 nm;
the thickness of a gate dielectric layer 9 of the Si metal oxide semiconductor field effect transistor is 10-20 nm;
the thickness of the gate electrode 10 of the Si metal oxide semiconductor field effect transistor is 100-150 nm;
the thickness of the first metal interconnection bar 12 and the second metal interconnection bar 13 are both 200-300 nm.
The manufacturing method of the Cascode gallium nitride high-mobility transistor based on the bonding technology is characterized by comprising the following steps of:
1) adopting a wafer cleaning process, carrying out ultrasonic treatment on the AlGaN/GaN/Substrate for 5min by using acetone, ethanol and deionized water in sequence, and then carrying out ultrasonic treatment on the AlGaN/GaN/Substrate by using a piranha solution (H)2O2:H2SO4Soaking for 5min in a ratio of 1:3) to obtain a high-purity AlGaN/GaN/Substrate;
2) depositing silicon dioxide with the thickness of 1 mu m on a clean AlGaN/GaN/Substrate by adopting a plasma chemical vapor deposition process to form an isolation buffer layer;
3) annealing the sample on which the silicon dioxide isolation buffer layer grows by adopting a high-temperature annealing process so as to compact the silicon dioxide;
4) grinding the silicon dioxide isolation buffer layer by adopting a chemical mechanical polishing process to reduce the surface roughness to 0.3-0.4nm, and preparing for successful bonding;
5) cleaning SOI substrate with acetone, ethanol, and deionized water sequentially for 5min, and adding into piranha solution (H)2O2:H2SO4Soaking in 1:3) for 5min, and adding diluted hydrofluoric acid solution (HF: H)2O is 1:50) for 1min to obtain a highly clean SOI substrate;
6) bonding the SOI Substrate obtained in the step 5) with an AlGaN/GaN/Substrate by adopting a wafer bonding technology, and then reinforcing the bonding effect by adopting a high-temperature annealing process;
7) removing the SOI substrate and the buried oxide layer in the bonded sample by adopting chemical mechanical polishing and wet etching processes, so that only the top silicon film is reserved on the SOI substrate part of the bonded sample;
8) etching the table top of the active area of the silicon device on the smooth silicon film of the sample obtained in the step 7) by adopting a reactive ion etching process; etching the middle part of the AlGaN/GaN/Substrate to form an isolation groove, wherein the other side of the isolation groove is the table top of the active region of the gallium nitride device;
9) injecting phosphorus ions on the table top of the active region of the silicon device by adopting an ion injection process to form a source drain doped region of the silicon metal oxide semiconductor field effect transistor;
10) adopting a wet etching process, removing silicon dioxide at a corresponding position of a table top of an active area of a gallium nitride device by using a BOE buffer solution, and then adopting an electron beam evaporation process to sequentially deposit 22nm of Ti, 140nm of Al, 55nm of Ni and 45nm of Au on the table top of the active area of the gallium nitride device to form a source electrode and a drain electrode of the gallium nitride high electron mobility transistor;
11) adopting an annealing process to fuse a source drain electrode of the gallium nitride device with AlGaN to form ohmic contact and activate source drain doping of the silicon device;
12) removing silicon dioxide at the corresponding position of the table top of the active area of the gallium nitride device in the sample obtained in the step 11) by using a BOE buffer solution by adopting a wet etching process, and then sequentially depositing Ni and Au on the table top of the active area of the gallium nitride device by adopting an electron beam evaporation process, wherein the thicknesses of the Ni and the Au are 45nm and 150nm respectively to form a gate electrode of the GaN high electron mobility transistor;
13) depositing HfO with a thickness of 10nm on the sample obtained in step 12) by using an atomic layer deposition process2A dielectric layer;
14) adopting an electron beam evaporation process to obtain HfO of the mesa of the active region of the silicon device in the sample obtained in the step 13)2Sequentially depositing Ni and Au on the dielectric layer, wherein the thicknesses of the Ni and the Au are respectively 20nm and 120nm, and forming a gate electrode of the Si metal oxide semiconductor field effect transistor;
15) removing HfO at the corresponding position of the mesa of the active region of the silicon device in the sample obtained in step 14) by adopting a reactive ion etching process2The dielectric layer is then removed of HfO by electron beam evaporation2Depositing Ni with the thickness of 30nm at the position of the silicon device, and annealing to form ohmic contact between a source drain electrode and a source drain doped region of the silicon device;
16) adopting a reactive ion etching process to cover HfO on the source and drain electrodes of the mesa gate of the active region of the gallium nitride device in the step 13)2The dielectric layer is removed and the dielectric layer is removed,exposing the grid source drain of the GaN high electron mobility transistor;
17) and (3) depositing Ni with the thickness of 45nm and Au with the thickness of 200nm respectively between the drain electrode of the Si metal oxide semiconductor field effect transistor and the source electrode of the GaN high electron mobility transistor and between the source electrode of the Si metal oxide semiconductor field effect transistor and the grid electrode of the GaN high electron mobility transistor in sequence by adopting an electron beam evaporation process to form metal interconnection, thereby completing the Cascode gallium nitride high mobility transistor based on the bonding technology and the manufacturing method thereof.
Compared with the prior art, the invention not only enables the monolithic heterogeneous integration of Si and GaN to reach the wafer-level integration size due to using the bonding technology as the monolithic heterogeneous integration means, but also realizes the wafer-level heterogeneous integration of the Cascode enhanced gallium nitride high electron mobility transistor device realized by the method, reduces the process cost of the monolithic integration, enhances the reliability of the device and improves the chip integration level.
Drawings
FIG. 1 is a schematic diagram of a prior art Cascode structure gallium nitride HEMT device;
FIG. 2 is a schematic diagram of a Cascode structure GaN HEMT device of the present invention;
fig. 3 is a schematic flow chart of the method for fabricating a gallium nitride hemt device of the present invention.
Detailed Description
Referring to fig. 2, the monolithic heterogeneous integrated Cascode GaN high electron mobility transistor based on bonding technology of the present invention is composed of a GaN high electron mobility transistor and a Si metal oxide semiconductor field effect transistor, and comprises from bottom to top: 400-500 mu m thick substrate 1, 1-2 mu m thick GaN buffer layer 2, and 20-30nm thick AlGaN barrier layer 3. Wherein, the substrate material 1 is a sapphire substrate, a SiC substrate or a silicon substrate; an isolation groove 4 is formed in the middle of the AlGaN barrier layer 3 to the GaN buffer layer 2 to cut off the two-dimensional electron gas and prevent leakage between devices.
An Si active layer with a thickness of 100-200nm is bonded on the AlGaN barrier layer 3 on the side of the isolation trench 45, a source electrode 9 and a drain electrode 12 with the thickness of 20-40nm are arranged on two sides of the Si active layer 5; HfO with the thickness of 10-20nm is arranged between the source electrode and the drain electrode2As a gate dielectric layer 10; the gate dielectric layer 10 is provided with a gate electrode 11 with the thickness of 150-250nm, and the silicon metal oxide semiconductor field effect transistor is formed.
The AlGaN barrier layer 3 on the other side of the isolation groove is provided with a source electrode 6 and a drain electrode 8 with the thickness of 262nm, and a gate electrode 7 with the thickness of 145nm is arranged between the source electrode and the drain electrode to form the gallium nitride high electron mobility transistor.
A first metal interconnecting strip 13 with the thickness of 200-300nm is arranged between the drain electrode 12 of the silicon metal oxide semiconductor field effect transistor and the source electrode 6 of the gallium nitride high electron mobility transistor and is used for electrically connecting the two devices; a second metal interconnection strip 14 with the thickness of 200 and 300nm is arranged between the source electrode 9 of the silicon metal oxide semiconductor field effect transistor and the gate electrode 7 of the gallium nitride high electron mobility transistor and is used for electrically connecting the two devices, so that a silicon and gallium nitride heterogeneous integrated monolithic chip based on the bonding technology is formed.
Referring to fig. 3, the method for manufacturing a monolithic heterogeneous integrated Cascode gallium nitride high electron mobility transistor based on the smart cut technology according to the present invention provides the following three embodiments.
Example 1: preparing a monolithic heterogeneous integrated Cascode gallium nitride high electron mobility transistor with the thickness of a monocrystalline silicon thin film of 100 nm.
1.1) selecting an AlGaN/GaN/Substrate with the AlGaN barrier layer thickness of 20nm, the GaN buffer layer thickness of 1 μm and the Substrate thickness of 400 μm, as shown in (a) in FIG. 3;
1.2) adopting a wafer cleaning process, carrying out ultrasonic treatment on the AlGaN/GaN/Substrate for 5min by respectively using acetone, ethanol and deionized water in sequence, and then carrying out ultrasonic treatment on the Substrate in a piranha solution (H)2O2:H2SO41:3) for 5min, to obtain a highly clean AlGaN/GaN/Substrate, as shown in fig. 3 (b).
And 2, depositing silicon dioxide to form an isolation buffer layer.
And depositing silicon dioxide with the thickness of 1 μm on the cleaned AlGaN/GaN/Substrate by adopting a plasma chemical vapor deposition process to form an isolation buffer layer, as shown in (c) of FIG. 3.
And 3, densifying the silicon dioxide isolation buffer layer.
The sample on which the silica isolation buffer layer is grown is annealed in a nitrogen atmosphere at a temperature of 900 c for 30min using a high temperature annealing process to densify the silica, as shown in fig. 3 (d).
And 4, flattening the silicon dioxide isolation buffer layer.
The silicon dioxide isolation buffer layer is ground using a chemical mechanical polishing process to reduce its surface roughness to 0.3-0.4nm in preparation for successful bonding, as shown in fig. 3 (e).
And 5, cleaning the SOI substrate to obtain the highly-clean SOI substrate.
Cleaning SOI substrate with acetone, ethanol, and deionized water sequentially for 5min, and adding into piranha solution (H)2O2:H2SO4Soaking in 1:3) for 5min, and adding diluted hydrofluoric acid solution (HF: H)2O ═ 1:50) for 1min, to obtain a highly clean SOI substrate, as shown in fig. 3 (f).
And 6, bonding the SOI Substrate obtained in the step 5 with the AlGaN/GaN/Substrate with the flat silicon dioxide layer obtained in the step 4.
Bonding the SOI Substrate obtained in the step 5 with an AlGaN/GaN/Substrate by using a wafer bonding technique, and annealing at 900 ℃ for 1 hour in a nitrogen atmosphere to reinforce the bonding effect, as shown in (g) of FIG. 3.
And 7, removing the SOI substrate and the buried oxide layer in the bonded substrate obtained in the step 6.
And (3) removing the SOI substrate and the buried oxide layer in the bonded sample by adopting chemical mechanical polishing and wet etching processes, so that only the silicon thin film with the top layer thickness of 100nm is reserved on the SOI substrate part of the bonded sample, as shown in (h) in fig. 3.
And 8, etching to form the active region table top of the Si device.
Using a reactive ion etching process, the active region mesa of the Si device is etched on the sample obtained in step 7, as shown in (i) of fig. 3.
And 9, etching to form the active region table top of the GaN device.
And (3) etching the middle part of the sample obtained in the step (8) by adopting a reactive ion etching process to form an isolation groove, wherein the other side of the isolation groove is the table top of the active region of the gallium nitride device, as shown in (j) in fig. 3.
And step 10, performing ion implantation to form a source drain doped region of the silicon metal oxide semiconductor field effect transistor.
Implanting phosphorus ions on the mesa of the active region of the silicon device by ion implantation process, wherein the dose of the ion implantation is 1 × 1016cm-2And the implantation energy is 10keV, and source and drain doped regions of the silicon metal oxide semiconductor field effect transistor are formed, as shown in (k) of FIG. 3.
And 11, manufacturing a source and drain electrode of the gallium nitride high-mobility transistor device, and annealing to form ohmic contact and activate source and drain region doping of the silicon metal oxide semiconductor field effect transistor device.
11.1) Wet etching with NH4Removing silicon dioxide from a BOE buffer solution of HF (6: 1) at a position corresponding to the mesa of the active region of the gallium nitride device;
11.2) depositing Ti with the thickness of 22nm, Al with the thickness of 140nm, Ni with the thickness of 55nm and Au with the thickness of 45nm on the table top of the active area of the gallium nitride device in sequence by adopting an electron beam evaporation process to form a source drain electrode of the gallium nitride high mobility transistor, and then annealing for 30s in a nitrogen atmosphere with the temperature of 875 ℃ to ensure that the source drain electrode of the gallium nitride device is fused with AlGaN to form ohmic contact and activate source drain doping of the silicon device, as shown in (l) in figure 3.
And step 12, manufacturing a grid electrode of the gallium nitride high-mobility transistor device.
12.1) adopting a wet etching process and utilizing NH4Removing silicon dioxide from the BOE buffer solution with HF being 6:1 at the position corresponding to the mesa of the active region of the gallium nitride device of the sample obtained in the step 11;
12.2) adopting an electron beam evaporation process, and sequentially depositing Ni with the thickness of 45nm and Au with the thickness of 150nm on the table top of the active area of the gallium nitride device to form a gate electrode of the gallium nitride high-mobility transistor, as shown in (m) in figure 3.
And step 13, depositing a gate dielectric layer of the silicon metal oxide semiconductor field effect transistor device.
Depositing the sample obtained in the step 12 in a nitrogen atmosphere at 250 ℃ by adopting an atomic layer deposition process to obtain HfO with the thickness of 10nm2And (e) a gate dielectric layer, such as (n) in fig. 3.
And step 14, manufacturing a gate electrode of the silicon metal oxide semiconductor field effect transistor device.
HfO of the Si device active region mesa of the sample obtained in step 13 by electron beam evaporation2Ni with the thickness of 20nm and Au with the thickness of 120nm are sequentially deposited on the dielectric layer to form a gate electrode of the silicon metal oxide semiconductor field effect transistor, as shown in (o) of figure 3.
And step 15, manufacturing a source electrode and a drain electrode of the silicon metal oxide semiconductor field effect transistor device.
Etching out HfO at the position corresponding to the mesa of the active region of the silicon device in the sample obtained in step 14 by using a reactive ion etching process2The dielectric layer is then removed of HfO by electron beam evaporation2After depositing Ni with the thickness of 30nm, annealing for 30s in a nitrogen atmosphere with the temperature of 400 ℃ so that the source and drain electrodes of the silicon device form ohmic contact with the source and drain doped regions, as shown in (p) of fig. 3.
And step 16, opening a through hole to expose the gate source and drain electrodes of the gallium nitride high mobility transistor.
Removing HfO covered on the source and drain electrodes of the mesa gate in the active region of the GaN device in step 13 by adopting a reactive ion etching process2And (e) exposing the gate-source drain of the GaN HEMT to form a through hole, as shown in (q) of FIG. 3.
And step 17, manufacturing a metal interconnection strip between the silicon metal oxide semiconductor field effect transistor and the gallium nitride high mobility transistor.
And (3) depositing Ni with the thickness of 45nm and Au with the thickness of 200nm in sequence between the drain electrode of the Si metal oxide semiconductor field effect transistor and the source electrode of the GaN high electron mobility transistor and between the source electrode of the Si metal oxide semiconductor field effect transistor and the grid electrode of the GaN high electron mobility transistor respectively by adopting an electron beam evaporation process to form metal interconnection, and finishing the manufacture of the monolithic heterogeneous integrated Cascode gallium nitride high mobility transistor based on the bonding technology, wherein the process is shown as (r) in the figure 3.
Example 2: and preparing the monolithic heterogeneous integrated Cascode gallium nitride high-electron-mobility transistor with the monocrystalline silicon thin film thickness of 145 nm.
Cleaning the AlGaN/GaN/Substrate.
1a) Selecting an AlGaN/GaN/Substrate with the AlGaN barrier layer thickness of 30nm, the GaN buffer layer thickness of 1 μm and the Substrate thickness of 450 μm, as shown in (a) in FIG. 3;
1b) adopting a wafer cleaning process, carrying out ultrasonic treatment on the AlGaN/GaN/Substrate for 5min by respectively using acetone, ethanol and deionized water in sequence, and then carrying out ultrasonic treatment on the Substrate in a piranha solution (H)2O2:H2SO41:3) for 5min, to obtain a highly clean AlGaN/GaN/Substrate, as shown in fig. 3 (b).
And step two, depositing silicon dioxide to form an isolation buffer layer.
The specific implementation of this step is the same as step 2 of example 1, as in (c) of fig. 3.
And step three, densifying the silicon dioxide isolation buffer layer.
The specific implementation of this step is the same as step 3 of example 1, as shown in fig. 3 (d).
And step four, flattening the silicon dioxide isolation buffer layer.
The specific implementation of this step is the same as step 4 of example 1, as shown in fig. 3 (e).
And step five, cleaning the SOI substrate to obtain the highly-clean SOI substrate.
The specific implementation of this step is the same as step 5 of example 1, as shown in fig. 3 (f).
And step six, bonding the SOI Substrate obtained in the step five with the AlGaN/GaN/Substrate with the flat silicon dioxide layer obtained in the step four.
The specific implementation of this step is the same as step 6 of example 1, as shown in fig. 3 (g).
And step seven, removing the SOI substrate and the buried oxide layer in the bonded substrate obtained in the step six.
And (3) removing the SOI substrate and the buried oxide layer in the bonded sample by adopting chemical mechanical polishing and wet etching processes, so that only the silicon thin film with the top layer thickness of 145nm is reserved on the SOI substrate part of the bonded sample, as shown in (h) in fig. 3.
And step eight, etching to form the active region table top of the Si device.
The specific implementation of this step is the same as step 8 of example 1, as in (i) of fig. 3.
And step nine, etching to form the active region table top of the GaN device.
The specific implementation of this step is the same as step 9 of example 1, as shown in (j) of fig. 3.
And step ten, performing ion implantation to form a source drain doped region of the silicon metal oxide semiconductor field effect transistor.
The specific implementation of this step is the same as step 10 of example 1, as shown in fig. 3 (k).
And eleventh, manufacturing a source and drain electrode of the gallium nitride high-mobility transistor device, and annealing to form ohmic contact and activate source and drain region doping of the silicon metal oxide semiconductor field effect transistor device.
The specific implementation of this step is the same as step 11 of example 1, as shown in fig. 3 (l).
And step twelve, manufacturing a grid electrode of the gallium nitride high-mobility transistor device.
The specific implementation of this step is the same as step 12 of example 1, as shown in (m) of fig. 3.
And thirteen, depositing a gate dielectric layer of the silicon metal oxide semiconductor field effect transistor device.
The specific implementation of this step is the same as step 13 of example 1, as shown in fig. 3 (n).
And step fourteen, manufacturing a gate electrode of the silicon metal oxide semiconductor field effect transistor device.
Adopting an electron beam evaporation process to obtain HfO of the mesa of the active region of the silicon device of the sample obtained in the step thirteen2Ni with the thickness of 10nm and Au with the thickness of 100nm are sequentially deposited on the dielectric layer to form a gate electrode of the silicon metal oxide semiconductor field effect transistor, as shown in (o) of figure 3.
And fifthly, manufacturing a source electrode and a drain electrode of the silicon metal oxide semiconductor field effect transistor device.
Etching out HfO at the position corresponding to the mesa of the active region of the silicon device in the sample obtained in the step fourteen by adopting a reactive ion etching process2The dielectric layer is then removed of HfO by electron beam evaporation2Then annealing for 30s at 400 deg.c in nitrogen atmosphere to make the source and drain electrodes of the silicon device form ohmic contact with the source and drain doped regions, as shown in fig. 3 (p).
Sixthly, opening a through hole to expose the gate source and drain electrodes of the gallium nitride high mobility transistor.
The specific implementation of this step is the same as step 16 of example 1, as shown in fig. 3 (q).
Seventhly, manufacturing a metal interconnection strip between the silicon metal oxide semiconductor field effect transistor and the gallium nitride high mobility transistor.
And (3) depositing Ni with the thickness of 50nm and Au with the thickness of 210nm respectively between the drain electrode of the Si metal oxide semiconductor field effect transistor and the source electrode of the GaN high electron mobility transistor and between the source electrode of the Si metal oxide semiconductor field effect transistor and the grid electrode of the GaN high electron mobility transistor in sequence by adopting an electron beam evaporation process to form metal interconnection, and finishing the manufacture of the monolithic heterogeneous integrated Cascode gallium nitride high mobility transistor based on the bonding technology, wherein the process is shown as (r) in the figure 3.
Example 3: and preparing the monolithic heterogeneous integrated Cascode gallium nitride high-electron-mobility transistor with the monocrystalline silicon thin film thickness of 200 nm.
And step A, cleaning the AlGaN/GaN/Substrate.
Selecting an AlGaN/GaN/Substrate with the AlGaN barrier layer thickness of 40nm, the GaN buffer layer thickness of 2 μm and the Substrate thickness of 500 μm, as shown in (a) in FIG. 3;
adopting a wafer cleaning process, carrying out ultrasonic treatment on the AlGaN/GaN/Substrate for 5min by respectively using acetone, ethanol and deionized water in sequence, and then carrying out ultrasonic treatment on the Substrate in a piranha solution (H)2O2:H2SO41:3) for 5min, to obtain a highly clean AlGaN/GaN/Substrate, as shown in fig. 3 (b).
And step B, depositing silicon dioxide to form an isolation buffer layer.
The specific implementation of this step is the same as step 2 of example 1, as in (c) of fig. 3.
And step C, densifying the silicon dioxide isolation buffer layer.
The specific implementation of this step is the same as step 3 of example 1, as shown in fig. 3 (d).
And D, flattening the silicon dioxide isolation buffer layer.
The specific implementation of this step is the same as step 4 of example 1, as shown in fig. 3 (e).
And E, cleaning the SOI substrate to obtain the highly-clean SOI substrate.
The specific implementation of this step is the same as step 5 of example 1, as shown in fig. 3 (f).
And step F, bonding the SOI Substrate obtained in the step E with the AlGaN/GaN/Substrate with the flat silicon dioxide layer obtained in the step D.
The specific implementation of this step is the same as step 6 of example 1, as shown in fig. 3 (g).
And G, removing the SOI substrate and the buried oxide layer in the bonded substrate obtained in the step F.
And (3) removing the SOI substrate and the buried oxide layer in the bonded sample by adopting chemical mechanical polishing and wet etching processes, so that only the silicon thin film with the top layer thickness of 200nm is reserved on the SOI substrate part of the bonded sample, as shown in (h) in fig. 3.
And H, etching to form the active region table of the Si device.
The specific implementation of this step is the same as step 8 of example 1, as in (i) of fig. 3.
And step I, etching to form the active region table top of the GaN device.
The specific implementation of this step is the same as step 9 of example 1, as shown in (j) of fig. 3.
And step J, injecting ions to form a source drain doped region of the silicon metal oxide semiconductor field effect transistor.
The specific implementation of this step is the same as step 10 of example 1, as shown in fig. 3 (k).
And K, manufacturing a source drain electrode of the gallium nitride high-mobility transistor device, and annealing to form ohmic contact and activate source drain region doping of the silicon metal oxide semiconductor field effect transistor device.
The specific implementation of this step is the same as step 11 of example 1, as shown in fig. 3 (l).
And step L, manufacturing a grid electrode of the gallium nitride high-mobility transistor device.
The specific implementation of this step is the same as step 12 of example 1, as shown in (m) of fig. 3.
And step M, depositing a gate dielectric layer of the silicon metal oxide semiconductor field effect transistor device.
The specific implementation of this step is the same as step 13 of example 1, as shown in fig. 3 (n).
And step N, manufacturing a gate electrode of the silicon metal oxide semiconductor field effect transistor device.
Adopting an electron beam evaporation process to obtain HfO of the mesa of the active region of the silicon device of the sample obtained in the step M2Ni with the thickness of 15nm and Au with the thickness of 125nm are sequentially deposited on the dielectric layer to form a gate electrode of the silicon metal oxide semiconductor field effect transistor, as shown in (o) of figure 3.
And step O, manufacturing a source electrode and a drain electrode of the silicon metal oxide semiconductor field effect transistor device.
Etching out HfO at the position corresponding to the mesa of the active region of the silicon device in the sample obtained in the step fourteen by adopting a reactive ion etching process2The dielectric layer is then removed of HfO by electron beam evaporation2Is deposited with a thickness of 70nm of Ni, followed byAnnealing is carried out for 30s under the nitrogen atmosphere with the temperature of 400 ℃, so that the source and drain electrodes of the silicon device and the source and drain doped regions form ohmic contact, as shown in (p) of fig. 3.
And step P, opening a through hole to expose the gate source and drain electrodes of the gallium nitride high mobility transistor.
The specific implementation of this step is the same as step 16 of example 1, as shown in fig. 3 (q).
And step Q, manufacturing a metal interconnection strip between the silicon metal oxide semiconductor field effect transistor and the gallium nitride high mobility transistor.
And (3) depositing Ni with the thickness of 60nm and Au with the thickness of 220nm in sequence between the drain electrode of the Si metal oxide semiconductor field effect transistor and the source electrode of the GaN high electron mobility transistor and between the source electrode of the Si metal oxide semiconductor field effect transistor and the grid electrode of the GaN high electron mobility transistor respectively by adopting an electron beam evaporation process to form metal interconnection, and finishing the manufacture of the monolithic heterogeneous integrated Cascode gallium nitride high mobility transistor based on the bonding technology, wherein the process is shown as (r) in the figure 3.
The foregoing description is only three specific examples of the present invention and is not intended to limit the invention, so that it will be apparent to those skilled in the art that various changes and modifications in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (5)
1. A manufacturing method of a monolithic heterogeneous integrated Cascode gallium nitride high mobility transistor based on bonding is characterized by comprising the following steps:
1) adopting a wafer cleaning process, carrying out ultrasonic treatment on the AlGaN/GaN/Substrate for 5min by respectively using acetone, ethanol and deionized water in sequence, and then carrying out ultrasonic treatment on the Substrate in the piranha solution H2O2:H2SO4Soaking for 5min in a ratio of 1:3 to obtain a high-purity AlGaN/GaN/Substrate;
2) depositing silicon dioxide with the thickness of 1 mu m on a clean AlGaN/GaN/Substrate by adopting a plasma chemical vapor deposition process to form an isolation buffer layer;
3) annealing the sample on which the silicon dioxide isolation buffer layer grows by adopting a high-temperature annealing process so as to compact the silicon dioxide;
4) grinding the silicon dioxide isolation buffer layer by adopting a chemical mechanical polishing process to reduce the surface roughness to 0.3-0.4nm, and preparing for successful bonding;
5) cleaning SOI substrate with acetone, ethanol, and deionized water sequentially for 5min, and adding into piranha solution H2O2:H2SO4Soaking in 1:3 solution for 5min, and adding HF and H in dilute hydrofluoric acid solution2Soaking for 1min at a ratio of 1:50 to obtain a highly clean SOI substrate;
6) bonding the SOI Substrate obtained in the step 5) with an AlGaN/GaN/Substrate by adopting a wafer bonding technology, and then reinforcing the bonding effect by adopting a high-temperature annealing process;
7) removing the SOI substrate and the buried oxide layer in the bonded sample by adopting chemical mechanical polishing and wet etching processes, so that only the top silicon film is reserved on the SOI substrate part of the bonded sample;
8) etching the table top of the active area of the silicon device on the smooth silicon film of the sample obtained in the step 7) by adopting a reactive ion etching process; etching the middle part of the AlGaN/GaN/Substrate to form an isolation groove, wherein the other side of the isolation groove is the table top of the active region of the gallium nitride device;
9) injecting phosphorus ions on the table top of the active region of the silicon device by adopting an ion injection process to form a source drain doped region of the silicon metal oxide semiconductor field effect transistor;
10) adopting a wet etching process, removing silicon dioxide at a corresponding position of a table top of an active area of a gallium nitride device by using a BOE buffer solution, and then adopting an electron beam evaporation process to sequentially deposit 22nm of Ti, 140nm of Al, 55nm of Ni and 45nm of Au on the table top of the active area of the gallium nitride device to form a source electrode and a drain electrode of the gallium nitride high electron mobility transistor;
11) adopting an annealing process to fuse a source drain electrode of the gallium nitride device with AlGaN to form ohmic contact and activate source drain doping of the silicon device;
12) removing silicon dioxide at the corresponding position of the table top of the active area of the gallium nitride device in the sample obtained in the step 11) by using a BOE buffer solution by adopting a wet etching process, and then sequentially depositing Ni and Au on the table top of the active area of the gallium nitride device by adopting an electron beam evaporation process, wherein the thicknesses of the Ni and the Au are 45nm and 150nm respectively to form a gate electrode of the GaN high electron mobility transistor;
13) depositing HfO with a thickness of 10nm on the sample obtained in step 12) by using an atomic layer deposition process2A dielectric layer;
14) adopting an electron beam evaporation process to obtain HfO of the mesa of the active region of the silicon device in the sample obtained in the step 13)2Sequentially depositing Ni and Au on the dielectric layer, wherein the thicknesses of the Ni and the Au are respectively 20nm and 120nm, and forming a gate electrode of the Si metal oxide semiconductor field effect transistor;
15) removing HfO at the corresponding position of the mesa of the active region of the silicon device in the sample obtained in step 14) by adopting a reactive ion etching process2The dielectric layer is then removed of HfO by electron beam evaporation2Depositing Ni with the thickness of 30nm at the position of the silicon device, and annealing to form ohmic contact between a source drain electrode and a source drain doped region of the silicon device;
16) adopting a reactive ion etching process to cover HfO on the source and drain electrodes of the mesa gate of the active region of the gallium nitride device in the step 13)2Removing the dielectric layer to expose the grid source drain of the GaN high electron mobility transistor;
17) and (3) depositing Ni with the thickness of 45nm and Au with the thickness of 200nm respectively between the drain electrode of the Si metal oxide semiconductor field effect transistor and the source electrode of the GaN high electron mobility transistor and between the source electrode of the Si metal oxide semiconductor field effect transistor and the grid electrode of the GaN high electron mobility transistor in sequence by adopting an electron beam evaporation process to form metal interconnection, thereby finishing the manufacture of the monolithic heterogeneous integrated Cascode gallium nitride high electron mobility transistor based on the bonding technology.
2. The method of claim 1, wherein:
the annealing process conditions in the step 3) are as follows: annealing at 900 deg.C under nitrogen atmosphere for 30 min;
the annealing process conditions in the 6) are as follows: annealing for 1h in a nitrogen atmosphere at the temperature of 900 ℃;
the annealing process condition in 11) is annealing for 30s in a nitrogen atmosphere at the temperature of 875 ℃;
the condition of the annealing process in the 15) is annealing for 30s in a nitrogen atmosphere at the temperature of 400 ℃.
3. The method of claim 1, wherein: the process condition of the deposition in the step 13) is deposition for 15min in a nitrogen atmosphere with the temperature of 250 ℃.
4. The method of claim 1, wherein: the dose of the ion implantation in the step 9) is 1 × 1016cm-2The implantation energy is 10 keV.
5. The method of claim 1, wherein the BOE solutions of 10) and 12) are prepared from NH4The mixed solution of the F solution and the HF solution is prepared according to the ratio of 6:1, and the matching process is as follows:
first, 34.29g of NH were weighed4F solid and 85.71ml deionized water were mixed to 40% NH4F solution;
then, 20ml of 40% HF solution was taken and NH was added4The solution F and the solution HF were mixed thoroughly to prepare a total of 140ml of BOE solution.
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