CN110610009B - SRAM circuit yield analysis method based on Bayesian model - Google Patents

Abstract

The invention belongs to the technical field of integrated circuits, and relates to a yield analysis method of a static random access memory circuit in the manufacturability design of an integrated circuit, wherein in the method, mutual information and sequence quadratic programming are firstly used for reducing the dimension of a disturbance space of a high-dimensional SRAM circuit, so that the quick calculation of the optimal translation vector of the high-dimensional SRAM circuit is realized; then establishing a Bayesian model of low-dimensional and high-dimensional SRAM circuit performance distribution; and finally, fitting of performance distribution of the high-dimensional SRAM circuit can be greatly accelerated by using priori knowledge of the low-dimensional SRAM circuit, the simulation times of the high-dimensional SRAM circuit are greatly reduced, and the failure rate of the SRAM meeting the precision requirement is obtained. Experimental results show that the method provided by the invention is obviously superior to the best method known internationally at present, and can realize the acceleration ratio of 6-7 times.

Description

SRAM circuit yield analysis method based on Bayesian model

Technical Field

The invention belongs to the technical field of integrated circuits, relates to a Static Random Access Memory (SRAM) yield analysis method in the manufacturability design of integrated circuits, in particular to an SRAM circuit yield analysis method based on a Bayesian model, and the method firstly uses Mutual Information (MI) and Sequence Quadratic Programming (SQP) method to quickly calculate the Optimal Shift Vector (OSV); then establishing a Bayesian model between the performance distributions of the low-dimensional SRAM circuit and the high-dimensional SRAM circuit; and finally, the low-dimensional SRAM circuit is used as priori knowledge, so that the fitting of the performance distribution of the high-dimensional SRAM circuit can be greatly accelerated, the simulation times of the high-dimensional SRAM circuit are greatly reduced, and the failure rate of the high-dimensional SRAM circuit meeting the precision requirement is obtained.

Background

The prior art discloses that as the size of semiconductor fabrication processes continues to shrink, process perturbations have an increasingly significant impact on the performance and reliability of SRAM circuits. To reduce chip area, SRAM cells are typically designed with minimum process dimensions, which makes SRAM performance very vulnerable to process variationsThe influence of motion; meanwhile, a large number of repeated SRAM cells are included in one SRAM circuit, and in order to ensure the yield of the whole SRAM circuit, the failure rate of each SRAM cell must be extremely low (generally less than 10) ^-6 )。

Generally, a Monte Carlo (MC) method is a simple and effective yield estimation method, but because the failure rate of an SRAM circuit is extremely low, which belongs to extreme event simulation, the MC method directly adopted usually requires thousands of sampling times to obtain accurate failure rate, each sampling point calls a circuit simulation tool, and the operation of the circuit simulation tool is extremely time-consuming for a large scale of SRAM circuits.

Therefore, how to quickly and accurately calculate the failure rate of the SRAM circuit or the SRAM cell is a very challenging problem in the field; the difficulty lies in two aspects: first, efficient high-dimensional SRAM circuit failure rate analysis [4]],[11]-[12]Efforts are made to solve this problem; secondly, the single simulation running time of the large-scale circuit is long; for an SRAM array comprising 80 core cells, a single circuit simulation takes two hours, and experiments show that the time complexity of the SRAM array circuit simulation is approximately O (n) ³ ) Where n is the number of SRAM core cells, therefore, as the circuit scale increases, the simulation time increases dramatically.

For SRAM yield estimation, the current main analysis methods can be roughly divided into three categories: importance Sampling based methods (import Sampling, IS) [1-6], dead Boundary search methods (Boundary Searching) [8-9], and progressive methods [10-12].

The importance sampling method obtains the actual distribution by shifting the original distribution, and this shift vector is called the optimal shift vector. Compared with original distribution, sampling on actual distribution can enable most sample points to fall near a failure boundary, the probability of obtaining failure points is greatly improved, and sampling efficiency is improved.

Recently, importance Boundary Sampling (IBS) [6] is proposed by combining the advantages of Importance Sampling and Boundary search methods, which establishes a surrogate model for the failing Boundary, and can greatly improve the efficiency of Importance Sampling, but in high dimensions, the surrogate model is difficult to obtain, so the method is still only suitable for low dimensions. Multiple Failure Region Importance Sampling (MFRIS) document [4] generalizes Importance Sampling to high-dimensional and Multiple failure regions, the main idea being to use Sequential Quadratic Programming (SQP) to quickly find the OSV and then sample in the vicinity of the OSV.

The failure boundary search method attempts to describe the boundaries of failure regions in parameter space and then directly integrates the failure rates for the failure regions [8-9]. The main disadvantage of this method is that the boundary description of the high-dimensional space is difficult, and therefore this method usually requires that the dimension of the process parameters does not exceed 100[ 2], [18].

The progressive approach calculates the failure rate of extreme events by breaking the SRAM circuit failure into a series of sub-events that are easier to solve. Subset Simulation (SUS) [10] is dedicated to analyzing large scale SRAM circuits and calculates failure rate by equivalently decomposing the circuit failure probability into a series of products of conditional probabilities, but SUS relies on Markov Monte Carlo and requires a large number of sample points to achieve a relatively high accuracy. Asymptotic Probability Approximation (APA) [11] and Asymptotic Probability Estimation (APE) [12] attempt to solve the problem of correlation of process parameters in high-dimensional SRAM circuits, and the APE decomposes the high-dimensional SRAM circuit failure rate analysis problem into a series of low-dimensional core cell level failure rate problems under fixed conditions, however, under such decomposition, circuit simulation is still performed under high dimensions, requiring a large amount of operating time.

In view of the above-mentioned shortcomings, the inventors of the present application propose to provide a method for analyzing the yield of SRAM circuits based on a bayesian model. The method can accelerate the fitting of the performance distribution of the high-dimensional SRAM circuit, greatly reduce the simulation times of the high-dimensional SRAM circuit and obtain the failure rate of the high-dimensional SRAM circuit which meets the precision requirement.

The prior art related to the present invention is:

[1]Rouwaida Kanj,Rajiv Joshi,and Sani Nassif,“Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events,”DAC,Jul.2006

[2]Lara Dolecek,Masood Qazi,Devavrat Shah,and Anantha Chandrakasan,“Breaking the simulation barrier:SRAM evaluation through norm minimization,”ICCAD,2008

[3]Qazi,Masood,Tikekar,Mehul,Dolecek,Lara,Shah,Devavrat,Chandrakasan,and Anantha,“Loop flattening&spherical sampling:highly efficient model reduction techniques for SRAM yield analysis,”DATE,2010,pp.801–806.

[4]Mengshuo Wang,Changhao Yan,Xin Li,Dian Zhou,and Xuan Zeng.“High-Dimensional and Multiple-Failure-Region Importance Sampling for SRAM Yield Analysis,”IEEE Trans.on VLSI,vol.25,no.3,pp.806–819,2017.

[5]C.Dong and X.Li,“Efficient SRAM failure rate prediction via Gibbs sampling,”DAC,2011,pp.200–205.

[6]Jian Yao,Zuochang Ye,and Yan Wang,“Importance Boundary Sampling for SRAM Yield Analysis With Multiple Failure Regions,”IEEE Trans.on CAD,vol.31,no.12,pp.1831–1844,2011

[7]Solido Design Automation Inc.,“High-Sigma Monte Carlo for High Yield and Performance Memory Design”Solido White Paper,2011

[8]Zhenyu Wu,Changhao Yan,Xuan Zeng,and Sheng Guo Wang.“Rapid estimation of the probability of SRAM failure via adaptive multi-level sliding-window statistical method,”Integration the VLSI Journal,vol.50,pp.1–15,2015.

[9]Shweta Srivastava and Jaijeet Roychowdhury,“Rapid Estimation of the Probability of SRAM Failure due to MOS threshold Variations,”IEEE Custom Integrated Circuits Conference.229–232,2007

[10]S.Sun and X.Li,“Fast statistical analysis of rare circuit failure events via subset simulation in high-dimensional variation space,”ICCAD,Nov.2014

[11]H.Yu,Jun Tao,Changhai Liao,et al.,“Efficient Statistical Analysis for Correlated Rare Failure Events via Asymptotic Probability Approximation,”ICCAD,Nov.2016.

[12]Tao,Jun,Handi Yu,et al."Correlated Rare Failure Analysis via Asymptotic Probability Evaluation."DAC 2017:1-6.

[13]X.Li,Wangyang Zhang,Fa Wang et al.,“Efficient parametric yield estimation of analog/mixed-signal circuits via Bayesian model fusion,”ICCAD,pp.627-634,2012.

[14]D.Ormoneit and V.Tresp,“Averaging,maximum penalized likelihood and Bayesian estimation for improving Gaussian mixture probability density estimates,”IEEE Trans.Neural Netw.,vol.9,no.4,pp.639–650,Jul.1998.

[15]S.Kucherenko and Y.Sytsko,“Application of deterministic lowdiscrepancy sequences in global optimization,”Comput.Optim.Appl.,vol.30,no.3,pp.297–318,2005.

[16]Ross,Brian C."Mutual Information between Discrete and Continuous Data Sets."Plos One 9.2(2014):e87357.

[17]J.M.Bernardo and A.F.M.Smith,Bayesian Theory.NewYork:Wiley,1994.

[18]Fang Gong,Yiyu Shi,Hao Yu,and Lei He,Parametric yield estimation for SRAM cells:Concepts,algorithms and challenges.In Design Automation Conference,Knowledge Center Article,2010.

[19]Ross,Brian C."Mutual Information between Discrete and Continuous Data Sets."Plos One 9.2(2014):e87357.。

disclosure of Invention

The invention aims to provide a Bayesian model-based SRAM circuit yield analysis method aiming at the defects in the prior art. The method is a rapid SRAM circuit yield estimation method under the consideration of process disturbance. In the method, firstly, mutual information and sequence quadratic programming are used for quickly calculating the optimal translation vector; then, establishing a Bayesian model between the performance distributions of the low-dimensional SRAM circuit and the high-dimensional SRAM circuit; and finally, using the priori knowledge of the low-dimensional SRAM circuit to accelerate the fitting of the performance distribution of the high-dimensional SRAM circuit, greatly reducing the simulation times of the high-dimensional SRAM circuit and obtaining the failure rate of the high-dimensional SRAM circuit which meets the precision requirement.

In particular, in the present invention,

firstly, in order to search OSV quickly, the dimension reduction is carried out on a high-dimensional SRAM circuit by adopting a Mutual Information (MI) 16 method, because of the special circuit structure of the SRAM, the high-dimensional gradient vector of the SRAM is usually sparse, namely, the performance is not obvious to the change of a large number of disturbance parameters, and the simulation times of the circuit can be greatly reduced by searching the OSV in the disturbance parameter space after dimension reduction by using an SQP method;

secondly, in order to improve the universality of the algorithm, a Gaussian mixture model is adopted to fit a probability density function of the performance, and meanwhile, in order to ensure that parameters of posterior distribution have an analytic solution, the conjugate prior distribution of mixed Gaussian is used as prior distribution;

finally, in order to reduce the simulation times of the high-dimensional SRAM circuit, based on the special structure of the SRAM circuit, the characteristic that the performance distribution of the high-dimensional SRAM and the performance distribution of the low-dimensional SRAM have similarity is assumed, based on the priori knowledge, the invention uses more sample points of the low-dimensional SRAM circuit to calculate the hyperparameter of conjugate prior distribution, and then uses an expectation maximization algorithm to calculate the Gaussian mixture model parameters, so that the simulation times of the high-dimensional SRAM circuit can be greatly reduced.

The flow chart of the method for rapidly estimating the yield of the SRAM circuit under the consideration of the process disturbance, which is provided by the invention, is shown in FIG. 1 and comprises the following steps:

inputting parameters:

SRAM circuit netlist, circuit simulator SPICE;

2. a probability density distribution function of the perturbed process parameter;

3. failure threshold spec for each performance parameter _j J =1, …, p, where p is the number of performance parameters of interest, and assume performance index y for the j-th _j If the simulation result y _j ≤spec _j The circuit is considered to be failed;

and outputting a result:

failure rate of SRAM circuits.

More specifically, the SRAM circuit yield analysis method based on the Bayesian model comprises the following steps:

step 1: compressing the search space of the optimal translation vector by calculating mutual information between the performance index and the process parameter, and then calculating to obtain the optimal translation vector of the high-dimensional SRAM circuit by using a sequence quadratic programming method;

step 2: calculating a hyper-parameter of conjugate prior distribution by using the low-dimensional SRAM circuit performance value;

and step 3: calculating Gaussian mixture model parameters of performance distribution of the high-dimensional SRAM circuit by using an expectation maximization algorithm;

and 4, step 4: and calculating the failure rate of the high-dimensional SRAM circuit according to the Gaussian mixture model parameters of the performance distribution of the high-dimensional SRAM circuit.

In step 1 of the invention, the optimal translation vector of the high-dimensional SRAM circuit is calculated through mutual information and sequence quadratic programming, which comprises the following steps:

step 1.1: in a parameter space, sampling is carried out in a high-dimensional disturbance parameter space by adopting Gaussian distribution of 8 sigma standard deviation, wherein sigma is the standard deviation of a given disturbance process parameter, the probability density distribution function of the disturbance process parameter is generally Gaussian distribution N (0, sigma), and after sampling is carried out by adopting the Gaussian distribution of N (0,8 sigma), the failure point of the high-dimensional SRAM circuit is more easily obtained;

step 1.2: circuit simulation shows that the performance values yj, j =1 and …, p of the sample points are obtained.

Step 1.3: calculating mutual information of each process parameter variable and performance by using a K-Nearest neighbors (K-Nearest neighbors);

for an SRAM array, only one unit is selected at the same time, so that not all circuit disturbance parameters are closely related to the circuit performance, and the invention preferably adopts a mutual information concept to reduce the dimension of the circuit disturbance parameter space;

mutual information is also called transfer information, and is used for measuring the interdependence between two variables, the mutual information is a non-negative number, when the value is zero, the two variables are mutually independent, the larger the value is, the stronger the interdependence is, the mutual information of two discrete random variables X and Y is defined as

Wherein p (x, y) is a joint distribution, p (x), p (y) are boundary distributions,

however, since the joint distribution p (X, Y) of the random variables X and Y is unknown, mutual information cannot be obtained directly by definition simply, the invention uses a k-neighborhood algorithm in a more mature open source library scimit-left to calculate the mutual information [19];

step 1.4: selecting D' variables with the maximum mutual information value, so that the sum of the mutual information of the variables accounts for more than 95% of the total mutual information;

step 1.5: in the D' space after the dimension reduction, calculating an optimal translation vector by using sequence quadratic programming;

the invention utilizes sequential quadratic programming to calculate the optimal translation vector. Calculating the optimal translation vector can be equivalent to solving the following optimization problem:

min||v||

s.t.y _j (v)≤spec _j ,j＝1,2,...,p (2)

wherein | · | | is the L2 norm of the vector, yj (v) is the jth performance index obtained through circuit simulation, yj is the given jth performance failure threshold;

obtaining an optimal solution v through solving the optimization problem, namely obtaining an optimal translation vector of the high-dimensional SRAM circuit;

in step 2 of the present invention, the method for calculating the hyperparameter of conjugate prior distribution by using the performance value of the low-dimensional SRAM circuit comprises the following steps:

step 2.1: a low-dimensional SRAM circuit comprising only 1 memory cell and 1 sense amplifier is constructed by removing most of the memory cells in the high-dimensional SRAM circuit, using N (mu = OSV) _L σ) gaussian distribution, sampled in the parameter space of the low-dimensional SRAM circuit, where the gaussian distribution mean μ = OSV _L OSVL is highOnly keeping the low-dimensional optimal translation vector of the remaining dimension after dimension reduction by a dimension reduction method in the optimal translation vector v of the dimension SRAM circuit; sigma is the standard deviation of the given disturbance process parameter;

step 2.2: obtaining performance values yj of the sampling sample points through circuit simulation;

step 2.3: fitting performance distribution parameters of the low-dimensional SRAM circuit through a maximum likelihood method and an expectation maximization algorithm;

fitting the distribution of the jth performance indicator yj of the SRAM circuit using a hybrid Gaussian model, i.e.

Wherein the content of the first and second substances,

and κ _i >0，N(y _j ；μ _i ,σ _i ) Is a mean value of μ _i Standard deviation of σ _i (ii) a gaussian distribution of;

the Gaussian mixture model can fit most of continuous distribution, and the sampling data { yjk; k =1,2, …, m' }, the log-likelihood function from which the maximum likelihood method can be derived is

Parameter κ in the above formula _i,L ,μ _i,L ,σ _i,L The method can be obtained by calculation of an expectation-maximization algorithm, wherein the expectation-maximization algorithm comprises two steps, namely an expectation step and a maximization step;

in the expectation step, it can be determined that yjk belongs to different Gaussian distributions N (y) according to the current parameter values _j ；μ _i,L ,σ _i,L ) A posteriori probability of

In the maximization step, the parameter values are updated,

repeating the expectation step and the maximization step until the parameters are converged to obtain the distribution parameter k _i,L ,μ _i,L ,σ _i,L ,i＝1..n；

Step 2.4: selecting proper prior distribution, namely selecting mixed Gaussian distribution as a likelihood function, and selecting conjugate prior of the mixed Gaussian distribution as prior distribution;

an SRAM array usually consists of a plurality of SRAM memory CELLs (bit CELLs), as shown in fig. 2, for example, to read Cell <1>, bit lines need to be precharged, word lines are charged, then Cell <1> is selected, and is connected with the bit lines through M3 and M6, if the voltage difference between the bit lines is always smaller than the input threshold of the phase amplifier within a certain time delay, the reading fails;

for an SRAM array containing N cells as in FIG. 2, the present invention attempts to find a priori knowledge about performance in SRAM arrays of different cell numbers;

FIG. 3 shows that the performance at the optimum translation vector and TT angle varies relatively smoothly with increasing number of cells, i.e., the circuit performance at OSV can be seen as a function of the smooth variation with the number of cells, which indicates that performance values of a low-dimensional (few bit cell) SRAM array can be used, and information about a high-dimensional (many bit cell) SRAM array can be deduced;

if the circuit performance is directly modeled, the circuit model needs to contain all process parameters, and for a large-scale circuit, modeling in a high-dimensional parameter space is difficult to realize, relatively speaking, one-dimensional performance distribution is mapping obtained by circuit simulation of the high-dimensional parameter space, and modeling of the circuit performance distribution can greatly reduce the difficulty of modeling;

the performance distribution of the high-dimensional SRAM circuit is similar to but not completely identical to the performance distribution of the low-dimensional SRAM circuit, so that an accurate performance distribution model of the high-dimensional SRAM circuit can be obtained by a small number of sample points of the high-dimensional SRAM circuit and the combination of the prior knowledge of the existing low-dimensional SRAM circuit;

in Bayes theory, if the posterior probability and the prior probability p (theta) of a random variable theta belong to the same distribution family, then p (x; theta) and p (theta) are conjugate distribution, and p (theta) can be called conjugate prior of a likelihood function p (x; theta);

the conjugate prior distribution of the Gaussian mixture distribution is

Wherein D (kappa; gamma) is Dirichlet Distribution, N (mu i; nui, eta i-1 sigma i) is Gaussian Distribution, W (sigma i-1; alpha i, beta i) is Wishart Distribution;

step 2.5: calculating the hyperparameters of the performance distribution of the high-dimensional SRAM circuit by using the sample points of the low-dimensional SRAM circuit and adopting a maximum likelihood method;

if there is a sample point set { yjk; k =1,2, …, m' }, using yj (i) to label the subset of the mixture gaussian sampling from the ith gaussian distribution, the hyperparameter can be calculated by maximum likelihood, i.e.:

γ _i ＝m _i +1,

η _i ＝m _i ,

i＝1,2,...,n (10)

where mi = | yj (i) | is the number of sample points in the yj (i) set, and var and mean are the variance and mean, respectively;

however, because the simulation of the high-dimensional SRAM circuit takes a long time, it is usually impossible to directly obtain enough sample values of the performance of the high-dimensional SRAM circuit, and if the performance distributions of the low-dimensional SRAM circuit and the high-dimensional SRAM circuit are assumed to be similar, the hyper-parameters can be calculated by enough low-dimensional sample points, and then the hyper-parameters are appropriately modified to be suitable for the high-dimensional SRAM circuit, that is, the hyper-parameter of the performance distribution of the high-dimensional SRAM circuit is

γ _i ＝m _i +1

η _i ＝m _i ,

ν _i ＝μ _i,L +y _j,H (OSV _H )-y _j,L (OSV _L )

i＝1,...,n, (11)

Where mi = kappa i, lm', y _j,H (. And y) _j,L (. Cndot.) shows the performance of the high-dimensional SRAM circuit and the low-dimensional SRAM circuit, respectively, OSVH is the OSV calculated in the high-dimensional SRAM circuit, i.e. v, OSVL is the OSV of the high-dimensional OSVH only preserving the residual dimension after dimension reduction by dimension reduction method, k _i,L ,μ _i,L ,σ _i,L Is calculated in step 2.3Performance distribution parameters of the low-dimensional SRAM circuit;

in step 3 of the invention, calculating Gaussian mixture model parameters of performance distribution of the high-dimensional SRAM circuit by an expectation maximization method;

the invention uses the maximum a posteriori to calculate the parameters, and the logarithm maximum a posteriori is

Where m is the number of high-dimensional sample points,

since a suitable conjugate prior distribution is chosen, the parameters can still be calculated using the expectation-maximization algorithm,

the expected steps are as follows:

the maximization step is as follows:

and similarly, continuously circulating the expectation step and the maximization step until the parameters are converged to obtain the performance distribution parameter kappa of the high-dimensional SRAM circuit _i,H ,μ _i,H ,σ _i,H ,i＝1..n；

In step 4 of the invention, the failure boundary of the high-dimensional SRAM circuit is approximated by the regression hyperplane, the failure rate calculation of the high-dimensional SRAM circuit is realized by an analytical formula,

after the mixed gaussian distribution parameters of the high-dimensional SRAM circuit are obtained by using the maximum posterior calculation, the performance distribution of the high-dimensional SRAM circuit at the optimal translation vector point can be obtained, but the performance distribution at the origin point cannot be directly obtained, fig. 4 shows the difference between the two distributions, and the "failure rate" can be directly calculated by knowing the performance cumulative distribution function and the failure threshold value near the optimal translation vector, but the "failure rate" at this time is equal to the purple region in fig. 4, that is, the gaussian distribution taking the optimal translation vector as the mean value is taken as the integral of the weight, and the true failure rate should be taken as the gaussian distribution taking the origin point as the mean value as the weight;

in the invention, a regression hyperplane is adopted to approximate a failure boundary in a high dimension, the hyperplane is perpendicular to an optimal translation vector, when the Gaussian distribution taking the optimal translation vector as a mean value is subjected to integration, the obtained integral values are consistent no matter a failure area (pink area in a figure) obtained by hyperplane approximation is taken as an integral area or an actual failure area is taken as an integral area, therefore, the bias of the hyperplane is that

Wherein the content of the first and second substances,

the failure rate of the Gaussian distribution which takes the optimal translation vector as the mean value, namely N (v, 1), the norm cdf is the cumulative distribution function of the standard Gaussian distribution, and the norm v is the inverse function of the cumulative distribution function of the standard Gaussian distribution;

after obtaining the regression hyperplane, the failure rate of the final high-dimensional SRAM circuit can be obtained by adopting the following analytic formula

P _fail ＝1-normcdf(||OSV||+offset) (17)

The invention has the advantages that: (1) The circuit performance distribution is directly modeled, and is one-dimensional mapping obtained by circuit simulation in an original high-dimensional parameter space, so that the modeling complexity is obviously reduced, and the difficulty of directly modeling the circuit performance in the high-dimensional parameter space is avoided; (2) According to the invention, the simulation times of the high-dimensional SRAM are reduced by using the Bayesian model through the low-dimensional SRAM simulation, so that the running time of the yield analysis of the high-dimensional SRAM circuit can be greatly reduced; (3) With the increase of the dimensionality of the parameter space of the high-dimensional SRAM circuit, the sampling number of the algorithm on the high-dimensional SRAM circuit is almost constant, and the yield analysis of the large-scale SRAM circuit can be greatly accelerated.

The invention has the advantages that:

1. the invention applies a mutual information method in informatics to reduce the dimension of the perturbation process parameter space in the high-dimensional SRAM circuit, thereby realizing the rapid calculation of the optimal translation vector;

2. the invention is based on the Bayesian model, and quickly establishes the mixed Gaussian model of the high-dimensional SRAM circuit by means of the prior knowledge in the low-dimensional SRAM circuit, thereby obviously reducing the simulation times of the high-dimensional SRAM circuit and reducing the program operation time.

3. The simulation times of the high-dimensional SRAM circuit required by the invention are approximately constant and do not obviously rise along with the rise of the dimension, so that the method is suitable for the yield analysis of the large-scale SRAM circuit.

Drawings

FIG. 1 is a flow chart of the method of the present invention.

FIG. 2 is an SRAM array consisting of a number of SRAM cells and a phase amplifier.

FIG. 3 is a graph of the relationship between performance and the number of memory cells.

FIG. 4 is a two-dimensional schematic of an OSV and a failure zone.

FIG. 5 is a graph of the variation of simulation times with the number of cells in an SRAM array.

Detailed Description

The method of the present invention will now be described by way of specific example implementations.

In order to verify the precision and efficiency of the method, the method is verified through two test cases of read operation failure and write operation failure of an SRAM array, all the test cases use a 28nm CMOS process library, circuit simulation is carried out by adopting an HSPICE tool, although SUS can handle high-dimensional conditions, more than 106 sample points are usually needed, and the method is difficult to bear for simulation of large-scale circuits; the accurate value of the failure rate is obtained on the basis of enough sample points through the most direct MNIS method, the optimal translation vector is obtained through calculation of the MFRIS method, the minimum Norm Importance Sampling (Min-Norm Import Sampling, MNIS) is an early Importance Sampling method, and the original Sampling distribution is moved to the failure point with the minimum two norms for Sampling, so in the experiment of the application, three methods, namely the MNIS, the MFRIS and the invention are compared, and all failure rate calculation methods have randomness, and all algorithms participating in comparison run 10 averaging and standard deviation.

EXAMPLES example 1

As shown in fig. 2, the read operation firstly needs to precharge the bit line and the word respectively, CELL <1> is selected and connected with the bit line through M3 and M6, if the voltage difference between the bit lines is always smaller than the input threshold of the phase amplifier within a certain time delay, the read fails; in order to maximize the influence of the leakage current, 0 is stored in CELL <1>, and 1[4 are stored in the remaining CELLs.

TABLE 1 comparison of the read failure results for 32bit Cell SRAM arrays

Table 1 compares the results of MNIS, MFRIS and the calculation of the failure rate of the 32bit SRAM array according to the present invention, and with the threshold voltage Vth of the transistors of the SRAM cell and the phase amplifier as a process parameter, for a 6-transistor memory cell (bit cell), 32 memory cells have 32 × 6 random variables in total, and in addition, the sense amplifier has 5 random variables, so 197 (32 × 6+5) random variables in total are present.

The MFRIS can accurately calculate the failure rate of the high-dimensional SRAM, 1327 times of high-dimensional SRAM circuit simulation is called altogether, and the time is required to be 87.1 hours on a single-core CPU. The invention needs to perform circuit simulation on a 1bit SRAM array (1 multiplied by 6+5= 11D) and a 32bit SRAM array (197D), wherein, the super parameter for determining conjugate prior distribution needs 1000 times of low-dimensional SRAM circuit simulation, the running time is 732 seconds, and compared with the high-dimensional SRAM circuit simulation, the time can be ignored; the dimensionality reduction and OSV search requires 121 times of high-dimensional SRAM circuit simulation; the MAP parameter calculation needs 100 times of high-dimensional SRAM circuit simulation, and the total number of the high-dimensional SRAM circuit simulation needs 221 times; as shown in Table 1, the acceleration ratio of the present invention is about 5.9 times compared to the best MFRIS method at present, with roughly comparable accuracy.

Experiments further verified the invention in a higher dimensional SRAM array, on an 80bit Cell SRAM array, the random variable dimension of the 80bit Cell SRAM array was 485 (80 × 6+5) dimensions, as shown in table 2, the speed up ratio of the invention is about 7.7 times compared to the best MFRIS method at present, at roughly equivalent precision.

TABLE 2 SRAM array read failure results comparison for 80bit cells

EXAMPLES example 2

As shown in FIG. 2, CELL<1>The initial value is 1 and a write of 0 is attempted. It is first necessary to set the bit line voltage, i.e. BL low,

high and then sets the word line WL high. In CELL<1>Write voltage V of _write As a property, if over a period of time, V _write Above the threshold, the circuit fails.

As shown in Table 3, compared with the MFRIS method, the acceleration ratio of the invention is 6.9 times, although the precision of the failure rate is slightly reduced, the invention can obtain 7.35% precision which meets the requirements of most practical engineering applications.

TABLE 3 comparison of write failure results for 80bit SRAM arrays

EXAMPLES example 3

The example further verifies that the relationship between the simulation times of the high-dimensional SRAM circuit and the number of bit Cell units in the SRAM array is gradually increased from the SRAM array with only 1bit Cell to the SRAM array with 80bit cells.

FIG. 4 shows the variation of simulation times of a high-dimensional SRAM circuit with the number of cells in an SRAM array; the result shows that the simulation times and the dimensionality of the MFRIS are approximately linear, and the simulation times of the invention are almost constant; the invention has obvious advantages for the failure rate calculation of the high-dimensional SRAM circuit because the number of bit Cell units contained in the real SRAM chip is extremely large.

Claims (5)

1. A SRAM circuit yield analysis method based on a Bayesian model is characterized in that: firstly, rapidly calculating an optimal translation vector by using mutual information and sequence quadratic programming; then, establishing a Bayesian model between the performance distributions of the low-dimensional SRAM circuit and the high-dimensional SRAM circuit; finally, the low-dimensional SRAM circuit is used as priori knowledge, the fitting of the performance distribution of the high-dimensional SRAM circuit is accelerated, the simulation times of the high-dimensional SRAM circuit are reduced, and the failure rate of the SRAM meeting the precision requirement is obtained;

the method comprises the following steps:

inputting parameters:

1.SRAM circuit netlist, circuit simulator SPICE;

2. perturbing a probability density distribution function of the process parameter;

3. failure threshold spec per performance parameter _j J =1, …, p, where p is the number of performance parameters of interest, and assume for the j-th performance index y _j If the simulation result y _j ≤spec _j The circuit is considered to be failed;

and outputting a result:

failure rate of the SRAM circuit;

comprises the following steps:

step 1: compressing the search space of the optimal translation vector by calculating mutual information between the performance index and the process parameter, and then calculating to obtain the optimal translation vector of the high-dimensional SRAM circuit by using a sequence quadratic programming method;

and 2, step: calculating a hyper-parameter of conjugate prior distribution by using the low-dimensional SRAM circuit performance value; the method comprises the following steps:

step 2.1: constructing a low-dimensional SRAM circuit only comprising 1 storage unit and 1 sense amplifier by a method of removing most storage units in the high-dimensional SRAM circuit; with N (μ = OSV) _L σ) gaussian distribution, sampled in the parameter space of the low-dimensional SRAM circuit, wherein the mean μ = OSV of the gaussian distribution _L ，OSV _L Only the low-dimensional optimal translation vector of the remaining dimension after dimension reduction by a dimension reduction method is reserved in the optimal translation vector v of the high-dimensional SRAM circuit; sigma is the standard deviation of the given disturbance process parameter;

step 2.2: obtaining the performance value y of the sampling sample points through circuit simulation _j ；

Step 2.3: fitting performance distribution parameters of the low-dimensional SRAM circuit through a maximum likelihood method and an expectation maximization algorithm;

fitting jth performance index y of an SRAM circuit using a hybrid Gaussian model _j Is distributed, i.e.

Wherein the content of the first and second substances,

and κ _i ＞0，N(y _j ；μ _i ,σ _i ) Is a mean value of μ _i Standard deviation of σ _i A gaussian distribution of (d);

the Gaussian mixture model can be fitted to most continuous distributions; sampling data y according to the existing low-dimensional SRAM circuit _j ^k (ii) a k =1,2, …, m' }, the log-likelihood function resulting in the maximum likelihood method is

Parameter κ in the above formula _i,L ,μ _i,L ,σ _i,L Can be calculated by an expectation maximization algorithm; the expectation maximization algorithm comprises two steps, namely an expectation step and a maximization step;

in the expectation step, y can be obtained according to the current parameter value _j ^k Belonging to different Gaussian distributions N (y) _j ；μ _i,L ,σ _i,L ) A posteriori probability of

In the maximization step, updating parameter values;

repeating the expectation step and the maximization step until the parameters are converged to obtain the distribution parameter k _i,L ,μ _i,L ,σ _i,L ,i＝1..n；

Step 2.4: selecting mixed Gaussian distribution as a likelihood function, and selecting conjugate prior of the mixed Gaussian distribution as prior distribution;

assuming that the performance profile of the high dimensional SRAM circuit is similar but not exactly identical to the low dimensional SRAM circuit performance profile; obtaining an accurate performance distribution model of the high-dimensional SRAM circuit through a small number of high-dimensional sample points and combining the prior knowledge of the existing low-dimensional SRAM circuit;

the conjugate prior distribution of the Gaussian mixture distribution is

Wherein D (kappa; gamma) is Dirichlet Distribution (Dirichlet Distribution), N (mu) _i ；ν _i ,η _i ^-1 σ _i ) Is Gaussian Distribution (Gaussian Distribution), W (σ) _i ^-1 ；α _i ,β _i ) Is a wiskart Distribution (wishirt Distribution);

step 2.5: calculating the hyperparameters of the performance distribution of the high-dimensional SRAM circuit by using the sample points of the low-dimensional SRAM circuit and adopting a maximum likelihood method;

if there is a sample point set y on the low dimensional SRAM circuit _j ^k (ii) a k =1,2, …, m' }, using y _j ⁽ⁱ⁾ The labeling mixed gaussians adopt subsets obtained by sampling from ith gaussians, and the hyper-parameters are calculated by a maximum likelihood method, namely:

wherein m is _i ＝|y _j ⁽ⁱ⁾ Is y _j ⁽ⁱ⁾ The number of sample points in the set, var and mean are variance and mean, respectively;

assuming similar performance distributions of the low-dimensional SRAM and the high-dimensional SRAM, the hyper-parameters can be calculated by the low-dimensional sample points, and then the hyper-parameters are modified to be suitable for the high-dimensional SRAM circuit, namely the hyper-parameters of the performance distribution of the high-dimensional SRAM circuit are

Wherein m is _i ＝κ _i,L m’，y _j,H (. And y) _j,L (. H) represents the performance of the high-dimensional SRAM circuit and the low-dimensional SRAM circuit, respectively; OSV _H Is OSV calculated in high-dimensional SRAM circuit _L Is at a high dimensional OSV _H Only keeping the OSV of dimensionality reduced by a dimensionality reduction method; kappa _i,L ,μ _i,L ,σ _i,L Is the performance distribution parameter of the low-dimensional SRAM circuit calculated in step 2.3;

and step 3: calculating Gaussian mixture model parameters of performance distribution of the high-dimensional SRAM circuit by using an expectation maximization algorithm;

and 4, step 4: and calculating the failure rate of the high-dimensional SRAM circuit according to the Gaussian mixture model parameters of the performance distribution of the high-dimensional SRAM circuit.

2. The method for analyzing the yield of the SRAM circuit according to the Bayesian model of claim 1, wherein in the step 1, the optimal translation vector of the high-dimensional SRAM circuit is calculated through mutual information and sequence quadratic programming; the method comprises the following steps:

step 1.1: sampling in a parameter space by adopting Gaussian distribution of 8 sigma standard deviations in a high-dimensional disturbance parameter space, wherein the sigma is the standard deviation of a given disturbance process parameter; the probability density distribution function of the disturbance process parameter is Gaussian distribution N (0, sigma), and after sampling is carried out by adopting the Gaussian distribution of N (0,8 sigma), failure points of the high-dimensional SRAM circuit are obtained;

step 1.2: obtaining the performance value y of the sample point through circuit simulation _j ，j＝1,…,p；

Step 1.3: calculating mutual information of each process parameter variable and performance by using a K-Nearest neighbors (K-Nearest neighbors);

step 1.4: selecting D' variables with the maximum mutual information value, so that the sum of the mutual information of the variables accounts for more than 95% of the total mutual information;

step 1.5: in the D' space after the dimension reduction, calculating an optimal translation vector by using sequence quadratic programming;

calculating an optimal translation vector by using sequential quadratic programming; calculating the optimal translation vector can be equivalent to solving the following optimization problem:

where | | · | | is the L2 norm of the vector, y _j (v) Is the j individual performance index, y, obtained by circuit simulation _j Is the failure threshold for a given jth property;

and solving the optimization problem to obtain an optimal solution v, namely the optimal translation vector of the high-dimensional SRAM circuit.

3. The bayesian-model-based SRAM circuit yield analysis method according to claim 2, wherein in substep 1.3, the concept of mutual information is used to reduce the dimensions of the circuit; wherein the content of the first and second substances,

mutual information, also called transfer information, is a measure of the interdependence between two variables; mutual information is a non-negative number, when the value is zero, the two variables are mutually independent, and the larger the value is, the stronger the mutual dependence is; mutual information of two discrete random variables X and Y is defined as

Wherein p (x, y) is a joint distribution, and p (x), p (y) are boundary distributions;

the mutual information is obtained by calculation through a k-neighborhood algorithm in an open source library scimit-lern.

4. The bayesian-model-based SRAM circuit yield analysis method according to claim 1, wherein in said step 3, gaussian mixture model parameters of the performance distribution of the high-dimensional SRAM circuit are calculated by an expectation-maximization method; wherein the maximum a posteriori calculation parameters are used, and the logarithm maximum a posteriori is

Wherein m is the number of high-dimensional sample points;

calculating parameters using an expectation-maximization algorithm;

the expected steps are as follows:

the maximization step is as follows:

continuously circulating the expectation step and the maximization step until the parameters are converged to obtain the performance distribution parameter kappa of the high-dimensional SRAM circuit _i,H ,μ _i,H ,σ _i,H ,i＝1..n。

5. The bayesian-model-based SRAM circuit yield analysis method of claim 1, wherein in said step 4, the failure boundary of the high-dimensional SRAM circuit is approximated by a regression hyperplane, and the failure rate of the high-dimensional SRAM circuit is calculated by an analytical formula; wherein a regression hyperplane is used to approximate the failure boundary in the high dimension, the hyperplane being perpendicular to the optimal translation vector; when the Gaussian distribution with the optimal translation vector as the mean value is subjected to integration, the obtained integral value is consistent with the requirement no matter the failure area obtained by hyperplane approximation is used as an integration area or the actual failure area is used as an integration area; thus, the offset of the hyperplane is

Wherein the content of the first and second substances,

with the best translation vector as the meanFailure rate of gaussian distribution, N (v x, 1), norm cdf is the cumulative distribution function of standard gaussian distribution, norm nv is the inverse function of the cumulative distribution function of standard gaussian distribution;

after obtaining the regression hyperplane, the failure rate of the final high-dimensional SRAM circuit can be obtained by adopting the following analytic formula

P _fail ＝1-normcdf(||OSV||+offset) (17)。

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