CN110601811B

CN110601811B - Safety test mode decoding circuit used in DFT

Info

Publication number: CN110601811B
Application number: CN201910865388.4A
Authority: CN
Inventors: 何立柱; 冯建华
Original assignee: SCHOOL OF SOFTWARE AND MICROELECTRONICS PEKING UNIVERSITY
Current assignee: SCHOOL OF SOFTWARE AND MICROELECTRONICS PEKING UNIVERSITY
Priority date: 2019-09-12
Filing date: 2019-09-12
Publication date: 2022-10-21
Anticipated expiration: 2039-09-12
Also published as: CN110601811A

Abstract

The present invention relates to a secure test pattern decoding circuit used in DFT. It includes: a 15-bit binary counter; a counter-based mode decoder coupled to the 15-bit binary counter, the counter-based mode decoder outputting a signal representative of a corresponding mode according to a count output by the 15-bit binary counter; a secure reset generator connected to the 15-bit binary counter, the secure reset generator outputting a signal representative of a respective state; the test mode decoding circuit further comprises a forced reset circuit, FF and SRAM for performing memory repair. The invention solves the problem that the traditional combinational logic decoder is easy to cause the false triggering of a circuit or the attack behavior of a third party, and improves the safety performance of a chip.

Description

Safety test mode decoding circuit used in DFT

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a safe test mode decoding circuit used in DFT.

Background

Conventional DFT-mode decoding circuits are simple combinational logic decoders such as conventional 3-8 decoders. As the security requirements of chips/integrated circuits increase. Conventional combinational logic decoders can easily result in false triggering of the circuit, or a perceived third party attack. In order to improve the security performance of the chip, a processing technique of the test mode decoding circuit in DFT, which enhances the security, needs to be provided. The user requirements are specifically as follows: it is highly desirable to establish a secure test mode configuration to prevent third parties from attacking the clock chip. To reduce such risks as much as possible, static test mode configuration should not be allowed.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a safe test mode decoding circuit used in DFT, which solves the problem that the traditional combinational logic decoder is easy to cause false triggering of the circuit or attack behavior of a third party, and improves the safety performance of a chip.

Technical objects that can be achieved by the present invention are not limited to what has been particularly described above, and other technical objects that are not described herein will be more clearly understood by those skilled in the art from the following detailed description.

The technical scheme for solving the technical problems is as follows:

according to an aspect of the present disclosure, the present invention provides a test mode decoding circuit for security used in DFT, the test mode decoding circuit comprising:

a 15-bit binary counter;

a counter-based mode decoder coupled to the 15-bit binary counter, the counter-based mode decoder outputting a signal representative of a corresponding mode according to a count output by the 15-bit binary counter;

a secure reset generator connected to the 15-bit binary counter, the secure reset generator outputting a signal representative of a respective state;

the circuit further includes a forced reset circuit for memory repair, FF and SRAM,

wherein, during a period when the main test MODE pin is 1, when the test MODE reset pin is set to 0, the value of FF is cleared, and the value of FF is cleared before transition to SCAN _ MODE1, an actual test operation can be performed once the value of FF is cleared, when the main test MODE pin transitions from 1 to 0, the value of FF is cleared, and the values on the address bits, the data bits, and the control bits of the SRAM are cleared before transition to other SUB _ DFT _ MODE, such as MBIST _ MODE, MODEs, and an actual test operation can be performed once the values on the address bits, the data bits, and the control bits of the SRAM are cleared.

Optionally, in the circuit as described above, the reset is 0 when the security reset generator is in the initialize state, the register and the memory are in the CLEAR state when the security reset generator is in the SEC _ CLEAR0 state, the security reset sequence is waited to be started when the security reset generator is in the IDLE state, and the register and the memory are in the CLEAR state when the security reset generator is in the SEC _ CLEAR1 state.

Alternatively, in the circuit as described above, the forced reset circuit is implemented by DFT and operates in the same system function mode as the repair circuit.

Optionally, in the circuit as described above, the forced reset circuit further includes a glitch removal circuit and a reset synchronization circuit.

The above-described embodiments are only some of the embodiments of the present invention, and those skilled in the art can derive and understand various embodiments including technical features of the present invention from the following detailed description of the present invention.

It will be appreciated by persons skilled in the art that the effects that can be achieved by the present invention are not limited to what has been particularly described hereinabove and other advantages of the present invention will be more clearly understood from the following detailed description.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention, illustrate embodiments of the invention and together with the description serve to explain the principle of the invention.

FIG. 1 is a schematic diagram of a test mode decoding circuit for security according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a test mode decoding circuit with a safety reset generator according to an embodiment of the present invention.

Fig. 3 is a state transition diagram of a safety reset generator of the test mode decoding circuit according to an embodiment of the present invention.

Fig. 4 is a timing diagram of a test mode decoding circuit according to an embodiment of the invention.

Fig. 5 is a timing diagram of a test mode decoding circuit according to an embodiment of the invention.

Fig. 6 is a timing diagram of a test mode decoding circuit according to an embodiment of the invention.

Fig. 7 is a schematic diagram of a forced reset circuit according to an embodiment of the present invention.

Fig. 8 is a timing diagram of a forced reset circuit according to an embodiment of the present invention.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. The detailed description, which will be given below with reference to the accompanying drawings, is intended to explain exemplary embodiments of the present invention, rather than to show the only embodiments that can be implemented according to the present invention. The following detailed description includes specific details in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details.

In some instances, well-known structures and devices are omitted or shown in block diagram form, focusing on important features of the structures and devices so as not to obscure the concept of the present invention. The same reference numbers will be used throughout the specification to refer to the same or like parts.

The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.

In the description of the present invention, it is to be understood that the terms "upper", "lower", "center", "inner", "outer", "top", "bottom", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Fig. 1 is a schematic diagram of a test mode decoding circuit using security according to an embodiment of the present invention. As shown in fig. 1, the present invention provides a test pattern decoding circuit for security used in DFT, wherein the test pattern decoding circuit comprises: a 15-bit binary counter; a counter-based mode decoder coupled to the 15-bit binary counter, the counter-based mode decoder outputting a signal representative of a corresponding mode according to a count output by the 15-bit binary counter; a secure reset generator connected to the 15-bit binary counter, the secure reset generator outputting a signal representative of a respective state; the circuit also includes a forced reset circuit for performing memory repair, FF and SRAM, wherein during a main test MODE pin of 1, when the test MODE reset pin is set to 0, the value of FF is cleared and the value of FF is cleared prior to conversion to SUB _ DFT _ MODE, such as SCAN _ MODE, once the value of FF is cleared, actual test operations can be performed, when the main test MODE pin is converted from 1 to 0, the value of FF is cleared prior to conversion to other SUB _ DFT _ MODE, such as MBIST _ MODE, the values on the address bits, data bits and control bits of SRAM are cleared, and actual test operations can be performed once the values on the address bits, data bits and control bits of the SRAM are cleared.

In particular, table 1 below shows the operating modes of a test mode decoding circuit having a counter-based mode decoder.

TABLE 1

According to an embodiment of the present invention, the test mode decoding circuit has a safety reset generator, as shown in fig. 2. Fig. 4-6 show timing diagrams of test mode decoding circuits provided by embodiments of the present invention.

Fig. 3 illustrates a state transition diagram of a secure reset generator provided by an embodiment of the present invention. According to the embodiment of the invention, in the circuit as described above, the safety reset generator is reset to 0 when in the INITIAL state, the register and the memory are in the zero state when in the SEC _ CLEAR0 state, the safety reset generator waits to start the safety reset sequence when in the IDLE state, and the register and the memory are in the zero state when in the SEC _ CLEAR1 state.

According to an embodiment of the present invention, in the circuit as described above, the forced reset circuit is implemented by DFT and operates in the same system function mode as the repair circuit. According to an embodiment of the present invention, in the circuit as described above, the forced reset circuit further includes a glitch removal circuit and a reset synchronization circuit, as shown in fig. 7 to 8.

From the above description of the embodiments, it is obvious for those skilled in the art that the present application can be implemented by software and necessary general hardware, and of course, can also be implemented by hardware. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which may be stored in a computer-readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute the methods described in the embodiments of the present application.

As mentioned above, a detailed description of the preferred embodiments of the invention has been given to enable those skilled in the art to make and practice the invention. Although the present invention has been described with reference to exemplary embodiments, those skilled in the art will appreciate that various modifications and changes can be made in the present invention without departing from the spirit or scope of the invention described in the appended claims. Thus, the present invention is not intended to be limited to the particular embodiments shown and described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A secure test mode decoding circuit for use in DFT, the test mode decoding circuit comprising:

a 15-bit binary counter;

a secure reset generator connected to the 15-bit binary counter, the secure reset generator outputting signals representative of respective states;

the test mode decoding circuit further includes a forced reset circuit for performing memory repair, an FF and an SRAM,

wherein, during a period when the main test MODE pin is 1, when the test MODE reset pin is set to 0, the value of FF is cleared, and the value of FF is cleared before transition to SCAN _ MODE1, an actual test operation is enabled once the value of FF is cleared, when the main test MODE pin transitions from 1 to 0, the values on the address bit, the data bit and the control bit of the SRAM are cleared before transition to the other SUB _ DFT _ MODE, and an actual test operation is enabled once the values on the data bit and the control bit of the SRAM are cleared.

2. The test mode decoding circuit of claim 1,

the method is characterized in that the reset is 0 when the security reset generator is in an INITIAL state, the register and the memory are in a CLEAR state when the security reset generator is in an SEC _ CLEAR0 state, a security reset sequence is waited to be started when the security reset generator is in an IDLE state, and the register and the memory are in a CLEAR state when the security reset generator is in an SEC _ CLEAR1 state.

3. The test mode decoding circuit of claim 1,

wherein the forced reset circuit is implemented by DFT and operates in the same system functional mode as the repair circuit.

4. The test mode decoding circuit of claim 1,

the forced reset circuit is characterized by further comprising a burr removing circuit and a reset synchronous circuit.