CN110600609B - Memristor memory and preparation method thereof - Google Patents
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- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of switching materials, e.g. deposition of layers
- H10N70/023—Formation of switching materials, e.g. deposition of layers by chemical vapor deposition, e.g. MOCVD, ALD
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Abstract
The invention relates to a memristor memory, which comprises a silicon substrate, an insulating layer, a bottom electrode, a functional layer and a top electrode which are sequentially arranged in a layered manner, wherein the main material of the functional layer is SnO 2 Or ZnO or TiO 2 Bi is doped in the material of the functional layer. The invention also provides a preparation method of the memristor memory, which comprises the steps of sequentially preparing an insulating layer, a bottom electrode, a functional layer and a top electrode on a silicon substrate by adopting a magnetron sputtering or atomic deposition method, so that the memristor memory of the invention can be prepared. The invention has the advantages of non-volatile storage, low operation voltage, high writing speed, simple structure, high consistency, micro watt (mu W) level operation power and the like.
Description
Technical Field
The invention relates to the technical field of underwater sound engineering, in particular to a memristor memory and a preparation method thereof.
Background
With the advent of the age of 5G, big data and artificial intelligence, complex computing tasks and varied application scenarios have put demands on computer performance for higher throughput and lower power consumption. Under the traditional von neumann computing architecture, the operation is separated from the storage unit, and when a big data moving task is processed, the frequent transmission and the moving of the data consume a great deal of time and energy, so that the problems of strong storage, strong power consumption and the like of the traditional computing architecture are caused, and therefore, a new computing architecture needs to be explored. The integrated calculation is a brand new calculation architecture based on a novel nonvolatile memristor memory device, data movement is not needed, and local calculation can be directly completed at the position where information is stored. The novel logic architecture can break the bottleneck problem of data transmission blocking through a device-level integrated path, and breaks through the limitation of the von neumann architecture in the existing logic system. The memristor memory is based on the memory calculation integrated function of the analog resistance change device, can finish calculation at the same time at the storage position, is very suitable for high-efficiency and parallel big data calculation and storage, and shows huge energy efficiency ratio and hardware overhead advantages.
The current memristor memory is composed of a lower electrode, a functional layer and a top electrode, and has the advantages of being simple in structure, easy to control material components, compatible in preparation process and semiconductor process, and the like. The double-layer functional layer is prepared by replacing electrode materials and functional layer materials, and performance indexes such as erasing voltage, writing voltage, operating current and the like in the resistance conversion process are reduced in the modes of reducing current and voltage parameters in the conductive filament forming process and the erasing process, so that the memristor memory device with lower power consumption is prepared. The doping influences the type, concentration and distribution of carriers in the semiconductor, so that the doping of proper elements can reduce the performance indexes such as erasing voltage, operating current and the like in the resistance conversion process, thereby achieving the effect of reducing the power consumption.
Tin oxide (SnO) 2 ) Although it has important applications in transparent conductive electrodes and gas sensors as a binary oxide semiconductor, it has little application in memristive memories. Memristor memories using pure tin oxide films as resistive layers generally have the problems of unstable erasing voltage, higher operating current and the like, and the memory performance is reduced. These problems with tin oxide can be solved by doping with appropriate elements. Several doping elements have been reported to date to improve the performance of tin oxide based memristive memories, such as iron, nitrogen and manganese. Although the performance is improved compared with the intrinsic tin oxide based memristor, the intrinsic tin oxide based memristor has the defects of poor consistency, higher operation current, higher power consumption and the like.
Disclosure of Invention
Aiming at the technical problems in the prior art, the invention provides a memristor memory and a preparation method thereof, and the memristor memory has the advantages of non-volatile storage, low operation voltage, high writing speed, simple structure, high consistency, micro watt (mu W) level operation power and the like.
The technical scheme for solving the technical problems is as follows: a memristor memory comprises a silicon substrate, an insulating layer and a bottom electrode which are sequentially arranged in a layered mannerThe electrode, the functional layer and the top electrode, wherein the main material of the functional layer is SnO 2 Or ZnO or TiO 2 Bi is doped in the material of the functional layer.
On the basis of the technical scheme, the invention can be improved as follows.
Further, the doping content of Bi is 2.3-10%.
Preferably, the thickness of the functional layer is 10-50 nm.
Further, the material of the bottom electrode is one of TiN, FTO, ZTO.
Preferably, the material of the bottom electrode is TiN, and the thickness is 50-300 nm.
Further, the material of the top electrode is one of ITO, FTO, ZTO, tiN.
Preferably, the material of the top electrode is ITO, and the thickness is 100-300 nm.
Further, the thickness of the insulating layer is 100-200 nm. The material of the insulating layer is preferably SiO 2 。
The invention also provides a technical scheme of the preparation method of the memristor memory, which comprises the following steps:
1) Cleaning a silicon substrate;
2) Placing a target material serving as an insulating layer on a target table, and preparing the insulating layer on a silicon substrate by utilizing a magnetron sputtering or atomic layer deposition method;
3) Placing a target material serving as a bottom electrode on a target table, and preparing the bottom electrode on the insulating layer (2) prepared in the step 2) by utilizing a magnetron sputtering or atomic layer deposition method;
4) Placing a target material serving as a main material of the functional layer on a target table, placing a doped Bi target material on the target table, preparing the functional layer on the bottom electrode prepared in the step 2) by utilizing a magnetron sputtering or atomic layer deposition method, selecting different power ratios for the Bi target material and the target material of the main material, sputtering or depositing simultaneously, and controlling the doping content of Bi by utilizing sputtering or depositing power of different ratios;
5) And (3) placing a target material serving as a top electrode on a target table, preparing the top electrode on the functional layer prepared in the step (4) by utilizing a magnetron sputtering or atomic layer deposition method, and obtaining the memristor after preparation.
On the basis of the technical scheme, the invention can be improved as follows.
Further, in the steps 2) to 5), a magnetron sputtering method is adopted.
Further, in the steps 2) to 5), the vacuum degree of the magnetron sputtering is less than 5x10 < -4 > Pa; in the steps 2) to 5), the working pressure of the magnetron sputtering is 0.1 Pa to 0.3Pa.
Further, the sputtering power of the step 2) is 30 to 100W, the sputtering power of the step 3) is 50 to 100W, and the sputtering power of the step 5) is 40 to 60W.
Further, the doping content of Bi in the step 4) is 2.3-10%, the sputtering power of the target material of the main material is 100W, bi, and the sputtering power of the target material is 5-9W.
The beneficial effects of the invention are as follows: the invention provides a method for doping bismuth (Bi) element into tin oxide (SnO) 2 ) Or zinc oxide (ZnO) or titanium oxide (TiO) 2 ) Memristive memory as functional layer and preparation method thereof (ZnO and TiO are adopted 2 And adopt SnO 2 The memory device has the advantages of nonvolatile memory, high writing speed, simple structure, simple preparation method, low cost and the like, and has enough memory window, high consistency, lower operating voltage, about operating current and lower operating power, so the bismuth-doped tin oxide is a semiconductor material with great development potential and research value.
The operation current of the oxide memristor memory device reported at present is generally higher, the operation power consumption is generally higher, along with the continuous improvement of the chip integration level, the unit volume temperature rise of the device caused by the Joule heat generated by the overlarge power consumption is quite remarkable, so that the stability of the device performance is damaged, the service life of the device is influenced, and therefore, the reduction of the power consumption of the device is still one of important contents of the research of the memristor memory.
Drawings
FIG. 1 is a schematic diagram of an embodiment of the present invention;
FIG. 2 is a cross-sectional view of a thin film Scanning Electron Microscope (SEM) of the present invention;
FIG. 3 is a graph showing the atomic ratio of characteristic peaks of oxygen element, tin element and bismuth element to each element of the film of the present invention;
FIG. 4 is a graph showing the current-voltage (I-V) curves of memristive devices of the first, fifth and third embodiments of the present invention;
FIG. 5 is a graph showing the high and low resistance profiles of memristor devices obtained in embodiments I and III;
in the drawings, the list of components represented by the various numbers is as follows:
1. the semiconductor device comprises a silicon substrate, 2, an insulating layer, 3, a bottom electrode, 4, a functional layer, 5 and a top electrode.
Detailed Description
The principles and features of the present invention are described below with reference to the drawings, the examples are illustrated for the purpose of illustrating the invention and are not to be construed as limiting the scope of the invention.
The invention designs a low-power consumption memristor memory, which is mainly composed of a silicon substrate 1, an insulating layer 2, a bottom electrode 3, a functional layer 4 and a top electrode 5 which are sequentially arranged in a layered manner. The main material SnO of the functional layer 4 2 Or ZnO or TiO 2 The material of the functional layer 4 is doped with Bi. As the applicant tests, the Bi is adopted to dope ZnO and TiO 2 Technical effects of the functional layer 4 and the doping of SnO with Bi 2 Substantially the same, the embodiment is to dope SnO with Bi 2 As the functional layer 4, a specific description is made.
In order to further improve the performance of low power consumption, the invention can be further improved as follows.
Further, the doping content of Bi is 2.3-10%. Through research and experiment on the doping content of Bi, the applicant finally obtains that the power consumption of the memristor memory can be kept at a lower level and the performance is stable under the doping content. Specific tests and results are shown in the examples.
Preferably, the thickness of the functional layer is 10-50 nm.
Further, the material of the bottom electrode is one of TiN, FTO, ZTO.
Preferably, the material of the bottom electrode is TiN, and the thickness is 50-300 nm.
Further, the material of the top electrode is one of ITO, FTO, ZTO, tiN.
Preferably, the material of the top electrode is ITO, and the thickness is 100-300 nm.
Further, the thickness of the insulating layer is 100-200 nm. The material of the insulating layer is preferably SiO 2 。
Film characterization and device testing were performed on the present invention:
the prepared bismuth-doped tin oxide film was subjected to Scanning Electron Microscope (SEM) analysis, and the specific results are shown in fig. 2. The instrument used was JSM-7100F and surface topography was characterized at a voltage of 15 kV.
And testing the element components of the prepared bismuth-doped tin oxide film by using an X-ray photoelectron spectrometer. The specific results are shown in FIG. 3.
The memristive memory provided by the invention can be prepared by adopting the following method, and comprises the following steps:
1) Cleaning the silicon substrate 1;
2) Placing a target material serving as an insulating layer 2 on a target table, and preparing the insulating layer 2 on the silicon substrate 1 by utilizing a magnetron sputtering or atomic layer deposition method;
3) Placing a target material serving as a bottom electrode 3 on a target table, and preparing the bottom electrode 3 on the insulating layer 2 prepared in the step 2) by utilizing a magnetron sputtering or atomic layer deposition method;
4) Placing a target material serving as a main material of the functional layer 4 on a target table, placing a doped Bi target material on the target table, preparing the functional layer 4 on the bottom electrode 3 prepared in the step 2) by utilizing a magnetron sputtering or atomic layer deposition method, selecting different power ratios for the Bi target material and the target material of the main material, sputtering or depositing simultaneously, and controlling the doping content of Bi by utilizing sputtering or deposition power of different ratios;
5) And (3) placing a target material serving as a top electrode 5 on a target table, preparing the top electrode 5 on the functional layer 4 prepared in the step (4) by utilizing a magnetron sputtering or atomic layer deposition method, and obtaining the memristor after preparation.
In order to improve the control accuracy and save the cost, the preparation method of the invention can be improved as follows.
Further, in the steps 2) to 5), a magnetron sputtering method is adopted.
Further, in the steps 2) to 5), the vacuum degree of the magnetron sputtering is less than 5x10 < -4 > Pa; in the steps 2) to 5), the working pressure of the magnetron sputtering is 0.1 Pa to 0.3Pa.
Further, the sputtering power of the step 2) is 30 to 100W, the sputtering power of the step 3) is 50 to 100W, and the sputtering power of the step 5) is 40 to 60W.
Further, the doping content of Bi in the step 4) is 2.3-10%, the sputtering power of the target material of the main material is 100W, bi, and the sputtering power of the target material is 5-9W.
Example 1
A memristor with low power consumption is composed of silicon substrate 1, insulating layer 2, bottom electrode 3, functional layer 4 and top electrode 5, wherein the insulating layer 2 is made of silicon oxide (SiO) 2 ) The bottom electrode 3 is made of titanium nitride (TiN), and the functional layer 4 is made of TiN oxide (SnO) 2 ) The top electrode 5 material is Indium Tin Oxide (ITO).
Placing the silicon wafer into an ultrasonic instrument, sequentially respectively carrying out ultrasonic treatment for 15min by using deionized water, acetone and absolute ethyl alcohol to obtain a cleaned silicon substrate 1;
A silicon oxide insulating layer 2 is prepared on a silicon substrate 1 by adopting a magnetron sputtering method, wherein the magnetron sputtering vacuum degree is less than 5x10 < -4 > Pa, the substrate temperature is room temperature, the working pressure is 0.3Pa, the radio frequency sputtering power is 60W, the flow rate of introduced argon is 30sccm, the time is 35min, and the thickness is 180nm.
In SiO 2 A layer of titanium nitride bottom electrode 3 is prepared on the substrate by adopting a magnetron sputtering method, and the vacuum degree of the magnetron sputtering is highLess than 5x10 < -4 > Pa, room temperature of the substrate, 0.3Pa of working pressure, 80W of direct current sputtering power, 30sccm of argon flow, 25min of time and 160nm of thickness.
And placing the prepared bottom electrode 3 in a magnetron sputtering instrument, placing a tin oxide target serving as the functional layer 4 in a radio frequency sputtering target table, wherein the magnetron sputtering vacuum degree is less than 5x10 < -4 > Pa, the substrate temperature is room temperature, the working pressure is 0.3Pa, the radio frequency sputtering power is 100W, and the flow rate of argon is 30sccm, the time is 1.5min and the thickness is 20nm, so that the functional layer 4 is prepared.
Preparing an indium tin oxide top electrode 5 doped with hafnium by using a magnetron sputtering instrument, wherein an indium tin oxide target material is placed at a radio frequency sputtering target position and sputtered, the magnetron sputtering vacuum degree is less than 5x10 < -4 > Pa, the substrate temperature is room temperature, the working pressure is 0.3Pa, the sputtering power of indium tin oxide is 50W, the flow rate of introduced argon is 30sccm, the time is 40min, and the thickness is 200nm.
Example two
A memristor with low power consumption is composed of silicon substrate 1, insulating layer 2, bottom electrode 3, functional layer 4 and top electrode 5, wherein the insulating layer 2 is made of silicon oxide (SiO) 2 ) The bottom electrode 3 is made of titanium nitride (TiN), and the functional layer 4 is made of bismuth doped TiN oxide (Bi: snO) 2 ) The thickness is 20nm, the material of the top electrode 5 is Indium Tin Oxide (ITO) and the thickness is 200nm.
The silicon wafer is placed in an ultrasonic instrument, and is respectively and ultrasonically treated for 15min by deionized water, acetone and absolute ethyl alcohol in sequence, so that a cleaned silicon substrate 1 is obtained.
A silicon oxide insulating layer 2 is prepared on a silicon substrate 1 by adopting a magnetron sputtering method, wherein the magnetron sputtering vacuum degree is less than 5x10 < -4 > Pa, the substrate temperature is room temperature, the working pressure is 0.3Pa, the radio frequency sputtering power is 60W, the flow rate of introduced argon is 30sccm, the time is 35min, and the thickness is 180nm.
A layer of titanium nitride bottom electrode 3 is prepared on the silicon oxide insulating layer 2 by adopting a magnetron sputtering method, the magnetron sputtering vacuum degree is less than 5x10 < -4 > Pa, the substrate temperature is room temperature, the working pressure is 0.3Pa, the direct current sputtering power is 80W, the flow rate of introduced argon is 30sccm, the time is 25min, and the thickness is 160nm.
And (3) placing the prepared bottom electrode 3 in a magnetron sputtering instrument, respectively placing bismuth and tin oxide targets at the direct current sputtering target position and the radio frequency sputtering target position, sputtering simultaneously, wherein the magnetron sputtering vacuum degree is less than 5x10 < -4 > Pa, the substrate temperature is room temperature, the working pressure is 0.3Pa, the sputtering power of bismuth is 5W, the sputtering power of tin oxide is 100W, the flow rate of argon is 30sccm, the time is 1.4min, the thickness is 20nm, and the content of bismuth element is about 2.3%, so that the functional layer 4 is prepared.
Preparing an indium tin oxide top electrode 5 doped with hafnium by using a magnetron sputtering instrument, wherein an indium tin oxide target material is placed at a radio frequency sputtering target position and sputtered, the magnetron sputtering vacuum degree is less than 5x10 < -4 > Pa, the substrate temperature is room temperature, the working pressure is 0.3Pa, the sputtering power of indium tin oxide is 50W, the flow rate of introduced argon is 30sccm, the time is 40min, and the thickness is 200nm.
Example III
A memristor with low power consumption is composed of silicon substrate 1, insulating layer 2, bottom electrode 3, functional layer 4 and top electrode 5, wherein the insulating layer 2 is made of silicon oxide (SiO) 2 ) The bottom electrode 3 is made of titanium nitride (TiN), and the functional layer 4 is made of bismuth doped TiN oxide (Bi: snO) 2 ) The thickness is 20nm, the material of the top electrode 5 is Indium Tin Oxide (ITO) and the thickness is 200nm.
The silicon wafer is placed in an ultrasonic instrument, and is respectively and ultrasonically treated for 15min by deionized water, acetone and absolute ethyl alcohol in sequence, so that a cleaned silicon substrate 1 is obtained.
A silicon oxide insulating layer 2 is prepared on a silicon substrate 1 by adopting a magnetron sputtering method, wherein the magnetron sputtering vacuum degree is less than 5x10 < -4 > Pa, the substrate temperature is room temperature, the working pressure is 0.3Pa, the radio frequency sputtering power is 60W, the flow rate of introduced argon is 30sccm, the time is 35min, and the thickness is 180nm.
A layer of titanium nitride bottom electrode 3 is prepared on the insulating layer 2 by adopting a magnetron sputtering method, wherein the magnetron sputtering vacuum degree is less than 5x10 < -4 > Pa, the substrate temperature is room temperature, the working pressure is 0.3Pa, the direct current sputtering power is 80W, the flow rate of introduced argon is 30sccm, the time is 25min, and the thickness is 160nm.
And placing the prepared bottom electrode 3 in a magnetron sputtering instrument, respectively placing bismuth and tin oxide targets at the direct current sputtering target position and the radio frequency sputtering target position, sputtering simultaneously, wherein the magnetron sputtering vacuum degree is less than 5x10 < -4 > Pa, the substrate temperature is room temperature, the working pressure is 0.3Pa, the sputtering power of bismuth is 6W, the sputtering power of tin oxide is 100W, the flow rate of argon is 30sccm, the time is 1.3min, the thickness is 20nm, the content of bismuth element is about 4.8%, and the functional layer 4 is prepared.
Preparing an indium tin oxide top electrode 5 doped with hafnium by using a magnetron sputtering instrument, wherein an indium tin oxide target material is placed at a radio frequency sputtering target position and sputtered, the magnetron sputtering vacuum degree is less than 5x10 < -4 > Pa, the substrate temperature is room temperature, the working pressure is 0.3Pa, the sputtering power of indium tin oxide is 50W, the flow rate of introduced argon is 30sccm, the time is 40min, and the thickness is 200nm. The prepared bismuth-doped tin oxide film was subjected to Scanning Electron Microscope (SEM) analysis. The apparatus used for Scanning Electron Microscopy (SEM) was JSM-7100F and surface topography was characterized at a voltage of 15kV, and FIG. 2 is a cross-sectional view of a Scanning Electron Microscope (SEM) of the device of this example. And testing the element components of the prepared bismuth-doped tin oxide film by using an X-ray photoelectron spectrometer. FIG. 3 shows characteristic peaks of Bi, sn and O elements of the present example, and atomic ratios of 4.8%, 26.6% and 68.6%, respectively.
Example IV
A memristor with low power consumption is composed of silicon substrate 1, insulating layer 2, bottom electrode 3, functional layer 4 and top electrode 5, wherein the insulating layer 2 is made of silicon oxide (SiO) 2 ) Bottom electrode 3 materialThe material is titanium nitride (TiN), and the material of the functional layer 4 is bismuth doped TiN oxide (Bi: snO) 2 ) The thickness is 20nm, the material of the top electrode 5 is Indium Tin Oxide (ITO) and the thickness is 200nm.
The silicon wafer is placed in an ultrasonic instrument, and is respectively and ultrasonically treated for 15min by deionized water, acetone and absolute ethyl alcohol in sequence, so that a cleaned silicon substrate 1 is obtained.
A silicon oxide insulating layer 2 is prepared on a silicon substrate 1 by adopting a magnetron sputtering method, wherein the magnetron sputtering vacuum degree is less than 5x10 < -4 > Pa, the substrate temperature is room temperature, the working pressure is 0.3Pa, the radio frequency sputtering power is 60W, the flow rate of introduced argon is 30sccm, the time is 35min, and the thickness is 180nm.
A layer of titanium nitride bottom electrode 3 is prepared on the insulating layer 2 by adopting a magnetron sputtering method, wherein the magnetron sputtering vacuum degree is less than 5x10 < -4 > Pa, the substrate temperature is room temperature, the working pressure is 0.3Pa, the direct current sputtering power is 80W, the flow rate of introduced argon is 30sccm, the time is 25min, and the thickness is 160nm.
And placing the prepared bottom electrode 3 in a magnetron sputtering instrument, respectively placing bismuth and tin oxide targets at the direct current sputtering target position and the radio frequency sputtering target position, sputtering simultaneously, wherein the magnetron sputtering vacuum degree is less than 5x10 < -4 > Pa, the substrate temperature is room temperature, the working pressure is 0.3Pa, the sputtering power of bismuth is 8W, the sputtering power of tin oxide is 100W, the flow rate of argon is 30sccm, the time is 1.1min, the thickness is 20nm, and the content of bismuth element is about 8.5%, so that the functional layer 4 is prepared.
Preparing an indium tin oxide top electrode 5 doped with hafnium by using a magnetron sputtering instrument, wherein an indium tin oxide target material is placed at a radio frequency sputtering target position and sputtered, the magnetron sputtering vacuum degree is less than 5x10 < -4 > Pa, the substrate temperature is room temperature, the working pressure is 0.3Pa, the sputtering power of indium tin oxide is 50W, the flow rate of introduced argon is 30sccm, the time is 40min, and the thickness is 200nm.
Example five
Low-powerThe memristor mainly comprises a silicon substrate 1, an insulating layer 2, a bottom electrode 3, a functional layer 4 and a top electrode 5, wherein the insulating layer 2 is made of silicon oxide (SiO) 2 ) The bottom electrode 3 is made of titanium nitride (TiN), and the functional layer 4 is made of bismuth doped TiN oxide (Bi: snO) 2 ) The thickness is 20nm, the material of the top electrode 5 is Indium Tin Oxide (ITO) and the thickness is 200nm.
The silicon wafer is placed in an ultrasonic instrument, and is respectively and ultrasonically treated for 15min by deionized water, acetone and absolute ethyl alcohol in sequence, so that a cleaned silicon substrate 1 is obtained.
A silicon oxide insulating layer 2 is prepared on a silicon substrate 1 by adopting a magnetron sputtering method, wherein the magnetron sputtering vacuum degree is less than 5x10 < -4 > Pa, the substrate temperature is room temperature, the working pressure is 0.3Pa, the radio frequency sputtering power is 60W, the flow rate of introduced argon is 30sccm, the time is 35min, and the thickness is 180nm.
A layer of titanium nitride bottom electrode 3 is prepared on the insulating layer 2 by adopting a magnetron sputtering method, wherein the magnetron sputtering vacuum degree is less than 5x10 < -4 > Pa, the substrate temperature is room temperature, the working pressure is 0.3Pa, the direct current sputtering power is 80W, the flow rate of introduced argon is 30sccm, the time is 25min, and the thickness is 160nm.
And (3) placing the prepared bottom electrode 3 in a magnetron sputtering instrument, respectively placing bismuth and tin oxide targets at the direct current sputtering target position and the radio frequency sputtering target position, sputtering simultaneously, wherein the magnetron sputtering vacuum degree is less than 5x10 < -4 > Pa, the substrate temperature is room temperature, the working pressure is 0.3Pa, the sputtering power of bismuth is 9W, the sputtering power of tin oxide is 100W, the flow rate of argon is 30sccm, the time is 1.2min, the thickness is 20nm, and the content of bismuth element is about 10%, so that the functional layer 4 is prepared.
Preparing an indium tin oxide top electrode 5 doped with hafnium by using a magnetron sputtering instrument, wherein an indium tin oxide target material is placed at a radio frequency sputtering target position and sputtered, the magnetron sputtering vacuum degree is less than 5x10 < -4 > Pa, the substrate temperature is room temperature, the working pressure is 0.3Pa, the sputtering power of indium tin oxide is 50W, the flow rate of introduced argon is 30sccm, the time is 40min, and the thickness is 200nm.
And (3) testing the electrical characteristics of the memristor obtained in each embodiment, wherein the testing instrument is an Agilent B1500A semiconductor parameter analyzer. The ground probe is pressed on the surface of the titanium nitride bottom electrode, and the other probe is pressed on the surface of the indium tin oxide top electrode.
For example one, a filament Forming (Forming) process first uses Agilent B1500A test software to set a scan voltage of 0V-10V, a limiting current of 1mA, and a Forming voltage of about 2V; the scanning voltage is set to be-2.0V-1.5V, current is not limited, the scanning voltage works in a cycle and is divided into four parts, namely, the scanning voltage is firstly scanned from 0V to-2.0V, then scanned from-2.0V to 0V, then scanned from 0V to +1.5V, finally scanned from +1.5V to 0V, the writing voltage is 0.7V-1.2V, and the erasing voltage is-1.0V-1.6V.
For example three, the filament formation (Forming) process first uses Agilent B1500A test software to set the scan voltage to 0V-10V, the limiting current to 1mA, and the Forming voltage to about 1.5V; the scanning voltage is set to be-1.0V, current is not limited, the scanning voltage works in a cycle and is divided into four parts, namely, the scanning voltage is firstly scanned from 0V to-1.0V, then scanned from-1.0V to 0V, then scanned from 0V to +1.0V, finally scanned from +1.0V to 0V, the writing voltage is 0.5V-0.7V, and the erasing voltage is-0.5V-0.6V.
For example five, the filament formation (Forming) process first uses Agilent B1500A test software to set the scan voltage to 0V-10V, the limiting current to 1mA, and the Forming voltage to about 2V; the scanning voltage is set to be-2.0V-1.5V, current is not limited, the scanning voltage works in a cycle and is divided into four parts, namely, the scanning voltage is firstly scanned from 0V to-2.0V, then scanned from-2.0V to 0V, then scanned from 0V to +1.5V, finally scanned from +1.5V to 0V, the writing voltage is 0.5V-1.0V, and the erasing voltage is-1.2V-1.7V.
Analysis of test results
The number of curve cycles tested was 1 cycle, the operating power of the device in the first embodiment of the present invention was about 7.4mW, the operating power of the device in the fifth embodiment was about 10.2mW, and the operating power of the device in the third embodiment was about 25. Mu.W.
By comparing 10% Bi doped SnO 2 Device and undoped SnO 2 The device is shown in FIG. 4, and it can be seen that 10% Bi is doped with SnO 2 Device and undoped SnO 2 Compared with the device, the writing voltage is increased from about 0.6V to about 1.0V, the erasing voltage is reduced from about-1.6V to about-1.25V, the operation current is basically unchanged, and the operation power is slightly increased, so that 10% is about the doping limit value.
SnO doped by comparison of 4.8% bi 2 Device and undoped SnO 2 The device, see FIG. 4, can be seen to be doped with undoped SnO 2 Compared with Bi doped SnO 2 The device (Bi content is 4.8%) has lower operation current and lower operation power, the resistance change window is kept about 10, the writing voltage is reduced from about 0.75V to about 0.6V, the erasing voltage is reduced from about-1.3V to about-0.6V, the high-resistance state current is reduced from 210A to 5.6 mu A, the low-resistance state current is reduced from 1.9mA to 56 mu A, and the operation power is reduced from 7.4mW to 25 mu W.
It can be seen that bismuth (Bi) is doped with tin oxide (SnO) 2 ) Memristive memories as functional layers have a sufficient memory window, high uniformity, low operating voltages, operating currents, and low operating powers.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (14)
1. The memristor memory comprises a silicon substrate (1), an insulating layer (2), a bottom electrode (3), a functional layer (4) and a top electrode (5) which are sequentially arranged in a layered mode, and is characterized in that: the main material of the functional layer (4) is ZnO or TiO 2 Bi is doped in the material of the functional layer (4), and the doping content of the Bi is 2.3-10%.
2. The memristive memory of claim 1, wherein: the thickness of the functional layer (4) is 10-50 nm.
3. The memristive memory of claim 1, wherein: the material of the bottom electrode (3) is one of TiN, FTO, ZTO.
4. A memristive memory as in claim 3, wherein: the bottom electrode (3) is made of TiN, and the thickness is 50-300 nm.
5. The memristive memory of claim 1, wherein: the material of the top electrode (5) is one of ITO, FTO, ZTO, tiN.
6. The memristive memory of claim 5, wherein: the top electrode (5) is made of ITO and has a thickness of 100-300 nm.
7. The memristive memory of claim 1, wherein: the thickness of the insulating layer (2) is 100-200 nm.
8. The memristive memory of claim 1, wherein: the material of the insulating layer (2) is SiO 2 。
9. The method for manufacturing a memristive memory as in claim 1, comprising the steps of:
1) Cleaning the silicon substrate (1);
2) Placing a target material serving as an insulating layer (2) on a target table, and preparing the insulating layer (2) on a silicon substrate (1) by utilizing a magnetron sputtering or atomic layer deposition method;
3) Placing a target material serving as a bottom electrode (3) on a target table, and preparing the bottom electrode (3) on the insulating layer (2) prepared in the step 2) by utilizing a magnetron sputtering or atomic layer deposition method;
4) The method comprises the steps of placing a target material serving as a main material of a functional layer (4) on a target table, placing a doped Bi target material on the target table, preparing the functional layer (4) on a bottom electrode (3) prepared in the step 2) by utilizing a magnetron sputtering or atomic layer deposition method, selecting different power ratios for the Bi target material and the target material of the main material, sputtering or depositing simultaneously, and controlling the doping content of Bi by utilizing sputtering or deposition power with different ratios;
5) And (3) placing a target material serving as a top electrode (5) on a target table, preparing the top electrode (5) on the functional layer (4) prepared in the step (4) by utilizing a magnetron sputtering or atomic layer deposition method, and obtaining the memristor after preparation.
10. The method for preparing a memristive memory according to claim 9, wherein: in the steps 2) to 5), a magnetron sputtering method is adopted.
11. The method for preparing a memristive memory according to claim 10, wherein: in the steps 2) to 5), the vacuum degree of the magnetron sputtering is less than 5 multiplied by 10 -4 Pa。
12. The method for preparing a memristive memory according to claim 10, wherein: in the steps 2) to 5), the working pressure of the magnetron sputtering is 0.1 Pa to 0.3Pa.
13. The method for preparing a memristive memory according to claim 10, wherein: the sputtering power of the step 2) is 30-100W, the sputtering power of the step 3) is 50-100W, and the sputtering power of the step 5) is 40-60W.
14. The method for preparing a memristive memory according to claim 10, wherein: the doping content of Bi in the step 4) is 2.3-10%, the sputtering power of the target material of the main material is 100W, bi, and the sputtering power of the target material is 5-9W.
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