CN110582847B - 半导体模块 - Google Patents
半导体模块 Download PDFInfo
- Publication number
- CN110582847B CN110582847B CN201880029069.3A CN201880029069A CN110582847B CN 110582847 B CN110582847 B CN 110582847B CN 201880029069 A CN201880029069 A CN 201880029069A CN 110582847 B CN110582847 B CN 110582847B
- Authority
- CN
- China
- Prior art keywords
- semiconductor
- housing
- terminal
- semiconductor module
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
- H01L23/051—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49537—Plurality of lead frames mounted in one device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04034—Bonding areas specifically adapted for strap connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/40247—Connecting the strap to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
- H01L2224/4101—Structure
- H01L2224/4103—Connectors having different sizes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
- H01L2224/4105—Shape
- H01L2224/41051—Connectors having different shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73263—Layer and strap connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Inverter Devices (AREA)
Abstract
本发明涉及一种具有至少两个半导体组件(10,20)的半导体模块(1),半导体组件在壳体之内分别设置在两个导电元件(12,14,22,24)之间并且与导电元件(12,14,22,24)导电连接。在此,导电元件(12,14,22,24)分别具有接触凸出部(12.1,14.2,22.1,24.1),所述接触凸出部从壳体引出,其中两个设置在不同的平面中的接触凸出部(12.1,24.1)在壳体之外经由接触元件(5)彼此连接,接触元件在壳体之外在两个接触凸出部(12.1,24.1)之间构成电流路径。
Description
技术领域
本发明基于根据独立权利要求1的类型的半导体模块。
背景技术
从现有技术中,已知作为集成的半桥电路(B2)实施在模塑壳体中的半导体模块,半导体模块例如构建为“无引线芯片级封装(leadlessChip-Scale-Packages)”(裸片数量级的无端子壳体)。该构型例如确定用于在电路板上构建功率电子脉冲逆变器组件。模塑壳体以导电元件的暴露的表面齐平地封闭,半桥电路利用该表面焊接到电路板上。导电元件例如能够实施为引线框。在该“无端子的”结构方式中,半桥电路的导电元件并不延伸超过模塑壳体的外边界。半桥电路包括两个晶体管,这些晶体管在壳体之内分别设置在两个传导元件之间并且与导电元件导电连接。出自半桥电路的电流流经电路板并且在那里在导电元件的暴露表面的紧邻的周围中产生高损失功率密度。半桥电路的导入电路载体中的相位电流在那里借助于分接头与相位电流线连接,相位电流线转入所连接的电机器的定子绕组中。
第一低边沿晶体管的漏极端子和第二高边沿晶体管的源极端子之间的电桥在由现有技术已知的半桥电路中建立了高边沿传导元件,高边沿传导元件一方面与高边沿晶体管的源极电极焊接并且另一方面在焊料部位处与低边沿晶体管的漏极电极焊接,所述焊料部位具有显著更小的电流横截面。在热学和热机械学方面,该焊料连接也或者键合连接由于焊料部位区域中的高局部电流和损失功率密度而是关键的;该焊料连接也或者键合连接导致因焊料部位断裂或焊料部位撕裂以及模塑脱层而使电桥失效所产生的显著的可靠性风险。
从DE 10 2009 006 152 A1中已知一种电子器件,电子器件包括***载体、第一半导体芯片、第二半导体芯片和金属芯片,它们由模塑壳体包围。第一半导体芯片利用第一表面施加在***载体上。金属芯片S形地弯曲并且将第一半导体芯片的(与第一表面相对置的)第二表面与第二半导体芯片的第一表面连接,其中第二半导体的第一表面设置在电子器件的另一平面中。第二半导体芯片的第二表面能够与第二金属芯片连接。金属芯片能够通过冲制、压印、压制、切割、锯割、铣削来制造。
发明内容
具有独立权利要求1特征的半导体模块具有的优点是:闭合壳体之外在两个半导体芯片之间的电桥。由此,通过高电流密度和温度上升引起的导电元件的接触附件中的电流收缩和与其关联的可靠性风险能够被有利地消除。根据本发明的半导体模块的实施方式能够有利地实施为半桥电路,并且设置用于构建在电子电路载体上,所述电子电路载体与电机器直接组合成“动力源”。有利地,相对应的半桥电路的相位电势分接头能够直接与电机器的定子绕组的相位电流线连接,而不引导相位电流经过电路载体,在所述电路载体上设置有半导体模块。此外,根据本发明的半导体模块的实施方式能够提供具有低电感的电桥路径,使得半桥电路有利地能够装入具有高PWM频率(PWM:脉宽调制)和微型化的无源器件的脉冲逆变器电路中。
此外,通过在壳体之外引导的电流路径有利地消除在半导体模块之内具有高损失功率密度的热量输入,并且消除随之产生的通过模塑壳体的脱层、焊料部位断裂、键合撕裂等引起的可靠性风险。所提出的半导体模块的实施方式在内部不具有电流收缩,并且因此在可靠性至少相同的情况下可在电和热学方面显著更高地负荷并且使用寿命如常规构型的类似的功率半导体模块。
半桥的半导体的电极、端子和尺寸能够有利地等大地实施,使得理论上在预设的总芯片面积和可靠的最大温度的情况下能施加最大的电流负荷。此外,相位分接头能够居中地安置在半桥的电流路径中。半桥的两个半导体组件的电层能够全等并且在电方面彼此对称地构成。
本发明的实施例提供一种具有至少两个半导体组件的半导体模块,所述半导体组件在壳体之内分别设置在两个导电元件之间并且与导电元件导电连接。在此,导电元件分别具有接触凸出部,所述接触凸出部从壳体引出。此外,两个设置在不同的平面中的接触凸出部在壳体之外经由接触元件彼此连接,所述接触元件在壳体之外在两个接触凸出部之间构成电流路径。
通过在从属权利要求中详述的措施和改进形式,可以有利地改进在独立权利要求1中说明的半导体模块。
尤其有利的是:接触元件例如能够借助于钎焊、电阻或激光熔焊、切夹式接线、拼合或压紧连接与接触凸出部连接。显然也能够使用其他适合的连接技术,以便将接触凸出部与接触元件连接并且构成相对应的电流路径。
在半导体模块的有利的设计方案中,至少两个半导体组件能够被实施为功率半导体组件,所述功率半导体组件具有相同的面积需求并且构成用于电机器的半桥电路。因此,半导体组件例如能够被实施为IGBT(绝缘栅双极晶体管)、MOSFET(金属氧化物半导体场效应晶体管,Metal-Oxide-Semiconductor Field Effect Transistor)等。
在半导体模块的另一有利的设计方案中,第一半导体的第一导电元件和第二半导体的第一导电元件能够被分别构成为漏极端子或集电极端子,并且第一半导体的第二导电元件和第二半导体的第二导电元件能够被分别构成为源极端子或发射极端子。此外,两个漏极端子或集电极端子能够以平行且对齐的棱边被设置在共同的第一平面中。两个源极端子或发射极端子能够以平行且对齐的棱边被设置在共同的第二平面中。因此,半桥的两个半导体组件的电层有利地具有等高的载流能力,并且在壳体之内具有扁平的、均匀的、有直边的轮廓,所述电层在脱层和裂纹形成方面与常规的半导体模块封装件相比相对于热机械负荷是更耐抗的。
在半导体模块的另一有利的设计方案中,在壳体之内,第一漏极端子或集电极端子能够经由接触层与第一半导体组件的相对应的漏极电极或集电极电极连接,并且第一源极端子或发射极端子能够经由接触层与第一半导体组件的相对应的源极电极或发射极电极连接,并且第一栅极端子或基极端子能够经由接触层与第一半导体组件的相对应的栅极电极或基极电极连接。此外,在壳体之内,第二漏极端子或集电极端子能够经由接触层与第二半导体组件的相对应的漏极电极或集电极电极连接,并且第二源极端子或发射极端子能够经由接触层与第二半导体组件的相对应的源极电极或发射极电极连接,并且第二栅极端子或基极端子能够经由接触层与第二半导体组件的相对应的栅极电极或基极电极连接。有利地,两个半导体组件的仅栅极端子或基极端子能够与电路板电接触,使得仅经由电路板引导功率低的操控信号。高功率电流流经设置在壳体之外的电流路径,所述电流路径通过未与电路板接触的接触凸出部和接触元件构成。
在半导体模块的另一有利的设计方案中,电机器的相位电流线的端部部段能够构成接触元件。由此,相位电流线的相同的端部部段闭合第一半导体和第二半导体之间的电桥,其中所述端部部段直接与所提出的半导体模块的相位电势分接头连接。
在半导体模块的另一有利的设计方案中,壳体能够被实施为模塑壳体。此外,两个第一导电元件的朝外的开放的表面能够分别以壳体的下侧齐平地封闭。此外,两个第二导电元件的朝外的开放的表面能够分别以壳体的上侧齐平地封闭。由此,壳体能够以有利的方式简单地以其下侧放置到电路板或热沉上。可替代地,壳体能够经由其上侧放置到电路板或热沉上。还可行的是:壳体以其下侧放置到电路板上并且附加地将热沉放置到壳体的上侧上。
附图说明
在附图中示出本发明的实施例并且在下面的描述中详细阐述。在附图中,相同的附图标记表示实施相同或类似功能的部件或元件。
图1示出Slug-Up(引线向上)构型的根据本发明的半导体模块的第一实施例的示意侧视图。
图2示出图1的根据本发明的半导体模块的实施例的示意立体俯视图。
图3示出图1和2中根据本发明的半导体模块没有壳体的实施例的示意立体俯视图。
图4示出导电元件图3中根据本发明的半导体模块没有第二导电元件的实施例的示意立体俯视图。
图5示出图1至图4中的根据本发明的半导体模块的第二半导体的第二导电元件和第一半导体的第一导电元件之间的电流路径的一个实施例的示意立体图。
图6示出图5的电流路径的另一实施例的示意图。
图7示出Slug-down(引线向下)构型的根据本发明的半导体模块的第二实施例的示意立体俯视图。
图8从下方示出图7的根据本发明的半导体模块的第二实施例的示意立体图。
具体实施方式
如从图1至8可见,根据本发明的半导体模块1的所示出的实施例分别包括至少两个半导体组件10、20,它们在壳体3之内分别设置在两个导电元件12、14、22、24之间并且与导电元件12、14、22、24导电连接。在此,导电元件12、14、22、24分别具有接触凸出部12.1、14.2、22.1、24.1,该接触凸出部从壳体3引出。此外,两个设置在不同平面中的接触凸出部12.1、24.1在壳体3之外经由接触元件5彼此连接,该接触元件在壳体3之内构成两个接触凸出部12.1、24.1之间的电流路径。
如从图1至8中进一步可见,接触元件5基本上垂直地在两个接触凸出部12.1、24.1之间伸展。接触元件5例如借助于钎焊、电阻或激光熔焊、切夹式接线、拼合或压紧连接与接触凸出部12.1、24.1连接。
如从图1至8中进一步可见,半导体模块1所示出的实施例分别构成一个电子功率模块,该电子功率模块在一件式的壳体3中包括由两个半导体组件10、20构成的可在电和热学方面高负荷的半桥电路,壳体与未示出的所连接的电机器的励磁绕组的相位电流线9直接连接。两个半导体组件10、20在所示出的实施例中被实施为具有相同面积需求的MOSFET(金属氧化物半导体场效应晶体管)。在未示出的可替代的实施例中,两个半导体组件10、20能够被实施为IGBT(绝缘栅双极晶体管)。
图3和4示出半导体模块1的内部细节,但没有示出其壳体3。如从图3和4中还可见,第一半导体10的第一导电元件12和第二半导体20的第一导电元件22被分别构成为漏极端子12A、22A。此外,第一半导体10的第二导电元件14和第二半导体20的第二导电元件24被分别构成为源极端子14A、24A。在此,两个漏极端子12A、22A以平行且对齐的棱边设置在共同的第一平面中。两个源极端子14A、24A以平行且对齐的棱边设置在共同的第二平面中。如从图3和4中进一步可见:漏极端子12A经由接触层7与第一半导体组件10的相对应的漏极电极连接。第一源极端子14A经由接触层7与第一半导体组件10的相对应的源极电极连接。第一栅极端子16经由接触层7与第一半导体组件10的相对应的栅极电极连接。此外,第二漏极端子22A经由接触层7与第二半导体组件20的相对应的漏极电极连接。第二源极端子24A经由接触层7与第二半导体组件20的相对应的源极电极连接。第二栅极端子26经由接触层7与第二半导体组件20的相对应的栅极电极连接。接触层7例如能够被构成为焊料层、导电胶层等。
第一“低边沿”桥路径的层构造“漏极端子-接触层-半导体组件-接触层-源极端子”在电方面相对于第二“高边沿”桥路径的层构造“漏极端子-接触层-半导体组件-接触层-源极端子”对称地构成。相反于常规类型、即借助于被焊接的连接器或键合线在壳体3之内闭合第一漏极端子12A和第二源极端子24A之间的电桥,提出通过相位电流线9的端部部段9.1连接第二源极端子24A的接触凸出部24.1和第一漏极端子12A的接触凸出部12.1。该连接能够借助于钎焊、电阻或激光熔焊、切夹式接线、拼合或压紧连接器来建立,因为该连接设置在构成为模塑壳体的壳体3之外。相位线部段9.2的中点构成相位电势分接头。该相位电势分接头将半桥的电流路径在电方面对称地划分成相同阻抗的“低边沿”路径和“高边沿”路径,该阻抗具有低电感以及低欧姆电阻。
如尤其从图5和6进一步可见:电机器的相位电流线9的端部部段9.1构成接触元件5。如从图6还可见,相位电流线9的端部部段7.1被实施为压入孔眼9.1A,该压入孔眼被压入到第一漏极端子12A的接触凸出部12.1中的和第二源极端子24A的接触凸出部24.1中的相应的接触开口12.2、24.2中。
如从图1和2进一步可见,在半导体模块1的引线向上构型中,壳体3的上侧3.1以两个平行且对齐设置的源极端子14A、24A的外部的开放的表面齐平地封闭,这些表面能够经由能导热的、电分离的中间介质与未详细示出的热沉连接。壳体3的下侧3.2仅由壳体3的模塑料形成。壳体3的下侧3.2在电方面是无电势的并且在技术方面能够有利地借助于在使用寿命上运行稳定的、持久弹性的粘胶与未详细示出的电路载体连接。电路载体例如能够被实施为多层的电路板。电路载体和半导体模块1的壳体3因此尽管热膨胀系数不同但是也能够以无裂纹和脱层的方式发生热机械膨胀。仅栅极端子16、26的接触凸出部16.1、26.1与电路载体电连接。然而,高电流仅流过半导体模块1的接触凸出部12.1、24.1和相位电流线9,并且不流过电路载体。因此,半导体模块1的在电方面的流动场中的欧姆损失功率主要流过漏极端子14A、24A的开放的表面流出到热沉中。电路载体和设置在其上的环绕的器件在热学和热机械方面仅有少量的负荷。
如从图7和8进一步可见:在半导体模块1的引线向下构型中,壳体3的下侧3.2以两个平行且对齐设置的漏极端子12A、22A的外部的开放的表面齐平地封闭。漏极端子12A、22A的两个外部的开放的表面中的一个能够与电路载体上的焊料面焊接,使得高边沿电流或低边沿电流能够流经电路载体。此外,漏极端子12A、22A的两个开放的表面中的一个能够经由塑性导热且电绝缘的中间介质与电路载体中的矩形周期性或六边形布置的热金属化通孔(“thermal vias”)连接,热金属化通孔能够将半导体模块1的热流引入到未示出的热沉中。壳体3的上侧3.1仅由壳体3的模塑料形成。
Claims (15)
1.一种具有至少两个半导体组件(10,20)的半导体模块(1),所述半导体组件在壳体(3)之内分别设置在两个导电元件(12,14,22,24)之间并且与所述导电元件(12,14,22,24)导电连接,其特征在于,所述导电元件(12,14,22,24)分别具有接触凸出部(12.1,14.2,22.1,24.1),所述接触凸出部从所述壳体(3)引出,其中在所述壳体(3)之外,两个设置在不同的平面中的接触凸出部(12.1,24.1)被接触元件(5)依次延伸穿过并且彼此连接,所述接触元件在所述壳体(3)之外在两个所述接触凸出部(12.1,24.1)之间构成电流路径。
2.根据权利要求1所述的半导体模块(1),其特征在于,所述接触元件(5)借助于钎焊、电阻或激光熔焊、切夹式接线、拼合或压紧连接与所述接触凸出部(12.1,24.1)连接。
3.根据权利要求1或2所述的半导体模块(1),其特征在于,所述至少两个半导体组件(10,20)被实施为功率半导体组件,所述功率半导体组件具有相同的面积需求并且构成用于电机器的半桥电路。
4.根据权利要求1至3中任一项所述的半导体模块(1),其特征在于,第一半导体组件(10)的第一导电元件(12)和第二半导体组件(20)的第一导电元件(22)被分别构成为漏极端子(12A,22A)或集电极端子,并且所述第一半导体组件(10)的第二导电元件(14)和所述第二半导体组件(20)的第二导电元件(24)被分别构成为源极端子(14A,24A)或发射极端子。
5.根据权利要求4所述的半导体模块(1),其特征在于,两个所述漏极端子(12A,22A)或集电极端子以平行且对齐的棱边被设置在共同的第一平面中。
6.根据权利要求4或5所述的半导体模块(1),其特征在于,两个所述源极端子(14A,24A)或发射极端子以平行且对齐的棱边被设置在共同的第二平面中。
7.根据权利要求4至6中任一项所述的半导体模块(1),其特征在于,在所述壳体(3)之内,第一漏极端子(12A)或集电极端子经由接触层(7)与所述第一半导体组件(10)的相对应的漏极电极或集电极电极连接,并且第一源极端子(14A)或发射极端子经由接触层(7)与所述第一半导体组件(10)的相对应的源极电极或发射极电极连接,并且第一栅极端子(16)或基极端子经由接触层(7)与所述第一半导体组件(10)的相对应的栅极电极或基极电极连接。
8.根据权利要求4至7中任一项所述的半导体模块(1),其特征在于,在所述壳体(3)之内,第二漏极端子(22A)或集电极端子经由接触层(7)与所述第二半导体组件(20)的相对应的漏极电极或集电极电极连接,并且第二源极端子(24A)或发射极端子经由接触层(7)与所述第二半导体组件(20)的相对应的源极电极或发射极电极连接,并且第二栅极端子(26)或基极端子经由接触层(7)与所述第二半导体组件(20)的相对应的栅极电极或基极电极连接。
9.根据权利要求7或8所述的半导体模块(1),其特征在于,两个所述半导体组件(10,20)的仅所述栅极端子(16,26)或基极端子与电路板电接触。
10.根据权利要求1至9中任一项所述的半导体模块(1),其特征在于,电机器的相位电流线(9)的端部部段(9.1)构成所述接触元件(5)。
11.根据权利要求1至10中任一项所述的半导体模块(1),其特征在于,所述壳体(3)被实施为模塑壳体。
12.根据权利要求1至11中任一项所述的半导体模块(1),其特征在于,两个第一导电元件(12,22)的朝外开放的表面分别以所述壳体(3)的下侧(3.2)齐平地封闭。
13.根据权利要求1至12中任一项所述的半导体模块(1),其特征在于,两个第二导电元件(14,24)的朝外开放的表面分别以所述壳体(3)的上侧(3.2)齐平地封闭。
14.根据权利要求12或13所述的半导体模块(1),其特征在于,所述壳体(3)以所述壳体的下侧(3.2)放置到电路板或热沉上。
15.根据权利要求12至14中任一项所述的半导体模块(1),其特征在于,所述壳体(3)经由所述壳体的上侧(3.1)放置到电路板或热沉上。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102017207564.3A DE102017207564A1 (de) | 2017-05-05 | 2017-05-05 | Halbleitermodul |
DE102017207564.3 | 2017-05-05 | ||
PCT/EP2018/060603 WO2018202509A1 (de) | 2017-05-05 | 2018-04-25 | Halbleitermodul |
Publications (2)
Publication Number | Publication Date |
---|---|
CN110582847A CN110582847A (zh) | 2019-12-17 |
CN110582847B true CN110582847B (zh) | 2023-04-11 |
Family
ID=62063066
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201880029069.3A Active CN110582847B (zh) | 2017-05-05 | 2018-04-25 | 半导体模块 |
Country Status (6)
Country | Link |
---|---|
US (1) | US11037867B2 (zh) |
EP (1) | EP3619739B1 (zh) |
JP (1) | JP7055151B2 (zh) |
CN (1) | CN110582847B (zh) |
DE (1) | DE102017207564A1 (zh) |
WO (1) | WO2018202509A1 (zh) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3545550B1 (en) * | 2016-11-23 | 2021-02-17 | ABB Schweiz AG | Manufacturing of a power semiconductor module |
EP3690939A1 (en) | 2019-01-30 | 2020-08-05 | Infineon Technologies AG | Semiconductor arrangements |
DE102020101288A1 (de) | 2020-01-21 | 2021-07-22 | Hanon Systems | Halbbrücke in einem Inverter und Verfahren zur Reduzierung parasitärer Induktivitäten in einer Halbbrücke eines Inverters |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1901187A (zh) * | 2005-07-22 | 2007-01-24 | 株式会社电装 | 半导体器件 |
JP2013101993A (ja) * | 2011-11-07 | 2013-05-23 | Denso Corp | 半導体装置 |
CN103199069A (zh) * | 2011-12-08 | 2013-07-10 | 英飞凌科技股份有限公司 | 包含两个功率半导体芯片的器件及其制造 |
WO2014206693A1 (de) * | 2013-06-26 | 2014-12-31 | Robert Bosch Gmbh | Elektrische schaltungsanordnung |
CN104332463A (zh) * | 2013-07-12 | 2015-02-04 | 英飞凌科技奥地利有限公司 | 多芯片器件 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8642394B2 (en) | 2008-01-28 | 2014-02-04 | Infineon Technologies Ag | Method of manufacturing electronic device on leadframe |
US8138587B2 (en) * | 2008-09-30 | 2012-03-20 | Infineon Technologies Ag | Device including two mounting surfaces |
JP2011086889A (ja) * | 2009-10-19 | 2011-04-28 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
US8987777B2 (en) * | 2011-07-11 | 2015-03-24 | International Rectifier Corporation | Stacked half-bridge power module |
US9054091B2 (en) | 2013-06-10 | 2015-06-09 | Alpha & Omega Semiconductor, Inc. | Hybrid packaged lead frame based multi-chip semiconductor device with multiple semiconductor chips and multiple interconnecting structures |
-
2017
- 2017-05-05 DE DE102017207564.3A patent/DE102017207564A1/de not_active Withdrawn
-
2018
- 2018-04-25 JP JP2019560312A patent/JP7055151B2/ja active Active
- 2018-04-25 US US16/610,947 patent/US11037867B2/en active Active
- 2018-04-25 WO PCT/EP2018/060603 patent/WO2018202509A1/de active Application Filing
- 2018-04-25 EP EP18720237.9A patent/EP3619739B1/de active Active
- 2018-04-25 CN CN201880029069.3A patent/CN110582847B/zh active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1901187A (zh) * | 2005-07-22 | 2007-01-24 | 株式会社电装 | 半导体器件 |
JP2013101993A (ja) * | 2011-11-07 | 2013-05-23 | Denso Corp | 半導体装置 |
CN103199069A (zh) * | 2011-12-08 | 2013-07-10 | 英飞凌科技股份有限公司 | 包含两个功率半导体芯片的器件及其制造 |
WO2014206693A1 (de) * | 2013-06-26 | 2014-12-31 | Robert Bosch Gmbh | Elektrische schaltungsanordnung |
CN104332463A (zh) * | 2013-07-12 | 2015-02-04 | 英飞凌科技奥地利有限公司 | 多芯片器件 |
Also Published As
Publication number | Publication date |
---|---|
DE102017207564A1 (de) | 2018-11-08 |
WO2018202509A1 (de) | 2018-11-08 |
EP3619739B1 (de) | 2021-04-14 |
US11037867B2 (en) | 2021-06-15 |
JP2020519027A (ja) | 2020-06-25 |
CN110582847A (zh) | 2019-12-17 |
US20200058575A1 (en) | 2020-02-20 |
JP7055151B2 (ja) | 2022-04-15 |
EP3619739A1 (de) | 2020-03-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6764807B2 (ja) | 半導体モジュール | |
US7298027B2 (en) | SMT three phase inverter package and lead frame | |
US8981553B2 (en) | Power semiconductor module with integrated thick-film printed circuit board | |
JP6354845B2 (ja) | 半導体モジュール | |
US7494389B1 (en) | Press-fit-connection | |
US8198712B2 (en) | Hermetically sealed semiconductor device module | |
US7592688B2 (en) | Semiconductor package | |
US11596077B2 (en) | Method for producing a semiconductor module arrangement | |
CN110582847B (zh) | 半导体模块 | |
EP2871676A1 (en) | Semiconductor device | |
US6646884B1 (en) | Sandwich-structured intelligent power module | |
JP2016184992A (ja) | 回路構成体 | |
US10028384B2 (en) | Circuit board assembly, control device for a cooler fan module and method | |
CN115117011A (zh) | 功率半导体模块和生产功率半导体模块的方法 | |
US10290568B2 (en) | Power module for an electric motor | |
US20190214340A1 (en) | Power module | |
CN109716877B (zh) | 电子组件 | |
US20220287209A1 (en) | Power electronics module and method for fabricating a power electronics module | |
CN115692210A (zh) | 具有按压配合触点的功率模块 | |
US10755999B2 (en) | Multi-package top-side-cooling | |
EP4270477A2 (en) | Power module and method for manufacturing a power module | |
CN115799208A (zh) | 功率半导体模块 | |
CN115472585A (zh) | 功率半导体模块 | |
CN115692339A (zh) | 功率模块 | |
CN114556554A (zh) | 基板、封装结构及电子设备 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |