CN110579937B - Test mask and forming method thereof, and forming device of test mask - Google Patents
Test mask and forming method thereof, and forming device of test mask Download PDFInfo
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- CN110579937B CN110579937B CN201910898773.9A CN201910898773A CN110579937B CN 110579937 B CN110579937 B CN 110579937B CN 201910898773 A CN201910898773 A CN 201910898773A CN 110579937 B CN110579937 B CN 110579937B
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
- G03F1/44—Testing or measuring features, e.g. grid patterns, focus monitors, sawtooth scales or notched scales
Abstract
The invention relates to a test mask and a forming method thereof, and a forming device of the test mask. The forming method of the test mask comprises the following steps: forming an initial layout with a plurality of test patterns, wherein a first gap is formed between every two adjacent test patterns; acquiring the graph density distribution in the corresponding product mask; adding a plurality of redundant graphs into the first gap of the initial graph to form a graph, wherein the difference value between the graph density distribution in the graph and the graph density distribution in the product mask is within a preset range; and generating a test mask according to the layout. The invention reduces or even eliminates the adverse effect of the etching load effect on the key sizes of different positions of the test mask plate in the preparation process, and improves the pattern size precision of the test mask plate. The OPC correction model is established by using the test mask produced by the invention, so that the model precision and the correction effect of the corresponding product mask are improved, and the photoetching quality is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a test mask and a forming method thereof, and a forming device of the test mask.
Background
In a semiconductor manufacturing process, due to the diffraction Effect of ultraviolet light, when a pattern on a reticle is projected onto a wafer, the pattern formed on the surface of the wafer is often distorted, which results in a reduction in the final image quality, and this phenomenon is called Optical Proximity Effect (OPE). The pattern on the reticle is modified appropriately to compensate for the defects caused by Optical Proximity effects, so as to obtain the same pattern on the wafer surface as the original reticle design, which is called Optical Proximity Correction (OPC). However, the existing OPC correction effect is closely related to the quality information of the test mask, and the accuracy of an OPC model and the photoetching quality of a final product are influenced by the larger pattern distribution and size accuracy of the test mask.
Therefore, how to improve the dimensional accuracy of the pattern on the test mask, and further improve the accuracy of the OPC model, and finally achieve the improvement of the lithography quality is a technical problem to be solved at present.
Disclosure of Invention
The invention provides a test mask and a forming method thereof, and a forming device of the test mask, which are used for solving the problem of low dimensional precision of a pattern on the conventional test mask so as to improve OPC (optical proximity correction) correction effect and improve photoetching quality.
In order to solve the above problems, the present invention provides a method for forming a test mask, comprising the steps of:
forming an initial layout with a plurality of test patterns, wherein a first gap is formed between every two adjacent test patterns;
acquiring the graph density distribution in the corresponding product mask plate;
adding a plurality of redundant graphs into the first gap of the initial graph to form a graph, wherein the difference value between the graph density distribution in the graph and the graph density distribution in the product mask is within a preset range;
and generating a test mask according to the layout.
Optionally, the method further includes the following steps before the initial layout is formed:
providing a plurality of different types of base graphics, any two types of said base graphics differing in shape and/or size;
forming a plurality of different types of test patterns, wherein each type of test pattern is formed by arranging at least two types of basic patterns, and the types and/or arrangement modes of the basic patterns in any two types of test patterns are different.
Optionally, the specific step of forming the initial layout with the plurality of test patterns includes:
and selecting at least two types of test pattern arrangements to form the initial layout.
Optionally, the specific step of forming the layout includes:
acquiring the graph density distribution in the initial layout;
adding a plurality of redundant graphs into the first gap of the initial layout, wherein the size of the redundant graphs and/or the spacing width between the adjacent redundant graphs are determined according to the graph density distribution of the product mask and the graph density distribution in the initial layout.
Optionally, a second gap is formed between two adjacent basic patterns inside each test pattern; the step of forming the layout further comprises:
adding a plurality of redundant patterns to the second gap of the initial layout.
Optionally, the plurality of redundant patterns filled in the first gap and the second gap are all arranged in an array.
Optionally, the redundant graph is rectangular.
In order to solve the above problem, the present invention further provides a test mask, comprising:
a plurality of test patterns, wherein a first gap is formed between every two adjacent test patterns;
and the redundant patterns are positioned in the first gap, so that the difference value between the pattern density distribution of the test mask and the pattern density distribution in the corresponding product mask is within a preset range.
Optionally, each of the test patterns is formed by arranging at least two types of basic patterns, and the shapes and/or sizes of any two types of the basic patterns are different;
the test patterns at least belong to two different types of test patterns, and the different types of test patterns refer to different types and/or different arrangement modes of the basic patterns forming the test patterns.
Optionally, a second gap is formed between two adjacent basic patterns inside each test pattern;
and a plurality of redundant patterns are filled in the second gap.
Optionally, the plurality of redundant patterns filled in the first gap and the second gap are all arranged in an array.
Optionally, the redundant graph is rectangular.
In order to solve the above problem, the present invention further provides a test mask forming apparatus, including:
the processing module is used for forming an initial layout with a plurality of test patterns, and a first gap is formed between every two adjacent test patterns;
the acquisition module is used for acquiring the graph density distribution in the corresponding product mask;
the adding module is used for adding a plurality of redundant graphs into the first gap of the initial layout to form a layout, and the difference value between the graph density distribution in the layout and the graph density distribution in the product mask is within a preset range;
and the generating module is used for generating the test mask plate by the layout.
Optionally, the method further includes:
the storage module is used for storing a plurality of different types of test patterns, each type of test pattern is formed by arranging at least two types of basic patterns, the types and/or the arrangement modes of the basic patterns in any two types of test patterns are different, and the shapes and/or the sizes of any two types of basic patterns are different.
Optionally, the processing module is configured to select at least two types of test pattern arrangements to form the initial layout.
Optionally, the adding module includes:
the obtaining unit is used for obtaining the graph density distribution in the initial layout;
and the adding unit is used for adding a plurality of redundant graphs into the first gap of the initial layout, and the size of the redundant graphs and/or the spacing width between the adjacent redundant graphs are determined according to the graph density distribution of the product mask and the graph density distribution in the initial layout.
Optionally, a second gap is formed between two adjacent basic patterns inside each test pattern;
the adding unit is further configured to add a plurality of redundant patterns to the second gap of the initial layout.
Optionally, the plurality of redundant patterns filled in the first gap and the second gap are all arranged in an array.
Optionally, the redundant graph is rectangular.
According to the test mask and the forming method thereof and the forming device of the test mask, the redundant graph is arranged in the interval area between the test graphs, so that the graph density distribution in the finally generated test mask is equivalent to the graph density distribution on the product mask, for example, the difference value is within a preset range, the adverse effect of the test mask on the key sizes of different positions of the test mask due to the etching load effect in the preparation process is reduced or even eliminated, the graph size precision of the test mask is improved, the deviation of the constructed OPC correction model due to the difference of loading environments is avoided, the OPC correction effect is ensured, the photoetching quality is improved, and the yield of the final semiconductor product is improved.
Drawings
FIG. 1 is a flow chart of a method for forming a test mask in accordance with an embodiment of the present invention;
FIG. 2 is a schematic illustration of a plurality of different types of base graphics in an embodiment of the present invention;
FIG. 3 is a schematic diagram of a test pattern formed from a base pattern in an embodiment of the present invention;
fig. 4A and 4B are schematic diagrams of filling the redundant graph in the initial layout in the embodiment of the present invention;
FIG. 5 is a graph density distribution plot in a layout in an embodiment of the present invention;
FIG. 6 is a block diagram of an apparatus for testing reticle formation in accordance with an embodiment of the present invention.
Detailed Description
The following describes in detail embodiments of a test mask, a method for forming the same, and an apparatus for forming the test mask according to the present invention with reference to the accompanying drawings.
The process for generating the OPC test mask mainly comprises the following steps: firstly, generating a plurality of GDS (Graphic Data Stream) files, wherein each GDS file comprises one type of OPC (optical proximity correction) test pattern; then, a plurality of GDS files are arranged in the effective exposure area of the mask according to requirements, and JDV (Job Deck View, photomask data detection) files are generated and output. However, after arranging several GDS files, there are a lot of Blank areas (Blank areas) between adjacent GDS files, and there is no current process for these Blank areas, which easily causes the following two problems:
on one hand, the feature size (CD) of the pattern formed in the test mask in different Loading environments (Loading Environment) of the same pattern and the feature size of the pattern formed on the product mask in the actual process have a larger difference;
on the other hand, in the developing process, the feature sizes formed on the wafer surface have a certain deviation in the same pattern in different pattern density regions.
That is, the pattern density distribution in the test mask is different from the pattern density distribution on the product mask, so that the same pattern has different characteristic sizes in the test mask and the product mask, the OPC correction effect is affected, and the lithography quality is reduced.
In order to reduce the difference between the loading environment of the test mask and the product mask and improve the OPC correction effect, the embodiment provides a method for forming the test mask, wherein FIG. 1 is a flow chart of the method for forming the test mask in the embodiment of the invention, FIG. 2 is a schematic diagram of various different types of basic patterns in the embodiment of the invention, FIG. 3 is a schematic diagram of a test pattern formed by the basic patterns in the embodiment of the invention, and FIGS. 4A and 4B are schematic diagrams of filling redundant patterns in an initial layout in the embodiment of the invention. As shown in fig. 1 to 3, 4A, and 4B, the method for forming a test reticle according to this embodiment includes the following steps:
step S11, an initial layout having a plurality of test patterns is formed, with a first gap 41 between adjacent test patterns.
Optionally, before forming the initial layout, the following steps are further included:
providing a plurality of different types of base graphics, any two types of said base graphics differing in shape and/or size;
forming a plurality of different types of test patterns, wherein each type of test pattern is formed by arranging at least two types of basic patterns, and the types and/or arrangement modes of the basic patterns in any two types of test patterns are different.
Optionally, the specific step of forming the initial layout with the plurality of test patterns includes:
and selecting at least two types of test pattern arrangements to form the initial layout.
The basic pattern, the test pattern, and the initial layout in this embodiment are all stored in GDS format files. The GDS is a file format generated after the layout design of the integrated circuit, is a binary file including the layout of the integrated circuit, and is an accepted semiconductor physical pattern storage format in the industry.
The plurality of different types of base graphics may comprise polygons (e.g. rectangles) of different sizes or different extension directions. In fig. 2, N different types of test patterns are shown, for example, a first test pattern GDS-1, a second test pattern GDS-2, a third test pattern GDS-3, \8230 \ 8230;, an nth test pattern GDS-N, the first test pattern GDS-1 may be a one-dimensional linear/Space (Line/Space) pattern, the second test pattern GDS-2 may be a two-dimensional Line end (Line-end) pattern, the third test pattern GDS-3 may be a pattern With a sub-resolution auxiliary pattern (With S-bar), and the nth test pattern GDS-N may be a dot (Hot spots) pattern. The skilled person can select or set the type of test pattern according to actual needs.
After forming a plurality of types of test patterns, forming the initial layout through the arrangement of the plurality of types of test patterns. Specifically, according to the actual needs of integrated circuit manufacturing, several types of test patterns are selected, and after being processed in a copying, rotating, turning and other manners, the test patterns are arranged in the effective exposure area of the pre-formed test reticle, as shown in fig. 3. The width W of the effective exposure area in FIG. 3 is 26000 μm, and the length L is 33000 μm. Wherein, in the process of arranging the test patterns in the effective exposure area, the interval width D between the edge of the test pattern and the edge of the effective exposure area is more than 20 μm.
FIG. 4A is a structure of an initial layout formed in an embodiment of the present invention. As shown in fig. 4A, the initial layout is formed by arranging a plurality of test patterns, for example, a first test pattern GDS-1, a second test pattern GDS-2, a third test pattern GDS-3, and an nth test pattern GDS-N, after being processed by copying, rotating, flipping, etc., that is, the number of each type of test pattern in the initial layout may be one or more than two, and those skilled in the art may arrange the test patterns according to actual design requirements.
And S12, acquiring the pattern density distribution in the product mask.
The product mask is a mask which covers the surface of a product wafer in a semiconductor manufacturing process and transfers a pattern to the surface of the product wafer through exposure and development operations. The pattern density in the product mask plate is the percentage of the calculated light transmission area in the whole set pattern area within a set pattern area. The graph density distribution in the product mask refers to that after a plurality of existing graph densities are detected and divided into a plurality of density intervals, the percentage of the area of a graph region in the product mask corresponding to each density interval to the area of an effective exposure region of the whole product mask is obtained.
And S13, adding a plurality of redundant patterns 42 into the first gap 41 of the initial layout to form a layout, wherein the difference value between the pattern density distribution in the layout and the pattern density distribution in the product mask is within a preset range.
The graph density in the layout refers to the percentage of the calculated area of the light-transmitting area in the area of the whole set graph area within the range of the set graph area. The graph density distribution in the layout refers to that after a plurality of existing graph densities are checked and divided into a plurality of density intervals, the percentage of the area of a graph region in the layout corresponding to each density interval to the area of an effective exposure area of the whole test mask is obtained. The density interval division in the layout is the same as the density interval division in the corresponding product mask so as to facilitate comparison. The difference value between the graph density distribution in the layout and the graph density distribution in the product mask is within a preset range, namely, for each density interval, the difference value between the area ratio of the area of the graph region in the layout in the effective exposure area of the whole test mask and the area ratio of the area of the graph region in the product mask in the effective exposure area of the whole test mask is within a preset range.
Optionally, the specific step of forming the layout includes:
acquiring the graph density distribution in the initial layout;
adding a plurality of redundant patterns 42 into the first gap 41 of the initial layout, wherein the size of the redundant patterns 41 and/or the spacing width between the adjacent redundant patterns 41 are determined according to the pattern density distribution of the product mask and the pattern density distribution in the initial layout.
Fig. 4B is a structure of the layout formed after the first gap 41 in the initial layout shown in fig. 4A is filled with the redundant pattern 42. The specific structure of the redundant pattern 42 may be any polygon, circle, or ellipse, and in order to further simplify the formation process of the test mask, optionally, the redundant pattern 42 is rectangular.
Similar to the product mask, the graph density in the initial graph refers to the percentage of the calculated light transmission area in the whole set graph area within a set graph area. The graph density distribution in the initial layout refers to the percentage of the area of a graph region in the test mask corresponding to each density interval to the area of an effective exposure region of the whole test mask after the existing multiple graph densities are detected and divided into multiple density intervals. And calculating the size of the redundant patterns 42 and/or the gap between the adjacent redundant patterns 42 filled in the first gap 41 according to the pattern density distribution in the product mask and the pattern density distribution in the initial layout. For example, when the difference between the pattern area ratio in a certain density interval in the product mask and the pattern area ratio in the same density interval in the initial layout is large, the gap between adjacent redundant patterns 23 may be correspondingly reduced and/or the size of the redundant pattern 23 may be increased according to the specific value range of the density interval. Thus, by filling the first gap 41, the difference between the loading environment of the test mask and the loading environment of the product mask is reduced, and the problem of large deviation when the pattern is loaded into the product mask is reduced or even avoided. The specific numerical value of the preset range can be set by a person skilled in the art according to actual needs, for example, the requirement of the lithography precision, and this embodiment does not limit this.
FIG. 5 is a graph density profile in a layout in an embodiment of the present invention. As shown in fig. 5, after the dummy pattern 41 is filled, the pattern area having a density of 0.019 to 0.18 occupies 38.93% of the area, and the pattern area having a density of 0.18 to 0.27 occupies 40.37% of the area. After the redundant graph is filled, the density of 79.3% of the graph area is between 0.019 and 0.27, the uniformity of density distribution in the layout is greatly improved, the environment where the test graph is located in the OPC correction process is close to or the same as the environment where the graph in the product mask is located, and the reliability and the accuracy of subsequent OPC correction are ensured.
Optionally, a second gap is formed between two adjacent basic patterns inside each test pattern; the step of forming the layout further comprises:
adding a plurality of redundant patterns 42 to the second gap of the initial layout.
For example, as shown in fig. 2, the second gap includes a gap 201 between two adjacent vertical bar-shaped base patterns within the first test pattern GDS-1, a gap 202 between two adjacent horizontal bar-shaped base patterns within the second test pattern GDS-2, a gap 203 between two adjacent polygonal-shaped base patterns within the nth base pattern GDS-N, and the like. The redundant pattern 42 can be filled into the second gap while the redundant pattern 42 is filled into the first gap 41, so that the uniformity of the pattern density of each region in the formed layout is further ensured, and the difference between the pattern density distribution in the layout and the pattern density distribution in the product mask is further reduced.
Optionally, the redundant patterns filled in the first gap 41 and the second gap are all arranged in an array.
In order to further simplify the formation process of the test mask, the size of the redundant patterns in the first gap 41 and the second gap and the space width between adjacent redundant patterns are the same.
And S14, generating a test mask according to the layout.
Specifically, after the redundant graph is filled and the layout in the GDS file format is formed, a corresponding JDV file is generated and output to form the final test mask. And the difference value between the graph density distribution in the layout and the graph density distribution in the product mask is within a preset range, so that the difference of loading environments between the test mask and the product mask can be effectively reduced or even avoided.
Furthermore, the present embodiment also provides a test mask, and the test mask of the present embodiment may be formed by the method shown in fig. 1 to 3, 4A, and 4B. As shown in fig. 1 to 3, 4A, and 4B, the test reticle formed in the present embodiment includes:
a plurality of test patterns having a first gap 41 between adjacent test patterns;
and the redundant patterns 42 are positioned in the first gap 41, so that the difference value between the pattern density distribution of the test mask and the pattern density distribution in the corresponding product mask is within a preset range.
Optionally, each of the test patterns is formed by arranging at least two types of basic patterns, and the shapes and/or sizes of any two types of basic patterns are different;
the plurality of test patterns belong to at least two different types of test patterns, and the different types of test patterns refer to different types and/or different arrangement modes of the basic patterns forming the test patterns.
Optionally, a second gap is formed between two adjacent basic patterns inside each test pattern;
and a plurality of redundant graphs are filled in the second gap.
Optionally, the plurality of redundant patterns 42 filled in the first gap 41 and the second gap are arranged in an array.
Optionally, the redundant pattern 42 is rectangular.
Moreover, the present embodiment further provides a device for forming a test mask, and fig. 6 is a block diagram of the device for forming a test mask according to the present embodiment. Fig. 1 to 3, 4A, and 4B show a control method of a test reticle forming apparatus according to this embodiment. As shown in fig. 1 to 3, 4A, 4B, and 5, the apparatus for forming a test reticle according to the present embodiment includes:
a processing module 51 for forming an initial layout having a plurality of test patterns with a first gap 41 between adjacent test patterns;
an obtaining module 52, configured to obtain a pattern density distribution in a corresponding product mask;
an adding module 53, configured to add a plurality of redundant patterns 42 to the first gap of the initial layout to form a layout, where a difference between a pattern density distribution in the layout and a pattern density distribution in the product mask is within a preset range;
and a generating module 54 for generating a test mask for the layout.
Optionally, the apparatus for forming a test reticle further includes:
the storage module 50 is configured to store a plurality of different types of test patterns, each type of test pattern is formed by arranging at least two types of basic patterns, the types and/or arrangement modes of the basic patterns in any two types of test patterns are different, and the shapes and/or sizes of any two types of basic patterns are different.
Optionally, the processing module 51 is configured to select at least two types of test pattern arrangements to form the initial layout.
Optionally, the adding module 53 includes:
an obtaining unit 531, configured to obtain a graph density distribution in the initial layout;
an adding unit 532, configured to add a plurality of redundant patterns 42 to the first gap 41 in the initial layout, where the size of the redundant patterns 42 and/or the width of the space between adjacent redundant patterns 42 are determined according to the pattern density distribution of the product reticle and the pattern density distribution in the initial layout.
Optionally, a second gap is formed between two adjacent basic patterns inside each test pattern;
the adding unit is further configured to add a plurality of redundant patterns 42 to the second gap of the initial layout.
Optionally, the plurality of redundant patterns 42 filled in the first gap and the second gap are all arranged in an array.
Optionally, the redundant pattern 42 is rectangular.
In the test mask and the forming method thereof and the forming device thereof provided by the embodiment of the invention, the redundant patterns are arranged in the interval regions between the test patterns, so that the pattern density distribution in the finally generated test mask is equivalent to the pattern density distribution on the product mask, for example, the difference value is within a preset range, the adverse effect of the test mask on the key sizes of different positions of the test mask due to the etching load effect in the preparation process is reduced or even eliminated, the pattern size precision of the test mask is improved, the deviation of the constructed OPC correction model due to the difference of loading environments is avoided, the OPC correction effect is ensured, the photoetching quality is improved, and the yield of the final semiconductor product is improved.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (19)
1. A method for forming a test mask is characterized by comprising the following steps:
forming an initial layout with a plurality of test patterns, wherein a first gap is formed between every two adjacent test patterns;
acquiring the graph density distribution in the corresponding product mask;
adding a plurality of redundant graphs into the first gap of the initial graph to form a graph, wherein the difference value between the graph density distribution in the graph and the graph density distribution in the product mask is within a preset range;
and generating a test mask according to the layout.
2. The method for forming a test reticle according to claim 1, further comprising, before forming the initial layout, the steps of:
providing a plurality of different types of base graphics, any two types of said base graphics differing in shape and/or size;
forming a plurality of different types of test patterns, wherein each type of test pattern is formed by arranging at least two types of basic patterns, and the types and/or arrangement modes of the basic patterns in any two types of test patterns are different.
3. The method of forming a test reticle according to claim 2, wherein the step of forming the initial layout having the plurality of test patterns comprises:
and selecting at least two types of test pattern arrangements to form the initial layout.
4. The method for forming a test reticle according to claim 2, wherein the step of forming the layout comprises:
acquiring the graph density distribution in the initial layout;
adding a plurality of redundant graphs into the first gap of the initial layout, wherein the size of the redundant graphs and/or the spacing width between the adjacent redundant graphs are determined according to the graph density distribution of the product mask and the graph density distribution in the initial layout.
5. The method for forming a test reticle according to claim 4, wherein a second gap is provided between two adjacent base patterns inside each of the test patterns; the step of forming the layout further comprises:
adding a plurality of redundant patterns to the second gap of the initial layout.
6. The method for forming a test reticle according to claim 5, wherein the plurality of redundant patterns filled in the first gap and the second gap are arranged in an array.
7. The method of forming a test reticle according to claim 1, wherein the redundant pattern is rectangular.
8. A test reticle, comprising:
a plurality of test patterns, wherein a first gap is formed between every two adjacent test patterns;
and the redundant patterns are positioned in the first gap, so that the difference value between the pattern density distribution of the test mask and the pattern density distribution in the corresponding product mask is within a preset range.
9. The test reticle defined in claim 8 wherein each of the test patterns is formed by arranging at least two types of base patterns, any two types of the base patterns being different in shape and/or size;
the test patterns at least belong to two different types of test patterns, and the different types of test patterns refer to different types and/or different arrangement modes of the basic patterns forming the test patterns.
10. The test reticle defined in claim 9 wherein adjacent two of the base patterns within each of the test patterns have a second gap therebetween;
the second gap is filled with a plurality of the redundant patterns.
11. The test reticle of claim 10, wherein the plurality of redundant patterns filled in the first and second gaps are arranged in an array.
12. The test reticle of claim 8, wherein the redundancy pattern is rectangular.
13. An apparatus for forming a test reticle, comprising:
the processing module is used for forming an initial layout with a plurality of test patterns, and a first gap is formed between every two adjacent test patterns;
the acquisition module is used for acquiring the graph density distribution in the corresponding product mask;
the adding module is used for adding a plurality of redundant graphs into the first gap of the initial layout to form a layout, and the difference value between the graph density distribution in the layout and the graph density distribution in the product mask is within a preset range;
and the generating module is used for generating the test mask by the layout.
14. The formation apparatus of a test reticle according to claim 13, further comprising:
the storage module is used for storing a plurality of different types of test patterns, each type of test pattern is formed by arranging at least two types of basic patterns, the types and/or the arrangement modes of the basic patterns in any two types of test patterns are different, and the shapes and/or the sizes of any two types of basic patterns are different.
15. The formation apparatus of a test reticle as claimed in claim 14, wherein the processing module is configured to select at least two types of test pattern arrangements to form the initial layout.
16. The test reticle forming apparatus of claim 14, wherein the add-on module comprises:
the acquisition unit is used for acquiring the graph density distribution in the initial layout;
and the adding unit is used for adding a plurality of redundant graphs into the first gap of the initial layout, and the size of the redundant graphs and/or the spacing width between the adjacent redundant graphs are determined according to the graph density distribution of the product mask and the graph density distribution in the initial layout.
17. The formation apparatus of a test reticle according to claim 16, wherein a second gap is provided between adjacent two of the base patterns inside each of the test patterns;
the adding unit is further configured to add a plurality of redundant patterns to the second gap of the initial layout.
18. The formation apparatus for a test reticle according to claim 17, wherein a plurality of the redundant patterns filled in the first gap and the second gap are arranged in an array.
19. The formation apparatus of a test reticle according to claim 13, wherein the redundancy pattern is rectangular.
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| CN109752930A (en) * | 2019-01-03 | 2019-05-14 | 长江存储科技有限责任公司 | The forming method and mask of mask |
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| US6709793B1 (en) * | 2002-10-31 | 2004-03-23 | Motorola, Inc. | Method of manufacturing reticles using subresolution test patterns |
| CN106294935A (en) * | 2016-07-28 | 2017-01-04 | 上海华力微电子有限公司 | The modeling of a kind of process modeling based on pattern density and modification method |
| CN109426083A (en) * | 2017-08-24 | 2019-03-05 | 中芯国际集成电路制造(上海)有限公司 | The optimization method and its optimization system and photolithography method of photoetching process |
| CN109752930A (en) * | 2019-01-03 | 2019-05-14 | 长江存储科技有限责任公司 | The forming method and mask of mask |
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