CN110572249A

CN110572249A - Synchronous automatic calibration method for high-speed TIADC

Info

Publication number: CN110572249A
Application number: CN201910807795.XA
Authority: CN
Inventors: 赵勇; 叶芃; 蒋俊; 邱渡裕; 曾浩
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2019-08-29
Filing date: 2019-08-29
Publication date: 2019-12-13
Anticipated expiration: 2039-08-29
Also published as: CN110572249B

Abstract

the invention discloses a synchronous automatic calibration method for a high-speed TIADC, which obtains calibration parameters of SYNC and BUFR _ RST synchronous reset signals by analyzing the relation among a clock, a synchronous signal and a data clock of a TIADC sampling system, and then carries out synchronous self-calibration on the TIADC sampling system according to the obtained calibration parameters, thereby improving the calibration speed and precision, and the calibration method is simple and easy to implement.

Description

synchronous automatic calibration method for high-speed TIADC

Technical Field

The invention belongs to the technical field of measuring instruments, and particularly relates to a synchronous automatic calibration method for a high-speed TIADC.

background

With the increase of the complexity of signals, the requirement on the measurement accuracy is higher and higher, which results in higher and higher requirements on the sampling rate of an acquisition system, and because of the limitation of the conversion rate and the inherent characteristics of the ADC, the sampling rate of a single-chip ADC cannot be increased rapidly, and under the existing period conditions, only the time-interleaved parallel sampling Technique (TIADC) can be sampled to increase the overall sampling rate.

in a high speed TIADC sampling system, N ADCs simultaneously receive analog input signals conditioned by channelsrespective sampling clock phaseThe analog signals are converted into digital signals sdata1, sdata2 and … sdatan, and are subjected to speed reduction processing, and transmitted to a real-time receiving system together with a data synchronization clock for processing.

As shown in fig. 1, a single chip 5GHz (4 core) ADC is used to achieve a 20G sampling rate scheme by time-interleaved sampling. The sampling clock SCLK of each ADC is 5GHz, the synchronous signal of the sampling clock of each ADC is SYNC, 4 cores of each ADC generate data clocks DCLK respectively, and each DCLK has BUFR _ RST synchronous reset signal in order to ensure data receiving synchronization. The role of each synchronization control signal is as follows:

1. SYNC signal

After the SYNC reset signal arrives (falling edge active), sampling begins on the first rising edge of SCLK, and the ADC generates 4-way synchronized DCLK (625MHz) with a fixed number of delays. The purpose of this synchronization signal is to control the synchronization of the n ADC samples.

SCLK is a 5GHz clock signal, which is down-converted to 2-way 2.5GHz signal inside the ADC, and the SYNC is actually synchronized with the 2.5GHz clock, with a period of 400 ps. In the following description, the SCLK clock refers to the 2.5GHz clock after ADC internal downconversion. The position of the falling edge of the SYNC signal in the SCLK period can not be determined in the design due to the wiring, the temperature influence and the like of the SYNC and the clock jitter of the SCLK, and the calibration can be carried out only by adopting a later calibration mode.

If SYNC is not well calibrated, it may cause the corresponding DCLK to advance or delay one clock when temperature changes, or small SCLK jitter occurs. Since the design cannot guarantee that SYNC falls in the proper position of SCLK, it must be guaranteed through parameter adjustment.

2、BUFR_RST

In the scheme, data receiving is completed in the FPGA, and the FPGA controls the resetting of the data receiving. Each core of each ADC has a corresponding BUFR _ RST reset signal controlled by the FPGA. However, the 4-way BUFR _ RST signal of one ADC is different from the phase difference of the synchronous DCLK due to different routing in the FPGA. When the 4 paths of BUFR _ RST signals are scattered in two periods of DCLK, the received data is not the data sampled by the same SCLK, and data mismatch is formed.

Similarly, in the design, it cannot be guaranteed that the 4 paths of BUFR _ RST fall in the same period of DCLK, and the SYNC also needs to be adjusted due to the business requirement, so that the clock of DCLK moves, it cannot be guaranteed that the 4 paths of BUFR _ RST fall in the same period of DCLK at the same time, and the time when the BUFR _ RST reaches DCLK can only be changed through parameter adjustment, so as to guarantee that the 4 paths of BUFR _ RST fall in the same period of DCLK.

The SYNC calibration parameter is closely related to the BUFR _ RST calibration parameter. To verify that BUFR _ RST falls within the same cycle of DCLK, a test mode of the ADC may be employed. In this mode, the ADC generates 4 identical data on the same SCLK, and by comparing whether the 4 data are identical, determines whether the 4-way BUFR _ RST reset falls in the same period of DCLK at the same time, thereby generating calibration data of BUFR _ RST. However, the delay from SCLK to DCLK generation is different between the ADC and the actual quantized data in the test mode, so there is still a possibility that the BUFR _ RST calibration data obtained in the test mode will be erroneous in the actual operating mode.

disclosure of Invention

the invention aims to overcome the defects of the prior art and provide a synchronous automatic calibration method for a high-speed TIADC, which realizes the automatic and reliable calibration of the TIADC system by acquiring the inherent characteristics of SYNC and BUFR _ RST calibration parameters.

To achieve the above object, the present invention provides a synchronous automatic calibration method for high-speed TIADC, comprising the steps of:

(1) acquiring the adjustment width BW of the reset signal BUFR _ RST;

(1.1) setting the ADC to work in a test mode;

(1.2) setting the adjustment step of the BUFR _ RST as Bstep, moving the BUFR _ RST by taking the Bstep as the step, and obtaining a comparison result sequence of the sampling data when different BUFR _ RST values exist;

(1.3) analyzing a comparison result sequence, recording the number of complete and continuous 0, and recording as C0;

(1.4), calculating BW: BW ═ Bstep × C0;

the method for acquiring the C0 comprises the following steps:

when the comparison result sequence firstly appears two or more than two consecutive 1 s, analyzing the data from left to right, encountering the first 0 to start counting until three or more than three consecutive 1 s appear subsequently, ending counting, and recording the counting value as C0;

when the comparison result sequence firstly appears as 0 or the leftmost two bits are not all 1, analyzing the data from left to right, starting counting at the first 0 after three or more continuous 1 appear, ending counting until three or more continuous 1 appear again, and recording the counting value as C0;

(2) when the synchronous signal SYNC is in the period of the sampling clock SCLK, acquiring a parameter St 0;

(2.1) setting the ADC to work in a test mode;

(2.2) setting the adjustment step SYNC _ step of SYNC, wherein the maximum adjustable length is N;

(2.3) starting the adjustable length from 0, and starting to scan the adjustable interval of the BUFR _ RST according to SYNC adjustment step to obtain a comparison sequence;

(2.4) analyzing and comparing the sequences to obtain a parameter T0;

the parameter T0 is obtained by the following steps:

when the BUFR _ RST is in one period of the data synchronization clock DCLK, and the leftmost two bits of the comparison sequence are all 1, counting the number of 1 which continuously appear from the left end of the comparison sequence, and when 0 appears, ending counting, and recording the count value as C1; further, from the left end to the right end of the comparison sequence, counting is started when 0 appears for the first time, and when three or more consecutive 1 s appear consecutively, the count value is denoted as C0;

Then the parameter T0 is: t0 ═ T-dclk-C1 × Bstep-BW, BW ═ C0 × Bstep;

when BUFR _ RST is on the rising edge of DCLK or the left end of BW is at the critical position of DCLK rising edge, and the two leftmost bits of the comparison sequence are not necessarily 1, counting the number of three or more continuous 1 which continuously appear subsequently from the left end of the comparison sequence, and recording the counting value as C0_ F; then after C0_ F, counting is started from the first occurrence of 0, and when the count is consistent to the subsequent occurrence of three or more consecutive 1 s, the counting is ended, and the count value is recorded as C0;

then the parameter T0 is: t0 ═ T-dclk-C0 _ F × Bstep, BW ═ C0 × Bstep;

(2.5) calculating an ideal setting value Bj of BUFR _ RST corresponding to the SYNC adjustment stepping value;

when the adjustable length is 0, the ideal setting value of BUFR _ RST corresponding to SYNC adjusting step is Bj _0, and the period of DCLK is T-DCLK; then Bj _0 ═ T-dclk ÷ 2-T0-BW ÷ 2, then Bj _0 is determined, if Bj _0<0, then Bj _0 ═ Bj _0+ T-dclk, otherwise Bj _0 remains unchanged;

(2.6) adding 1 to the adjustable length, then judging whether the adjustable length reaches the maximum adjustable length N, if so, entering the step (2.7), otherwise, returning to the step (2.3);

(2.7) adjusting SYNC by all the adjusting steps SYNC _ step according to the method from the step (2.3) -2.6 to obtain a series of Bj values, and then forming a series of Bj values into a Bj sequence;

(2.8) classifying the Bj sequences, if a current Bj value is Bj _ M, a next Bj value is Bj _ n, and | Bj _ M-Bj _ n | > M ÷ 2 is satisfied, M ═ SCLK ÷ Bstep indicates that a mutation has occurred, and the M value at this time is recorded, thereby calculating a parameter St 0: st0 ═ SCLK-m × SYNC _ step;

(3) in actual sampling, when the left end of BW is in the period of DCLK, acquiring a parameter Bt 0;

(3.1) setting the ADC to work in an actual sampling mode, and then inputting a test signal;

(3.2) setting the adjustment step of the BUFR _ RST to be Bstep, wherein the maximum adjustable length is H;

(3.3) starting from 0, and acquiring sampling data of the ADC in a stepping mode according to the adjustment of the BUFR _ RST;

{y₀₀,y₀₁,…,y_0n,…,y_0M},

{y₁₀,y₁₁,…,y_1n,…,y_1M}

{y₂₀,y₂₁,…,y_2n,…,y_2M}

{y₃₀,y₃₁,…,y_3n,…,y_3M}

Wherein n is 0,1,2, …, and M is the total number of sampling time;

(3.4) respectively calculating the phases of the four paths of sampling data;

let the frequency of the test signal be omega, alpha_n＝cos(ωt_n)，β_n＝sin(ωt_n) The following variables are then:

wherein τ is 0,1,2,3, which represents a sampling channel;

computing samples within each sampling channelphase theta of sample data_τ：

(3.5) adding 1 to the adjustable length, judging whether the adjustable length reaches the maximum adjustable length H, if so, substituting the phase difference of the sampling data corresponding to the maximum adjustable length H into the step (3.6), and if not, returning to the step (3.3);

(3.6) judging whether the phase difference of the sampling data in any two channels is greater than 800ps, if so, indicating that the BUFR _ RST is in different periods of the DCLK, and then recording an adjustable length value set by the BUFR _ RST when the situation occurs for the first time, and recording the adjustable length value as K;

(3.7), calculating parameter Bt 0: bt0 ═ T-dclk-K × Bstep;

(4) acquiring synchronous setting values of SYNC and BUFR _ RST;

(4.1) calculating a synchronization setting value required to be sent by SYNC;

According to the practical situation, when the SYNC does not need to be adjusted, if the period of the SYNC satisfies: when SYNCa is T-sclk ÷ 2-St 0 and T-sclk ≧ 2 ≧ St0, or SYNCa is T-sclk ÷ 2+ St0+ T-sclk and T-sclk ÷ 2 < St0, then the synchronization setting value SYNCj0 that SYNC needs to send satisfies: SYNCj0 ═ SYNCa ÷ SYNC _ step;

according to the practical situation, when the SYNC needs to be adjusted, the synchronization setting value SYNCsend that the SYNC needs to send satisfies: syncend 0+ (N × T-sclk) ÷ SYNC _ step;

(4.2) calculating a synchronization setting value Bj0 required to be sent by BUFR _ RST;

according to practical conditions, when SYNC does not need to be adjusted, if the ideal setting value Bj of BUFR _ RST satisfies: bj ═ T-dclk ÷ 2-BT 0-BW ÷ 2, if Bj <0, Bj ═ Bj + T-dclk, then the synchronization setting Bj0 that BUFR _ RST needs to send satisfies: bj0 ═ INT ((SYNCa × 2 ÷ T-SCLK)) × T-SCLK ÷ Bstep + Bj, INT being the rounding function, T-SCLK being the period of SCLK;

According to the practical situation, when SYNC needs to be adjusted, the synchronization setting value Bsend that the BUFR _ RST needs to send satisfies: bsend ═ Bj0+ (INT (((syncend-SYNCj 0) × SYNC _ step) ÷ T-sclk) × T-sclk) ÷ Bstep;

(5) and (5) sending the synchronous setting value obtained in the step (4) according to the actual situation, thereby completing the synchronous automatic calibration of the TIADC. The invention aims to realize the following steps:

the invention relates to a synchronous automatic calibration method for a high-speed TIADC, which obtains calibration parameters of SYNC and BUFR _ RST synchronous reset signals by analyzing the relationship among a clock, a synchronous signal and a data clock of a TIADC sampling system, and then carries out synchronous self-calibration on the TIADC sampling system according to the obtained calibration parameters, thereby improving the calibration speed and precision, and the calibration method is simple and easy to implement.

Drawings

FIG. 1 is a schematic diagram of a 20GSPS sampling implementation by TIADC technology;

FIG. 2 is a flow chart of a method of synchronous auto-calibration for a high-speed TIADC of the present invention;

FIG. 3 is a timing diagram of the 4-way BUFR _ RST signal arriving at DCLK;

FIG. 4 is a schematic diagram of the justification width of BUFR _ RST;

FIG. 5 is a graph of BUFR _ RST versus DCLK as it changes with DCLK when SYNC is adjusted;

FIG. 6 is a schematic diagram of the position of BW in a DCLK cycle;

FIG. 7 is a schematic diagram of the BUFR _ RST reset group in the same DCLK cycle;

FIG. 8 is a schematic diagram of the BUFR _ RST reset group being within two DCLK cycles;

FIG. 9 is a diagram of the BUFR _ RST reset group arriving at DCLK prior to its arrival when SYNC is 0;

FIG. 10 is a synchronous calibration timing diagram when St0< SCLK/2;

FIG. 11 is a timing diagram for synchronous calibration when St0 ≧ SCLK/2.

Detailed Description

the following description of the embodiments of the present invention is provided in order to better understand the present invention for those skilled in the art with reference to the accompanying drawings. It is to be expressly noted that in the following description, a detailed description of known functions and designs will be omitted when it may obscure the subject matter of the present invention.

examples

when the falling edge of the synchronous signal SYNC comes, the next clock of the sampling clock signal SCLK starts to carry out quantitative collection, after the expected delay is set and the inherent delay of each ADC is added, the quantitative data is prepared, 4 paths of synchronous data synchronous clocks DCLK are output, and when the FPGA receives the data, 4 paths of BUFR _ RST reset signals are sent out to start receiving the data. In this process, if SYNC and SCLK are jittered or affected by temperature, the falling edge of SYNC does not fall within the valid region of SCLK (a little further away from the rising edge of SCLK), resulting in a delay or an advance of one cycle for subsequent DCLK. If the 4 paths of BUFT _ RSTs do not fall within one period of the 4 paths of DCLK at the same time, the received 4 paths of data are not data generated by the same SCLK, and data mismatch is caused.

When the SYNC is sent from the PLL, it is synchronized with SCLK, and when reaching the respective ADC through the respective trace, it forms a phase relationship only related to hardware at the ADC with the respective SCLK (also passing through the respective line). Once the hardware determines that the position of the falling edge of SYNC in the SCLK period is fixed, when the SYNC is adjusted, the falling edge of SYNC is moved to be in different positions of the SCLK period, and the movement is linear. Therefore, we only need to find out that the adjustment time of SYNC is 0, and the falling edge of SYNC is at the position of SCLK period, and then we can adjust SYNC arbitrarily according to our business needs. This parameter is defined as St0, and is an intrinsic parameter determined by hardware, and is obtained by automatic calibration in the present invention.

and starting by the clock of the first SCLK (2.5GHz) after the descending edge of SYNC, the ADC starts to collect, and then outputs a data synchronization clock DCLK through the delay required by the service plus the inherent delay of the ADC characteristic. In order to make the 4-way BUFR _ RST fall in the same DCLK period at the same time, the adjustment of BUFR _ RST is related to the position of the left end of the reset group in DCLK besides the width of BUFR _ RST reset group, and the determination of the position is related to the inherent delay of ADC characteristic and the routing of BUFR _ RST reset signal. Once the hardware is fixed (specific ADC, BUFR _ RST trace), the position relationship is determined, which we call this parameter Bt0, and it is an inherent parameter after the hardware and design are completed, and the present invention is obtained by automatic calibration. Note that this parameter has a different value in the test mode of the ADC than in the actual sampling mode, and we must obtain it by measuring the signal.

the BUFR _ RST reset group has a total of 4 BUFR _ RST reset signals, the time difference between the first arrival and the last arrival of the BUFR _ RST reset signals after the arrival of DCLK is prior, and the width of the BUFR _ RST reset group is called BW. This is also an inherent property of the hardware, and the ADC is not identical for each channel. According to the invention, three parameters of St0, Bt0 and BW are obtained through an automatic calibration technology, so that synchronous calibration of the ADC is completed.

In the following, we will describe the detailed process of the synchronous auto-calibration method for high-speed TIADC according to the present invention with reference to fig. 2, which specifically includes the following steps:

s1, acquiring the adjustment width BW of the reset signal BUFR _ RST;

BUFR _ RST is used to ensure that the 4 reset signals fall in the same DCLK cycle at the same time.

As shown in fig. 3, after the 4-way BUFR _ RST signals are simultaneously sent out, the time elapsed until the signals reach DCLK differs depending on the respective wirings, and the signals are sent out before the signals reach DCLK.

fig. 3 depicts the meaning of BW (BUFR _ RST Width). In the following figures, we denote the BUFR _ RST reset group by a box, the width of which denotes the BW;

when we adjust the value of BUFR _ RST, we equate to shifting the BUFR reset group, represented by a box, relative to DCLK. When the square box is in the same period of DCLK, it means that the data we receive comes from the data collected in the same SCLK clock period, and no data mismatch occurs at this time. When the box is at two cycles of DCLK, i.e., the box crosses the rising edge of DCLK, the data received at this time comes from two DCLK cycles, i.e., from the data collected by two SCLK clock cycles, resulting in a data mismatch. The black dots in fig. 4 represent data from different DCLK cycles.

The BW value is dependent only on the hardware design and not on the mode of the ADC, whether in the test mode or the actual acquisition mode of the ADC. Therefore, whether 4 collected data are consistent or not can be observed in the test mode of the ADC to judge whether the reset group spans two DCLK, and the specific operation process is as follows:

S1.1, setting an ADC to work in a test mode;

s1.2, setting the adjustment step of the BUFR _ RST as Bstep, moving the BUFR _ RST by taking the Bstep as the step, and obtaining a comparison result sequence of sampling data when different BUFR _ RST values exist;

In this embodiment, when the reset group is in the same DCLK cycle, the received 4 data are the same, we mark 1, when the reset group is in (spans) two DCLK cycles, the received 4 data are inconsistent, we mark 0, and the comparison result sequence consists of 0 and 1;

we take the DCLK cycle as 625MHz (1600ps), Bstep as 80ps, and the total number of adjustable steps as 32 as an example, and assume the following sequence of comparison results:

00011111111111110000001111111111 or 11111111111000000011111111111110

s1.3, analyzing a comparison result sequence, recording the number of complete and continuous 0, and recording as C0;

s1.4, calculating BW: BW ═ Bstep × C0;

the method for acquiring the C0 comprises the following steps:

When the comparison result sequence firstly appears two or more than two consecutive 1 (for example 11111111111000000011111111111110), analyzing the data from left to right, encountering the first 0 to start counting until three or more than three consecutive 1 appear subsequently, ending counting, and marking the counting value as C0;

in the above example, C0 ═ 7, BW ═ 80 × 7 ═ 560(ps)

in the above example, C0 is 6, BW is 80 × 6 is 480(ps)

in practical cases, multiple tests can be performed, and the average of the tests is obtained.

Through the algorithm, the inherent time difference between the BUFR _ RST reset group and the DCLK arriving time can be found out due to hardware, and basic data is provided for the subsequent automatic adjustment of the BUFR _ RST.

s2, when the synchronous signal SYNC is in the period of the sampling clock SCLK, acquiring a parameter St 0;

the SYNC signal and SCLK clock are both sent out synchronously from the PLL and each goes through a different line, so there is a fixed phase difference when arriving at the ADC, which is inherent in the hardware design, and once the hardware determines, its value is fixed.

in both the test mode and the actual sampling mode of the ADC, the path of the subsequent signal does not affect the phase difference at the previous stage after SYNC and SCLK are synchronized, so St0 can be obtained in the test mode of the ADC.

FIG. 5 illustrates the change in DCLK, the BUFR _ RST reset group, as a function of DCLK when SYNC is adjusted. Where the green and red lines represent the cases when SYNC is at different positions on SCLK, respectively.

as can be seen from fig. 5, when the SYNC is adjusted (shifted to the right), the corresponding DCLK is delayed by 1 SCLK clock after the rising edge of SYNC across domain SCLK, so that the position of BUFR _ RST in DCLK is also shifted by 1 SCLK clock. The comparison sequence obtained by analyzing and scanning different setting values of BUFR _ RST shows that SYNC crosses the rising edge of SCLK when the comparison result sequence is mutated.

The specific process of this step is described in detail below.

S2.1, setting the ADC to work in a test mode;

s2.2, setting an adjusting step SYNC _ step of SYNC, wherein the maximum adjustable length is N, N is greater than T-sclk/SYNC _ step, and N is T-sclk/SYNC _ step multiplied by 2 under the general condition; t-sclk is the period of SYNC;

s2.3, starting from 0, adjusting the length, and starting to scan the adjustable interval of the BUFR _ RST according to SYNC adjustment steps to obtain a comparison sequence;

s2.4, analyzing and comparing the sequence to obtain a parameter T0;

the parameter T0 is obtained by the following steps:

then the parameter T0 is: t0 ═ T-dclk-C1 × Bstep-BW, BW ═ C0 × Bstep;

then the parameter T0 is: t0 ═ T-dclk-C0 _ F × Bstep, BW ═ C0 × Bstep;

s2.5, calculating an ideal setting value Bj of BUFR _ RST corresponding to the SYNC adjustment stepping value;

Reasonable values of BFRT _ RST should have the BFRT _ RST reset group box in the middle of the DCLK cycle, with T0 indicating the position of the left side of BW in the DCLK cycle in FIG. 6. Regardless of the BW location, the ideal setting value of BUFR _ RST (defined as Bj, and the value at which SYNC is 0 is defined as Bj _0) can be set as follows:

S2.6, adding 1 to the adjustable length, judging whether the adjustable length reaches the maximum adjustable length N, if so, entering the step S2.7, otherwise, returning to the step S2.3;

s2.7, adjusting SYNC by all the adjusting steps SYNC _ step according to the method from the step S2.3 to the step S2.6 to obtain a series of Bj values, and forming a Bj sequence by the series of Bj values;

s2.8, theoretically, when M ═ SCLK ÷ Bstep changes occur in a mutation, it indicates that the falling edge of SYNC crosses the rising edge of SCLK once, this time called a mutation; analyzing the Bj sequence, if a current Bj value is Bj _ M, the next Bj value is Bj _ n, and if | Bj _ M-Bj _ n | > M ÷ 2 is satisfied, M ═ SCLK ÷ Bstep, it indicates that a mutation has occurred, and the M value at this time is recorded, thereby calculating a parameter St 0: st0 ═ SCLK-m × SYNC _ step;

from the above description, it can be seen that the finer St0 is, the smaller SYNC _ step is required.

S3, acquiring a parameter Bt0 when the left end of BW is in a period of DCLK during actual sampling;

In the case where the SYNC adjustment value is 0, the BUFR _ RST reset group block has different positions in DCLK at the leftmost side, in the test mode and the actual sampling mode of the ADC, where the two modes go through different internal circuits of the ADC. Therefore, this value must be obtained in the actual sampling mode, which includes the following steps:

s3.1, setting the ADC to work in an actual sampling mode, and then inputting a test signal;

in this embodiment, a 5Gsps ADC samples 4 channels of 1.25 data, and the waveform phase difference corresponding to each channel of data is 200 ps. With a 100MHz sine wave as the test waveform, the sine wave can be expressed as:

Acos(ωt_n+ θ) + C, where A is the amplitude, signal frequency, initial phase, and C is the offset.

s3.2, setting the adjustment step of the BUFR _ RST as Bstep, and setting the maximum adjustable length as H;

s3.3, starting from 0, obtaining sampling data of the ADC in a stepping mode according to the adjustment of the BUFR _ RST;

{y₀₁,…,y_0n,…,y_0M'},

{y₁₁,…,y_1n,…,y_1M'}

{y₂₁,…,y_2n,…,y_2M'}

{y₃₁,…,y_3n,…,y_3M'}

Wherein n is 1,2, …, M' is the total number of sampling moments;

s3.4, respectively calculating the phases of the four paths of sampling data;

wherein τ is 0,1,2,3, which represents a sampling channel;

Calculating the phase θ of the sampled data in each sampling channel_τ：

S3.5, adding 1 to the adjustable length, judging whether the adjustable length reaches the maximum adjustable length H, if so, substituting the phase difference of the corresponding sampling data under the maximum adjustable length H into the step S3.6, otherwise, returning to the step S3.3;

S3.6, theoretically, every time of acquisition, 4 paths of signals are compared according to the Core1, the Core2, the Core3 and the Core4, and the phase differences of the Core2, the Core3, the Core4 and the Core1 are respectively 200ps,400ps and 600 ps. If the synchronization is not correct, the phase difference is not the distance, and therefore the reset is judged to be abnormal.

as can be seen from the above description, the BUFR _ RST reset group is either in the same period of DCLK or in two periods of DCLK, and therefore it is necessary to determine whether the phase difference between the sampled data in any two channels is greater than 800ps, if so, it indicates that the BUFR _ RST is in a different period of DCLK, and then records the adjustable length value set by the BUFR _ RST when this occurs for the first time, and records it as K;

s3.7, as shown in fig. 7, when the BUFR _ RST reset group is in the same DCLK period at the beginning, the number of steps of the BUFR _ RST in the same DCLK period is:

N＝(T-dclk－BW)÷Bstep

similarly, as shown in FIG. 8, the number of Bstep of BUFR _ RST reset group in two DCLK cycles is:

M＝BW÷Bstep

from a design point of view, N should be much larger than M, which means BW should be much smaller than the period of DCLK, otherwise the tunable range of BUFR _ RST is narrow or not tunable.

this situation needs to be guaranteed by design not to occur. This occurs because the reset signal of BUFR _ RST reaches DCLK before it arrives when SYNC is 0, and in practical designs, its BUFR _ RST that reaches DCLK first should be greater than 4.8ns, as shown in FIG. 9. Therefore, the design parameters Bt0 are required: bt0 ═ T-dclk-K × Bstep;

Theoretically, the number of adjustment steps of BUFR _ RST should be greater than or equal to DCLK _ p ÷ Bstep × 2. I.e. 2 times the DCLK period can be scanned.

So far, in the actual sampling case, when SYNC is 0, BUFR _ RST is obtained at the initial position in the DCLK cycle.

s4, acquiring synchronous setting values of SYNC and BUFR _ RST;

The aim of the high-speed TIADC synchronous calibration is to ideally place the SYNC synchronous signal in the middle of the SCLK period so as to avoid the uncertainty of SCLK starting acquisition caused by clock jitter, temperature influence and metastable state.

meanwhile, for the BUFR _ RST, no matter how SCLK and synchronization of the front end change, 4 paths of BUFR _ RST are ensured to fall in the same DCLK period at the same time, ideally, a reset group (square frame) formed by the 4 paths of BUFR _ RST falls in the middle of the same DCLK period, so that inconsistency of data receiving caused by clock jitter, temperature influence, metastable state and the like is avoided, and data mismatching is avoided.

in the following description, 400 means the period of SCLK (2.5GHZ), meaning 400ps, which may be denoted by T-SCLK.

in specific application, we need to discuss separately according to the requirements of actual services, and even if the services do not need to adjust SYNC, a certain adjustment value needs to be sent in order to ensure that the system is stable and sampling does not have mismatch. The basic principle is that SYNC falls in the middle of the SCLK (2.5GHz) period, and the BUFR _ RST reset group box falls in the middle of the DCLK period.

in another case, when the SYNC needs to be adjusted according to the service requirement, the time that the SYNC can only be adjusted is only an integral multiple of 400ps, and the value that needs to be adjusted is set as: SYNC _ adjust _ ps ═ N × 400.

based on the two situations, we respectively set up the following specific processes:

s4.1, calculating a synchronization setting value required to be sent by SYNC;

in the present embodiment, the timing charts when T-sclk/2 < St0 and T-sclk/2 ≧ St0 are shown in FIGS. 10 and 11.

s4.2, calculating a synchronization setting value Bj0 required to be sent by the BUFR _ RST;

According to practical conditions, when SYNC does not need to be adjusted, if the ideal setting value Bj of BUFR _ RST satisfies: bj ═ T-dclk ÷ 2-T0-BW ÷ 2, if Bj <0, Bj ═ Bj + T-dclk, then the synchronization setting Bj0 that BUFR _ RST needs to send satisfies: bj0 ═ INT ((SYNCa × 2 ÷ T-SCLK)) × T-SCLK ÷ Bstep + Bj, INT being the rounding function, T-SCLK being the period of SCLK;

and S5, according to the actual situation, sending the synchronization setting value acquired in the step S4, thereby completing the synchronous automatic calibration of the TIADC. Thus, unreliable caused by clock jitter and temperature influence is avoided; meanwhile, the BUFR _ RST reset group frame is ensured to be in the middle position of the DCLK period, and data mismatch caused by clock jitter and temperature influence is avoided.

although illustrative embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, and various changes may be made apparent to those skilled in the art as long as they are within the spirit and scope of the present invention as defined and defined by the appended claims, and all matters of the invention which utilize the inventive concepts are protected.

Claims

1. a method for synchronous auto-calibration of a high-speed TIADC, comprising the steps of:

(1) Acquiring the adjustment width BW of the reset signal BUFR _ RST;

(1.1) setting the ADC to work in a test mode;

(1.4), calculating BW: BW ═ Bstep × C0;

(2.1) setting the ADC to work in a test mode;

(2.4) analyzing and comparing the sequences to obtain a parameter T0;

(2.8), analyzing the Bj sequence, if a current Bj value is Bj _ M, the next Bj value is Bj _ n, and | Bj _ M-Bj _ n | > M ÷ 2 is satisfied, M ═ SCLK ÷ Bstep indicates that a mutation has occurred, and the M value at this time is recorded, thereby calculating a parameter St 0: st0 ═ SCLK-m × SYNC _ step;

{y₀₀,y₀₁,…,y_0n,…,y_0M},

{y₁₀,y₁₁,…,y_1n,...,y_1M}

{y₂₀,y₂₁,…,y_2n,...,y_2M}

{y₃₀,y₃₁,…,y_3n,...,y_3M}

wherein n is 0,1,2, …, and M is the total number of sampling time;

(3.4) respectively calculating the phases of the four paths of sampling data;

Wherein τ is 0,1,2,3, which represents a sampling channel;

Calculating the phase θ of the sampled data in each sampling channel_τ：

(3.7), calculating parameter Bt 0: bt0 ═ T-dclk-K × Bstep;

(4) acquiring synchronous setting values of SYNC and BUFR _ RST;

(4.1) calculating a synchronization setting value required to be sent by SYNC;

(5) and (5) sending the synchronous setting value obtained in the step (4) according to the actual situation, thereby completing the synchronous automatic calibration of the TIADC.

2. The method of claim 1, wherein the C0 is obtained by:

when the comparison result sequence first appears to be 0, or the leftmost two bits are not all 1, the data is analyzed from left to right, the first 0 after three or more consecutive 1's appear starts counting until three or more consecutive 1's appear again, the counting is ended, and the count value is denoted as C0.

3. the method of claim 1, wherein the parameter T0 is obtained by:

then the parameter T0 is: t0 ═ T-dclk-C1 × Bstep-BW, BW ═ C0 × Bstep;

then the parameter T0 is: t0 ═ T-dclk-C0 _ F × Bstep, BW ═ C0 × Bstep.

4. A method of synchronous automatic calibration for a high speed TIADC according to claim 1, wherein the maximum adjustable length N satisfies: n is greater than T-sclk/SYNC _ step.