CN110572225A - Receiver direct current offset monitoring system, method, electronic device and storage medium - Google Patents
Receiver direct current offset monitoring system, method, electronic device and storage medium Download PDFInfo
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- CN110572225A CN110572225A CN201910650370.2A CN201910650370A CN110572225A CN 110572225 A CN110572225 A CN 110572225A CN 201910650370 A CN201910650370 A CN 201910650370A CN 110572225 A CN110572225 A CN 110572225A
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- 238000012544 monitoring process Methods 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 25
- 238000003860 storage Methods 0.000 title claims abstract description 11
- 238000012545 processing Methods 0.000 claims abstract description 30
- 230000002093 peripheral effect Effects 0.000 claims abstract description 5
- 238000013139 quantization Methods 0.000 claims description 25
- 238000004590 computer program Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 3
- 238000004458 analytical method Methods 0.000 abstract description 4
- 238000012360 testing method Methods 0.000 abstract description 4
- 238000010923 batch production Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009776 industrial production Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/20—Monitoring; Testing of receivers
- H04B17/29—Performance testing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/20—Monitoring; Testing of receivers
- H04B17/21—Monitoring; Testing of receivers for calibration; for correcting measurements
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- Computer Networks & Wireless Communication (AREA)
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- Measurement Of Current Or Voltage (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention provides a direct current offset monitoring system of a receiver, which comprises an accumulator, a memory and a data processing module, wherein an analog-to-digital converter of the receiver is connected with the accumulator, the accumulator is connected with the memory, the memory is connected with the data processing module, and the data processing module is connected with an SPI (serial peripheral interface) host of the receiver. The invention relates to a direct current offset monitoring method of a receiver. The invention also relates to an electronic device and a readable storage medium for executing the receiver direct current offset monitoring method. The invention can monitor the DC offset voltage generated in the zero intermediate frequency receiver circuit in real time and feed back the DC offset voltage value into accurate DC offset voltage value no matter whether the DC offset calibration is carried out or not, and can accurately indicate the DC working state of the receiver no matter in chip test, chip analysis or chip batch production chip selection.
Description
Technical Field
the present invention relates to the field of wireless communication technologies, and in particular, to a receiver dc offset monitoring system, method, electronic device, and storage medium.
background
in the field of modern wireless communication, zero intermediate frequency receivers have great advantages in terms of low power consumption and high integration, and are thus widely used in today's wireless devices. However, both random deviation generated by devices or modules in the industrial production of integrated circuits and local oscillator leakage can cause direct current offset, and direct current operating points of the receiver can be deviated or even saturated after the direct current operating points are amplified step by a later-stage gain stage, so that the whole channel can not work normally. Therefore, all zero if receivers will perform dc offset calibration, but how to select out the calibration failed chip in mass production is a problem to be solved if the calibration result meets the requirement.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a receiver direct current offset monitoring system, which can monitor the output direct current offset voltage of a zero intermediate frequency receiver in real time and feed back an accurate direct current offset voltage value for the purposes of testing, analysis, mass production chip selection and the like no matter whether direct current offset calibration is carried out or not.
The invention provides a direct current offset monitoring system of a receiver, which comprises an accumulator, a memory and a data processing module, wherein an analog-to-digital converter of the receiver is connected with the accumulator, the accumulator is connected with the memory, the memory is connected with the data processing module, and the data processing module is connected with an SPI (serial peripheral interface) host of the receiver; wherein the content of the first and second substances,
The accumulator is used for accumulating the output signals of the analog-to-digital converter;
the memory is used for dynamically storing the data of the accumulator;
The data processing module is used for extracting and outputting the sign bit of the direct current offset voltage stored in the memory, performing high-order interception on the digital quantization value of the direct current offset voltage and outputting the digital quantization value, comparing the digital quantization value of the direct current offset voltage with an overload threshold value and outputting an overload identifier.
furthermore, the data processing module comprises a data processor, a comparator, a plurality of input ports and a plurality of output ports, wherein the data processor is connected with the memory through the input ports, the data processor is connected with the SPI host through the output ports, the data processor is connected with the comparator, and the comparator is connected with the SPI host through the input ports and the output ports.
further, the number of the input ports is two, the input ports include a first input port and a second input port, the data processor is connected with the memory through the first input port, the comparator is connected with the SPI host through the second input port, the data processor reads data stored in the memory through the first input port, and the comparator receives the overload threshold value set by the SPI host through the second input port.
Further, the number of the output ports is three, the output ports include a first output port, a second output port, and a third output port, the data processor is connected to the SPI host through the first output port and the second output port, the comparator is connected to the SPI host through the third output port, the data processor outputs a sign bit of the dc offset voltage through the first output port, the data processor outputs a high-order intercept result of a digital quantization value of the dc offset voltage through the second output port, and the comparator outputs the overload flag through the third output port.
further, the memory is a random access memory.
the method for monitoring the direct current offset of the receiver comprises the following steps:
Receiving a signal, and receiving an output signal of an analog-to-digital converter of a receiver;
Accumulating the output signals of the analog-to-digital converter;
storing the signals, and dynamically storing the accumulated signals;
Processing a signal, extracting a sign bit of a stored direct-current offset voltage, performing high-order interception on a digital quantization value of the direct-current offset voltage, and comparing the digital quantization value of the direct-current offset voltage with an overload threshold value;
And outputting a signal, namely outputting the sign bit of the direct current offset voltage, a high bit interception result of the digital quantization value of the direct current offset voltage and an overload identifier.
Further, in the signal processing step, if the absolute value of the digital quantization value of the dc offset voltage is greater than the overload threshold, it is determined that the dc overload offset is generated.
further, the method also comprises a step of receiving a threshold value, wherein the threshold value is received by an overload threshold value set by an SPI host of the receiver.
An electronic device, comprising: a processor;
a memory; and a program, wherein the program is stored in the memory and configured to be executed by the processor, the program comprising instructions for performing a receiver dc offset monitoring method.
A computer-readable storage medium having stored thereon a computer program for execution by a processor of a receiver dc offset monitoring method.
compared with the prior art, the invention has the beneficial effects that:
The invention provides a direct current offset monitoring system of a receiver, which comprises an accumulator, a memory and a data processing module, wherein an analog-to-digital converter of the receiver is connected with the accumulator, the accumulator is connected with the memory, the memory is connected with the data processing module, and the data processing module is connected with an SPI (serial peripheral interface) host of the receiver. The invention relates to a direct current offset monitoring method of a receiver. The invention also relates to an electronic device and a readable storage medium for executing the receiver direct current offset monitoring method. The invention can monitor the DC offset voltage generated in the zero intermediate frequency receiver circuit in real time and feed back the DC offset voltage value into accurate DC offset voltage value no matter whether the DC offset calibration is carried out or not, and can accurately indicate the DC working state of the receiver no matter in chip test, chip analysis or chip batch production chip selection.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical solutions of the present invention more clearly understood and to implement them in accordance with the contents of the description, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings. The detailed description of the present invention is given in detail by the following examples and the accompanying drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
Fig. 1 is a diagram of a receiver architecture including a dc offset monitoring system according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a DC offset monitoring system of a receiver according to the present invention;
FIG. 3 is a schematic diagram of a data processing module according to the present invention;
fig. 4 is a flow chart of a receiver dc offset monitoring method according to the present invention.
Detailed Description
the present invention will be further described with reference to the accompanying drawings and the detailed description, and it should be noted that any combination of the embodiments or technical features described below can be used to form a new embodiment without conflict.
As shown in fig. 1, the receiver dc offset monitoring system of the present invention is applied to a receiver circuit, and specifically, the receiver dc offset monitoring system is connected between a signal link of a receiver and an SPI reading module, an output signal of the signal link is a differential signal, and the receiver inevitably generates a dc offset voltage, and the receiver can correctly read the dc offset voltage as long as an ADC (analog-to-digital converter), the receiver dc offset monitoring system, and the SPI reading module normally operate regardless of whether the receiver is in dc offset calibration or not.
A receiver dc offset monitoring system, as shown in fig. 2, includes an accumulator, a memory, and a data processing module, wherein an analog-to-digital converter of the receiver is connected to the accumulator, the accumulator is connected to the memory, the memory is connected to the data processing module, and the data processing module is connected to an SPI host of the receiver; wherein the content of the first and second substances,
The accumulator is used for receiving an output signal of an analog-to-digital converter (ADC) of the channel and accumulating the output signal of the ADC; in this embodiment, the output signal of the analog-to-digital converter is a differential signal.
The memory is used for dynamically storing the data of the accumulator; preferably, the memory is Random Access Memory (RAM).
The data processing module is used for extracting and outputting the sign bit of the direct current offset voltage stored in the memory, performing high-order interception on the digital quantization value of the direct current offset voltage and outputting the digital quantization value, determining the final detection precision by the intercepted digit, comparing the digital quantization value of the direct current offset voltage with an overload threshold value and outputting an overload identifier.
as shown in fig. 3, preferably, the data processing module includes a data processor, a comparator, a plurality of input ports, and a plurality of output ports, the data processor is connected to the memory through the input ports, the data processor is connected to the SPI host through the output ports, the data processor is connected to the comparator, and the comparator is connected to the SPI host through the input ports and the output ports. Preferably, the number of the input ports is two, the input ports include a first input port and a second input port, the data processor is connected with the memory through the first input port, the comparator is connected with the SPI host through the second input port, the data processor reads data stored in the memory through the first input port, that is, data input of the RAM in fig. 3, the comparator receives an overload threshold value set by the SPI host through the second input port, that is, a preset overload threshold value in fig. 3, in this embodiment, as shown in fig. 2, the overload threshold value is set through an SPI write-in module in the SPI host. Preferably, the number of the output ports is three, the output ports include a first output port, a second output port and a third output port, the data processor is connected with the SPI host through the first output port and the second output port, the comparator is connected with the SPI host through the third output port, the data processor outputs a sign bit of the dc offset voltage through the first output port, i.e., the sign bit output in fig. 3, the data processor outputs the digital quantization value high bit truncated result of the dc offset voltage through the second output port, i.e. the data output in fig. 3, the comparator outputs an overload flag, i.e. the overload flag output in fig. 3, via a third output port, which, in this embodiment, as shown in fig. 2, and reading the sign bit of the direct-current offset voltage, the high-order interception result of the digital quantization value of the direct-current offset voltage and the overload identification through an SPI reading module in the SPI host.
The method for monitoring the dc offset of the receiver, as shown in fig. 4, includes the following steps:
Receiving a signal, and receiving an output signal of an analog-to-digital converter of a receiver; in this embodiment, the output signal of the analog-to-digital converter is a differential signal.
Accumulating the signal, accumulating the output signal of the A/D converter;
Storing the signals, and dynamically storing the accumulated signals;
And processing the signal, extracting the sign bit of the stored DC offset voltage, performing high-order interception on the digital quantization value of the DC offset voltage, determining the final detection precision by the intercepted digit number, comparing the digital quantization value of the DC offset voltage with an overload threshold value, and judging the DC overload offset if the absolute value of the digital quantization value of the DC offset voltage is greater than the overload threshold value.
and outputting a signal, namely outputting a sign bit of the direct current offset voltage, a high bit interception result of a digital quantization value of the direct current offset voltage and an overload identifier.
In an embodiment, it is preferable that the method further includes a step of receiving an overload threshold set by an SPI master of the receiver.
An electronic device, comprising: a processor;
A memory; and a program, wherein the program is stored in the memory and configured to be executed by the processor, the program comprising instructions for performing the receiver dc offset monitoring method.
A computer-readable storage medium having stored thereon a computer program for execution by a processor of a receiver dc offset monitoring method.
the invention provides a direct current offset monitoring system of a receiver, which comprises an accumulator, a memory and a data processing module, wherein an analog-to-digital converter of the receiver is connected with the accumulator, the accumulator is connected with the memory, the memory is connected with the data processing module, and the data processing module is connected with an SPI (serial peripheral interface) host of the receiver. The invention relates to a direct current offset monitoring method of a receiver. The invention also relates to an electronic device and a readable storage medium for executing the receiver direct current offset monitoring method. The invention can monitor the DC offset voltage generated in the zero intermediate frequency receiver circuit in real time and feed back the DC offset voltage value into accurate DC offset voltage value no matter whether the DC offset calibration is carried out or not, and can accurately indicate the DC working state of the receiver no matter in chip test, chip analysis or chip batch production chip selection.
The foregoing is merely a preferred embodiment of the invention and is not intended to limit the invention in any manner; the present invention may be readily implemented by those of ordinary skill in the art as illustrated in the accompanying drawings and described above; however, those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention without departing from the scope of the invention as defined by the appended claims; meanwhile, any changes, modifications, and evolutions of the equivalent changes of the above embodiments according to the actual techniques of the present invention are still within the protection scope of the technical solution of the present invention.
Claims (10)
1. Receiver direct current offset monitoring system, its characterized in that: the system comprises an accumulator, a memory and a data processing module, wherein an analog-to-digital converter of a receiver is connected with the accumulator, the accumulator is connected with the memory, the memory is connected with the data processing module, and the data processing module is connected with an SPI (serial peripheral interface) host of the receiver; wherein the content of the first and second substances,
The accumulator is used for accumulating the output signals of the analog-to-digital converter;
the memory is used for dynamically storing the data of the accumulator;
The data processing module is used for extracting and outputting the sign bit of the direct current offset voltage stored in the memory, performing high-order interception on the digital quantization value of the direct current offset voltage and outputting the digital quantization value, comparing the digital quantization value of the direct current offset voltage with an overload threshold value and outputting an overload identifier.
2. The receiver dc offset monitoring system of claim 1, wherein: the data processing module comprises a data processor, a comparator, a plurality of input ports and a plurality of output ports, the data processor is connected with the memory through the input ports, the data processor is connected with the SPI host through the output ports, the data processor is connected with the comparator, and the comparator is connected with the SPI host through the input ports and the output ports.
3. The receiver dc offset monitoring system of claim 2, wherein: the number of the input ports is two, the input ports comprise a first input port and a second input port, the data processor is connected with the storage through the first input port, the comparator is connected with the SPI host through the second input port, the data processor reads data stored in the storage through the first input port, and the comparator receives the overload threshold value set by the SPI host through the second input port.
4. the receiver dc offset monitoring system of claim 2, wherein: the number of the output ports is three, the output ports include a first output port, a second output port and a third output port, the data processor is connected with the SPI host through the first output port and the second output port, the comparator is connected with the SPI host through the third output port, the data processor outputs a sign bit of the dc offset voltage through the first output port, the data processor outputs a high-order intercept result of a digital quantization value of the dc offset voltage through the second output port, and the comparator outputs the overload identifier through the third output port.
5. The receiver dc offset monitoring system of claim 3, wherein: the memory is a random access memory.
6. the method for monitoring the direct current offset of the receiver is characterized by comprising the following steps:
Receiving a signal, and receiving an output signal of an analog-to-digital converter of a receiver;
Accumulating the output signals of the analog-to-digital converter;
Storing the signals, and dynamically storing the accumulated signals;
processing a signal, extracting a sign bit of a stored direct-current offset voltage, performing high-order interception on a digital quantization value of the direct-current offset voltage, and comparing the digital quantization value of the direct-current offset voltage with an overload threshold value;
and outputting a signal, namely outputting the sign bit of the direct current offset voltage, a high bit interception result of the digital quantization value of the direct current offset voltage and an overload identifier.
7. the receiver dc offset monitoring method of claim 6, wherein: in the signal processing step, if the absolute value of the digital quantization value of the direct current offset voltage is greater than the overload threshold, the direct current overload offset is judged.
8. the receiver dc offset monitoring method of claim 6, wherein: the method also comprises a step of receiving a threshold value, wherein the threshold value is received by an overload threshold value set by the SPI host of the receiver.
9. An electronic device, characterized by comprising: a processor;
A memory; and a program, wherein the program is stored in the memory and configured to be executed by the processor, the program comprising instructions for carrying out the method of any one of claims 6-8.
10. a computer-readable storage medium having stored thereon a computer program, characterized in that: the computer program is executed by a processor for performing the method according to any of claims 6-8.
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Cited By (1)
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| CN110572225B (en) | 2022-04-15 |
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