CN110554946B - Operation speed compensation circuit and compensation method thereof - Google Patents
Operation speed compensation circuit and compensation method thereof Download PDFInfo
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- CN110554946B CN110554946B CN201810558400.2A CN201810558400A CN110554946B CN 110554946 B CN110554946 B CN 110554946B CN 201810558400 A CN201810558400 A CN 201810558400A CN 110554946 B CN110554946 B CN 110554946B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
- G06F11/3419—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment by assessing time
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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Abstract
The invention provides an operation speed compensation circuit and a compensation method thereof. The operation speed compensation circuit comprises a power supply selection circuit and an operation speed sensor. The power selection circuit selects one of the first power supply and the second power supply to generate a supply power according to the first control signal. The operation speed sensor generates a first control signal according to the reaction speed of a first detection signal at a first relay signal transmission point of the detection operation circuit. The voltage value of the first power supply is smaller than that of the second power supply, and the operational circuit receives the supply power as the operation power.
Description
Technical Field
The present invention relates to a circuit and a method for compensating an operating speed, and more particularly, to a circuit and a method for compensating an operating speed by adaptively adjusting the size of an operating power supply.
Background
As process technology evolves, the size of semiconductor processes is decreasing. In the small-scale process technology, the influence caused by the variation of the process parameters, especially in the low operating voltage state, can not be effectively overcome by the design mode of the worst case (worst case) in the prior art. Especially, how to simply integrate a circuit capable of detecting and correcting a running-time into an integrated circuit for the time violation (timing) is an important issue for those skilled in the art.
Disclosure of Invention
The invention provides a compensation circuit and a compensation method for operation speed, which dynamically adjust the operation speed to make the circuit operation completed in real time.
The arithmetic speed compensation circuit of the invention comprises a power supply selection circuit and an arithmetic speed sensor. The power selection circuit selects one of the first power supply and the second power supply to generate a supply power according to the first control signal. The operation speed sensor is coupled to a first relay signal transmission point of the operation circuit, and generates a first control signal according to a response speed of a first detection signal at the first relay signal transmission point. The voltage value of the first power supply is smaller than that of the second power supply, and the operational circuit receives the supply power as the operation power.
The operation speed compensation method of the invention comprises the following steps: selecting one of the first power supply and the second power supply to generate a supply power according to the first control signal; and detecting a first detection signal at a first relay signal transmission point of the arithmetic circuit, and generating a first control signal according to the response speed of the first detection signal. The voltage value of the first power supply is smaller than that of the second power supply, and the operational circuit receives the supply power as the operation power.
In view of the above, the present invention adjusts the operation speed of the operation circuit by detecting the response speed of the signal at the relay signal transmission point of the operation circuit. The operation speed of the operation circuit can be adaptively adjusted according to the current operation speed of the operation circuit. The operation circuit can generate effective operation result in real time effectively, and the phenomenon of time violation (timing operation) is avoided.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic diagram of an operation speed compensation circuit according to an embodiment of the invention.
FIG. 2 is a diagram of an operation speed compensation circuit according to another embodiment of the present invention.
Fig. 3A and 3B are waveform diagrams of different operations of the operation speed compensation circuit according to the embodiment of the invention.
FIG. 4 is a diagram illustrating an operation speed compensation circuit according to still another embodiment of the present invention.
FIG. 5 is a flowchart illustrating a method for compensating a computation speed according to an embodiment of the present invention.
Description of the symbols:
100. 200, 400: an operation speed compensation circuit;
110. 210, 410: a power supply selection circuit;
120. 220, 420: an arithmetic speed sensor;
101. 201, 401: an arithmetic circuit;
2011. 2012, 4011, 4012, 4013: a sub-operation circuit;
CTR, CTR1, CTR2: a control signal;
v1, V2, V3: a power source;
VPP: supplying a power source;
IN: inputting a signal;
MP1, MP2: a relay signal transmission point;
DET, DET1, DET2: detecting a signal;
CLK, CLK1, CLK2: a clock signal;
DFF1, DFF2: a trigger;
SW1, SW2: a switch;
IV1: an inverter;
TR1, TR2: a reference time point;
s510, S520: and compensating the operation speed.
Detailed Description
Referring to fig. 1, fig. 1 is a schematic diagram of an operation speed compensation circuit according to an embodiment of the invention. The arithmetic speed compensation circuit 100 includes a power selection circuit 110 and an arithmetic speed sensor 120. The power selection circuit 110 receives a control signal CTR1 and power supplies V1 and V2. The power selection circuit 110 selects one of the power V1 and the power V2 to generate the supply power VPP according to the control signal CTR1. The supply power VPP is supplied to the operational circuit 101 and serves as an operational power supply of the operational circuit 101. The voltage values of the power supply V1 and the power supply V2 are different, and in this embodiment, the voltage value of the power supply V1 may be smaller than the voltage value of the power supply V2, for example, it is obvious that the voltage value of the power supply V2 may be equal to about 1.1 times the voltage value of the power supply V1.
The computation speed sensor 120 is coupled to the relay signal transmission point MP1 of the computation circuit 101. IN the present embodiment, the operation circuit 101 receives an input signal IN and performs an operation on the input signal IN. The arithmetic circuit 101 outputs the result of the arithmetic operation through an output signal OUT. In this embodiment, the operation circuit 101 can be divided into a first part and a second part, wherein the first part and the second part are connected through the relay signal transmission point MP1, and the operation result generated by the first part is provided to the relay signal transmission point MP1, and the second part receives the operation result generated by the first part from the relay signal transmission point MP1 for further operation.
The computation speed sensor 120 receives the detection signal DET (i.e., the computation result generated by the first part) at the relay signal transmission point MP1, and determines the response speed of the detection signal DET. The computation speed sensor 120 generates a control signal CTR1 according to a response speed of the detection signal DET, and transmits the control signal CTR1 to the power selection circuit 110.
Specifically, in the present embodiment, the operation speed sensor 120 may provide the control signal CTR to the power selection circuit 110 at an initial time point when the operation circuit 101 operates, and enable the power selection circuit 110 to provide the power V1 with a relatively low voltage value as the supply power VPP. In this way, the operation circuit 101 can receive the supply power VPP with a relatively low voltage as the operation power and perform the operation. The operational circuit 101 may have lower power consumption.
On the other hand, the arithmetic speed sensor 120 detects the detection signal DET at the relay signal transmission point MP1 in the arithmetic circuit 101, and determines the reaction speed of the detection signal DET from the transition time point of the detection signal DET. In the embodiment of the invention, the operation speed sensor 120 can determine whether the detection signal DET is in a transition state within a predetermined reference time interval. If the operation speed sensor 120 determines that the detection signal DET is transited within the reference time interval, which indicates that the operation speed of the operation circuit 101 cannot meet the design requirement, the operation speed sensor 120 may generate a corresponding control signal CTR (e.g., a first logic level). Correspondingly, the power selection circuit 110 can change the selected power V2 to be the supply power VPP according to the control signal CTR1 equal to the first logic level. Thus, the voltage value of the operating power (equal to the power V2) received by the operation circuit 101 can be increased, and the operation speed of the operation circuit 101 can be increased.
On the contrary, if the operation speed sensor 120 determines that the detection signal DET does not generate the transition phenomenon within the reference time interval, the operation speed of the operation circuit 101 is satisfied with the design requirement. The operation speed sensor 120 maintains the logic level (e.g., the second logic level) of the control signal CTR, and enables the power selection circuit 110 to maintain the power supply V1 as the power supply VPP.
It should be noted that, regarding the transition of the detection signal DET, the computation speed sensor 120 can determine the transition of the detection signal DET by the time point when the detection signal DET transitions from a logic high level to a logic low level or by the time point when the detection signal DET transitions from a logic low level to a logic high level.
Incidentally, the first logic level is opposite to the second logic level, wherein the first logic level may be 0 (or 1), and the second logic level may be 1 (or 0). The correspondence relationship between the logic level of the control signal CTR and the selection operation of the power selection circuit 110 may be determined by a designer, and is not limited.
Further, the setting of the reference time point may be set in accordance with the operation speed of the operation circuit 101 in the ideal state (typical case). The designer may set the operation state of the operational circuit 101 according to actual requirements, and there is no fixed limit.
As can be seen from the above description, the embodiment of the invention adjusts the voltage value of the operating power received by the operation circuit 101 by detecting the response speed of the detection signal DET at the relay signal transmission point MP1 of the operation circuit 101. Therefore, when the operation speed of the operation circuit 101 meets the requirement of the design specification, the operation circuit 101 can be kept operating under the relatively low voltage operation power supply, and the power consumption is kept low. When the operation speed of the operation circuit 101 cannot meet the requirement of the design specification, the operation speed of the operation circuit 101 can be increased by increasing the voltage value of the operation power supply, and the operation speed can meet the requirement of the design specification.
Referring to fig. 2, fig. 2 is a schematic diagram of an operation speed compensation circuit according to another embodiment of the invention. The operation speed compensation circuit 200 includes a power selection circuit 210 and an operation speed sensor 220. The power selection circuit 210 is coupled to the operation circuit 201, and includes switches SW1 and SW2 formed by transistors. The switch SW1 receives a power supply VDD1, is coupled to the operation circuit 201, and is controlled by an inverted signal of the control signal CTR1 to be turned on or off. The switch SW2 receives a power supply VDD2, is coupled to the operation circuit 201, and is directly controlled by the control signal CTR1 to be turned on or off. Wherein, the inverse signal of the control signal CTR1 is generated by the inverter IV 1.
In the embodiment of the invention, the switches SW1 and SW2 are formed by transistors of the same type, so that the switches SW1 and SW2 are not turned on at the same time based on the switches SW1 and SW2 controlled by opposite signals. While the power supply selection circuit 210 selects the output power supply VDD1 as the operation power supply of the operation circuit 201 when the switch SW1 is turned on (the switch SW2 is turned off), and the power supply selection circuit 210 selects the output power supply VDD2 as the operation power supply of the operation circuit 201 when the switch SW2 is turned on (the switch SW1 is turned off).
The operational circuit 201 includes a sub-operational circuit 2011 and a sub-operational circuit 2012, the sub-operational circuit 2011 and the sub-operational circuit 2012 are coupled to each other via a relay signal transmission point MP1, and the sub-operational circuit 2011, the relay signal transmission point MP1 and the sub-operational circuit 2012 are sequentially coupled between an input terminal and an output terminal of the operational circuit 201. In the embodiment of the present invention, the input terminal of the operation circuit 201 is coupled to the flip-flop DFF1, and the output terminal of the operation circuit 201 is coupled to the flip-flop DFF2. The flip-flop DFF1 receives the input signal IN and transmits the input signal IN to the operation circuit 201 according to a transition edge of the clock signal CLK 1. The flip-flop DFF2 receives the output of the operation circuit 201 and transmits the output of the operation circuit 201 according to a transition edge of the clock signal CLK2 to generate the output signal OUT.
It should be noted that the clock signals CLK1 and CLK2 may be the same signal or different signals. The flip-flops DFF1 and DFF2 operate according to the same transition edge (e.g., a positive transition edge or a negative transition edge) of the clock signals CLK1 and CLK2, respectively.
In addition, as to the operation details of the operation speed sensor 220, the operation speed sensor 220 can calculate the time point of the detection signal DET occurring a transition state through a counting operation (a built-in counting circuit (not shown)), and determine whether the time point of the detection signal DET occurring a transition state is earlier than a predetermined reference time point through a comparing circuit (not shown), so as to generate the control signal CTR1. The counting circuit and the comparison circuit can be applied to the field
Analog or digital circuits known to the skilled person may be implemented without fixed limitations. Of course, the above description is only an example, and those skilled in the art may implement the operation speed sensor 220 by other circuit design ways, and the implementation need not be limited to the counting circuit and the comparing circuit.
Referring to fig. 3A and 3B, fig. 3A and 3B are waveform diagrams of different operations of the operation speed compensation circuit according to the embodiment of the invention. In FIG. 3A, the operation speed compensation circuit and the operation circuit therein operate according to the clock signal CLK. At an initial point in time, the detection signal DET is at a logic low level, the control signal CTR1 is set to a logic low level, and the supply power VPP, which is an operation power of the operation circuit, is the power V1 having a relatively low voltage value.
By the detection operation of the operation speed sensor, after the reference time point TR1 and before the operation circuit operates the next data (for example, before the reference time point TR 2), the detection signal DET is transited, and accordingly, the operation speed sensor transits the control signal CTR1 to a logic high level, and causes the voltage selector to select the power supply V2 having a relatively high voltage value as the supply power VPP, thereby increasing the operation speed of the operation circuit. That is, when the detection signal DET transits in the reference time interval between the reference time points TR1 and TR2, the voltage selector may select the power supply V2 with a relatively high voltage value as the supply power VPP, and increase the operating speed of the operational circuit.
When the clock signal CLK enters the next cycle, the control signal CTR1 is restored to the preset logic low level, and causes the voltage selector to select the power supply V1 having a relatively low voltage value as the supply power VPP.
In FIG. 3B, the operation speed compensation circuit and the operation circuit therein operate according to the clock signal CLK. At an initial point in time, the detection signal DET is at a logic low level, the control signal CTR1 is set to a logic low level, and the supply power VPP, which is an operation power of the operation circuit, is the power V1 having a relatively low voltage value.
By detecting operation of the operation speed sensor, after the reference time point TR1 and before the reference time point TR2, the detection signal DET does not transit, and accordingly, the operation speed sensor maintains the control signal CTR1 at a logic low level, and the voltage selector maintains the power supply V1 having a relatively low voltage value as the supply power VPP, and power consumption of the operation circuit is reduced. That is, when the detection signal DET does not transit between the reference time points TR1 and TR2, the voltage selector can maintain the voltage value of the power supply VPP.
Referring to fig. 4, fig. 4 is a schematic diagram of an operation speed compensation circuit according to still another embodiment of the invention. The operation speed compensation circuit 400 includes a power selection circuit 410 and an operation speed sensor 420. The power selection circuit 410 is used for providing a supply power VPP as an operation power for the operation circuit 401 according to the control signals CTR1 and CTR2. The computation speed sensor 420 is used to provide control signals CTR1 and CTR2. In contrast to the previous embodiments, the operation circuit 401 in this embodiment can be divided into three sub-operation circuits 4011, 4012 and 4013. The sub-operation circuits 4011 and 4012 are coupled to each other through a relay signal transmission point MP1, and the sub-operation circuits 4012 and 4013 are coupled to each other through a relay signal transmission point MP 2. The sub-operation circuit 4011, the relay signal transmission point MP1, the sub-operation circuit 4012, the relay signal transmission point MP2, and the sub-operation circuit 4013 are coupled in sequence.
The computation speed sensor 420 can detect the response speeds of the detection signals DET1 and DET2 at the relay signal transmission points MP1 and MP2, respectively, and generate the control signals CTR1 and CTR2 according to the response times of the detection signals DET1 and DET2, respectively. The power selection circuit 410 can select one of the power supplies V1 to V3 to generate the power supply VPP according to the control signals CTR1 and CTR2, wherein the voltage value of the power supply V1 is smaller than the voltage value of the power supply V2, and the voltage value of the power supply V2 is smaller than the voltage value of the power supply V3.
In detail, the operation speed sensor 420 generates the control signal CTR1 according to the response speed (transition time point) of the detection signal DET1, and when the response speed of the detection signal DET1 is too slow, the control signal CTR1 enables the power selection circuit 410 to select the power V2 with a relatively high voltage value as the operation power of the operation circuit 401. Moreover, the operation speed sensor 420 can generate the control signal CTR2 according to the response speed (transition time point) of the detection signal DET2, and when the response speed of the detection signal DET2 is not fast enough, the power selection circuit 410 can select the power V3 with a higher voltage value as the operation power of the operation circuit 401 according to the generated control signal CTR2, so as to ensure that the operation speed of the operation circuit 401 can meet the requirement of the design specification.
Details of the detection of the response speeds of the detection signals DET1 and DET2 and details of the implementation of the power selection operation of the power selection circuit 410 are already described in the foregoing embodiments and implementations, and are not repeated herein.
As can be seen from the above description, the embodiment of the present invention can detect the response speed of the detection signal at the plurality of relay signal transmission points in the operation circuit 401, and provide the switching operation of the multi-stage voltage of the operation power supply to adjust the operation speed of the operation circuit 401. So as to effectively reduce the phenomenon of time violation of the operation circuit.
Referring to fig. 5, fig. 5 is a flowchart illustrating a method for compensating a computation speed according to an embodiment of the invention. In fig. 5, step S510 selects one of the first power source and the second power source to generate the supply power according to the first control signal. In step S520, a first detection signal at a first relay signal transmission point of the arithmetic circuit is detected, and a first control signal is generated according to a response speed of the first detection signal. The voltage value of the first power supply is smaller than that of the second power supply, and the operational circuit receives the supply power as the operation power.
The details of the above steps have been described in the aforementioned embodiments, and are not repeated herein.
In summary, the invention adjusts the voltage value of the operation power received by the operation circuit according to the response speed of the relay signal transmission point by detecting the response speed of the relay signal transmission point of the operation circuit. The voltage value of the operation power supply received by the operation circuit is increased, so that the operation speed of the operation circuit is increased, and the possibility of generating time violation is reduced. Based on the embodiment of the invention, a designer can design the arithmetic circuit based on the ideal state (typical case), thereby effectively reducing the design difficulty of the arithmetic circuit.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (10)
1. An operation speed compensation circuit, comprising:
the power supply selection circuit selects one of the first power supply and the second power supply to generate a supply power supply according to a first control signal; and
an operation speed sensor coupled to a first relay signal transmission point of the operation circuit, for generating the first control signal according to a response speed of a first detection signal at the first relay signal transmission point,
wherein a voltage value of the first power supply is smaller than a voltage value of the second power supply, the arithmetic circuit receiving the supply power as an operation power.
2. The operation speed compensation circuit according to claim 1, wherein the operation speed sensor determines a reaction speed of the detection signal depending on a transition time point of the first detection signal.
3. The operation speed compensation circuit according to claim 2, wherein the operation speed sensor determines whether a transition of the first detection signal occurs in a reference time interval to generate the first control signal.
4. The operation speed compensation circuit according to claim 3, wherein the operation speed sensor generates the first control signal at an initial time point to cause the power supply selection circuit to provide the first power supply as the supply power supply.
5. The operation speed compensation circuit according to claim 4, wherein when the operation speed sensor determines that the first detection signal has a transition in the reference time interval, the operation speed sensor generates the first control signal to cause the power selection circuit to select the second power to generate the supply power; when the operation speed sensor judges that the first detection signal does not generate a transition state in the reference time interval, the operation speed sensor generates the first control signal, so that the power supply selection circuit keeps selecting the first power supply to generate the supply power supply.
6. The operation speed compensation circuit of claim 1, wherein the operation circuit comprises a first sub-operation circuit and a second sub-operation circuit, wherein the first sub-operation circuit, the first relay signal transmission point and the second sub-operation circuit are coupled in sequence.
7. The operation speed compensation circuit according to claim 6, wherein the operation circuit further comprises:
a third sub-operational circuit coupled to the second sub-operational circuit through a second relay signal transmission point;
the operation speed sensor is coupled to the second relay signal transmission point, and generates a second control signal according to a response speed of a second detection signal at the second relay signal transmission point, and the power selection circuit determines whether to select a third power source to generate the supply power according to the second control signal, wherein a voltage value of the third power source is greater than a voltage value of the second power source.
8. The operation speed compensation circuit according to claim 1, wherein the power supply selection circuit comprises:
the first switch receives the first power supply, is coupled to the operational circuit and is controlled by the first control signal; and
a second switch receiving the second power, coupled to the operational circuit, and controlled by the first control signal,
wherein at most one of the first switch and the second switch is turned on.
9. The operation speed compensation circuit according to claim 1, wherein a voltage value of the first power supply is smaller than a voltage value of the second power supply.
10. An operation speed compensation method, comprising:
selecting one of a first power supply and a second power supply to generate a supply power according to a first control signal;
detecting a first detection signal at a first relay signal transmission point of an arithmetic circuit, generating the first control signal according to a response speed of the first detection signal,
wherein a voltage value of the first power supply is smaller than a voltage value of the second power supply, the arithmetic circuit receiving the supply power as an operation power.
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| CN201810558400.2A CN110554946B (en) | 2018-06-01 | 2018-06-01 | Operation speed compensation circuit and compensation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102332749A (en) * | 2010-12-31 | 2012-01-25 | 上海源致信息技术有限公司 | Control equipment and power supply management device and method thereof |
| CN105572603A (en) * | 2014-10-17 | 2016-05-11 | 财团法人金属工业研究发展中心 | Power management system and detector for power supply module of power management system |
| CN106681549A (en) * | 2015-11-06 | 2017-05-17 | 财团法人工业技术研究院 | Touch device and noise compensation circuit and noise compensation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7667497B2 (en) * | 2007-10-30 | 2010-02-23 | President And Fellows Of Harvard College | Process variation tolerant circuit with voltage interpolation and variable latency |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102332749A (en) * | 2010-12-31 | 2012-01-25 | 上海源致信息技术有限公司 | Control equipment and power supply management device and method thereof |
| CN105572603A (en) * | 2014-10-17 | 2016-05-11 | 财团法人金属工业研究发展中心 | Power management system and detector for power supply module of power management system |
| CN106681549A (en) * | 2015-11-06 | 2017-05-17 | 财团法人工业技术研究院 | Touch device and noise compensation circuit and noise compensation method thereof |
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