CN110554833B

CN110554833B - Parallel processing IO commands in a memory device

Info

Publication number: CN110554833B
Application number: CN201810548050.1A
Authority: CN
Inventors: 金石; 杨腾; 盛亮
Original assignee: Beijing Starblaze Technology Co ltd
Current assignee: Beijing Starblaze Technology Co ltd
Priority date: 2018-05-31
Filing date: 2018-05-31
Publication date: 2023-09-19
Anticipated expiration: 2038-05-31
Also published as: CN110554833A

Abstract

The application discloses parallel processing of IO commands in a memory device. The disclosed read command processing method includes the steps of: acquiring a read command, and splitting the read command into a plurality of subcommands; acquiring a physical address corresponding to a logical address accessed by a subcommand; adding the subcommand to a subcommand set corresponding to the logic unit accessed by the subcommand; accessing a subcommand set, and acquiring subcommands from the subcommand set; accessing the nonvolatile memory according to the physical address of the subcommand; in response to all subcommand processing split from the read command being completed, the read command processing is indicated as being completed.

Description

Parallel processing IO commands in a memory device

Technical Field

The present application relates to solid state storage devices, and in particular to parallel processing IO commands in a storage device.

Background

FIG. 1 illustrates a block diagram of a solid state storage device. The solid state storage device 102 is coupled to a host for providing storage capability for the host. The host and solid state storage device 102 may be coupled by a variety of means including, but not limited to, connecting the host to the solid state storage device 102 via, for example, SATA (Serial Advanced Technology Attachment ), SCSI (Small Computer System Interface, small computer system interface), SAS (Serial Attached SCSI ), IDE (Integrated Drive Electronics, integrated drive electronics), USB (Universal Serial Bus ), PCIE (Peripheral Component Interconnect Express, PCIE, peripheral component interconnect Express), NVMe (NVM Express), ethernet, fibre channel, wireless communications network, and the like. The host may be an information processing device capable of communicating with the storage device in the manner described above, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, or the like. The storage device 102 includes a media interface 103, a control unit 104, one or more nonvolatile memories NVM 105, and an external memory DRAM (Dynamic Random Access Memory ) 110.

NAND flash memory, phase change memory, feRAM (Ferroelectric RAM, ferroelectric memory), MRAM (MagneticRandom Access Memory, magnetoresistive memory), RRAM (Resistive Random Access Memory, resistive memory), and the like are common NVM.

The interface 103 may be adapted to exchange data with a host by way of, for example, SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc.

The control unit 104 is used to control data transfer among the interface 103, NVM chip 105, and DRAM 110, and also for memory management, host logical address to flash physical address mapping, erase balancing, bad block management, etc. The control component 104 can be implemented in a variety of ways, such as software, hardware, firmware, or a combination thereof, for example, the control component 104 can be in the form of an FPGA (Field-programmable gate array, field programmable gate array), an ASIC (Application Specific Integrated Circuit, application-specific integrated circuit), or a combination thereof. The control component 104 may also include a processor or controller in which software is executed to manipulate the hardware of the control component 104 to process IO (Input/Output) commands. Control unit 104 may also be coupled to DRAM 110 and may access data of DRAM 110. FTL tables and/or cached data of IO commands may be stored in the DRAM.

The control section 104 includes a flash interface controller (or referred to as a media interface controller, a flash channel controller) that is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in a manner conforming to an interface protocol of the NVM chip 105 to operate the NVM chip 105 and receive a command execution result output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", and the like.

The memory Target (Target) is one or more Logical Units (LUNs) of shared CE (Chip Enable) signals within the NAND flash package. One or more dies (Die) may be included within the NAND flash package. Typically, the logic unit corresponds to a single die. The logic cell may include multiple planes (planes). Multiple planes within a logic unit may be accessed in parallel, while multiple logic units within a NAND flash memory chip may execute commands and report status independently of each other.

Data is typically stored and read on a storage medium on a page basis. While data is erased in blocks. A block (also called a physical block) contains a plurality of pages. A block contains a plurality of pages. Pages on a storage medium (referred to as physical pages) have a fixed size, e.g., 17664 bytes. The physical pages may also have other sizes.

In solid state storage devices, FTL (Flash Translation Layer ) is utilized to maintain mapping information from logical addresses to physical addresses. The logical addresses constitute the storage space of the solid state storage device as perceived by upper level software such as the operating system. The physical address is an address for accessing a physical storage unit of the solid state storage device. Address mapping may also be implemented in the related art using an intermediate address modality. For example, logical addresses are mapped to intermediate addresses, which in turn are further mapped to physical addresses.

The table structure storing mapping information from logical addresses to physical addresses is called FTL table. FTL tables are important metadata in solid state storage devices. Typically, the data items of the FTL table record address mapping relationships in units of data pages in the solid-state storage device.

FTL tables include a plurality of FTL table entries (or entries). In one case, a correspondence of one logical page address to one physical page is recorded in each FTL table entry. In another case, correspondence between consecutive logical page addresses and consecutive physical pages is recorded in each FTL table entry. In yet another case, a correspondence of logical block addresses to physical block addresses is recorded in each FTL table entry. In still another case, mapping relation between logical block address and physical block address, and/or mapping relation between logical page address and physical page address are recorded in FTL table.

A large block includes physical blocks from each of a plurality of Logical Units (LUNs), also referred to as a logical unit group. Each logical unit may provide a physical block for a large block. For example, in the schematic diagram of a large block shown in FIG. 2, the large block is constructed on every 16 Logical Units (LUNs). Each large block includes 16 physical blocks from 16 Logical Units (LUNs), respectively. In the example of FIG. 2, chunk 0 includes physical chunk 0 from each of the 16 Logical Units (LUNs), while chunk 1 includes physical chunk 1 from each Logical Unit (LUNs). The chunks may also be constructed in a variety of other ways.

For example, page stripes are constructed in large blocks, with physical pages of the same physical address in each Logical Unit (LUN) constituting a "page stripe". In FIG. 2, physical pages P0-0, P0-1, … … and P0-x form page stripe 0, where physical pages P0-0, P0-1, … … are used to store user data and physical pages P0-x are used to store parity data calculated from all user data within the stripe. Similarly, in FIG. 2, physical pages P2-0, P2-1 and … …, and P2-x constitute page stripe 2. The physical page used to store the parity data may be located anywhere in the page stripe. As yet another example, in FIG. 3A of the China patent application No. 201710752321.0 and the related description of FIG. 3A in its specification, a further form of construction is provided in large blocks. As yet another example, each physical page of a page stripe is used to store user data.

In yet another example, page stripes are not used in the large block, but rather data is written to physical pages of physical blocks of the large block.

Disclosure of Invention

The memory device needs to process tens of thousands to millions of IO commands per second. At the same time, hundreds of IO commands are being processed in the storage device. An efficient parallel processing architecture is needed to meet the demands of the memory devices for parallel processing of IO commands.

According to a first aspect of the present application, there is provided a first read command processing method according to the first aspect of the present application, comprising the steps of: acquiring a read command, and splitting the read command into a plurality of subcommands; acquiring a physical address corresponding to a logical address accessed by a subcommand; adding the subcommand to a subcommand set corresponding to the logic unit accessed by the subcommand; accessing a subcommand set, and acquiring subcommands from the subcommand set; accessing the nonvolatile memory according to the physical address of the subcommand; in response to all subcommand processing split from the read command being completed, the read command processing is indicated as being completed.

According to a first read command processing method of the first aspect of the present application, there is provided a second read command processing method according to the first aspect of the present application, wherein the method further includes, in response to the sub-command being processed, receiving data read out from the nonvolatile memory according to the sub-command.

According to a first or second read command processing method of the first aspect of the present application, there is provided a third read command processing method according to the first aspect of the present application, wherein a plurality of logic units each including a plurality of physical blocks are included in the nonvolatile memory.

The read command processing method according to any one of the first to third aspects of the present application provides the fourth read command processing method according to the first aspect of the present application, wherein the subcommand set is accessed periodically or in response to the subcommand set being added with subcommands.

The read command processing method according to any one of the first to fourth aspects of the present application provides the fifth read command processing method according to the first aspect of the present application, wherein an execution result of the subcommand is acquired, and the subcommand whose execution is completed is deleted from the subcommand set.

According to a read command processing method of any one of the first to fifth aspects of the present application, there is provided a sixth read command processing method according to the first aspect of the present application, wherein a node corresponding to each logical unit is recorded in a memory.

According to a sixth read command processing method of the first aspect of the present application, there is provided the seventh read command processing method according to the first aspect of the present application, wherein each node includes a subcommand set in which subcommands to be processed are recorded.

According to a seventh read command processing method of the first aspect of the present application, there is provided an eighth read command processing method of the first aspect of the present application, wherein the sub-command to be processed recorded in the first sub-command set accesses the first logic unit, and the sub-command set corresponds to the logic units one by one, and the first sub-command set corresponds to the first logic unit.

According to a read command processing method of any one of the first to eighth aspects of the present application, there is provided a ninth read command processing method according to the first aspect of the present application, wherein a logical unit accessed by a subcommand is identified according to an acquired physical address corresponding to a logical address accessed by the subcommand, and the subcommand is added to a subcommand set of nodes corresponding to the logical unit accessed by the subcommand.

According to a tenth read command processing method according to the first aspect of the present application, there is provided the read command processing method according to the first aspect of the present application, wherein, for a plurality of nodes, subcommand sets of the respective nodes are accessed in turn, subcommands to be processed are acquired from the respective subcommand sets and processed.

The read command processing method according to any one of the first to ninth aspects of the present application provides the eleventh read command processing method according to the first aspect of the present application, wherein the logic unit is alternately queried as to whether or not the sub-command can be received.

According to an eleventh read command processing method of the first aspect of the present application, there is provided the twelfth read command processing method of the first aspect of the present application, wherein if the logic unit is capable of receiving the subcommand, the subcommand is acquired from the subcommand set included in the node corresponding to the logic unit.

According to an eleventh read command processing method of the first aspect of the present application, there is provided the thirteenth read command processing method of the first aspect of the present application, wherein if a logical unit cannot receive a subcommand, it is queried whether another logical unit can receive the subcommand.

According to a second aspect of the present application, there is provided a first write command processing method according to the second aspect of the present application, comprising the steps of: acquiring a write command, and splitting the write command into a plurality of subcommands; allocating an active big block for the subcommand, and recording the subcommand in a subcommand set corresponding to the active big block allocated for the subcommand; acquiring a write subcommand from a subcommand set of the active large block, and accessing the nonvolatile memory according to the acquired subcommand; in response to identifying that all subcommands of the write command are processed to completion, the write command processing is indicated to be complete.

According to a first write command processing method of a second aspect of the present application, there is provided a second write command processing method according to the second aspect of the present application, wherein a subcommand to be written to a first active large block is recorded in a subcommand set corresponding to the first active large block.

According to the first or second write command processing method of the second aspect of the present application, there is provided a third write command processing method according to the second aspect of the present application, further comprising: the subcommand is assigned a physical address.

According to a third aspect of the present application, there is provided a write command processing method according to the third aspect of the present application, wherein the sub-command to be written with data to the first logical unit is recorded in the sub-command set corresponding to the first logical unit.

According to a second write command processing method of a second aspect of the present application, there is provided a fifth write command processing method according to the second aspect of the present application, wherein the active large block is a large block capable of or being written with data, and the inactive large block is a large block filled with data or blank.

A write command processing method according to any one of the first to fifth aspects of the present application provides the sixth write command processing method according to the second aspect of the present application, wherein, in response to the sub-command being assigned a physical address, the nonvolatile memory is accessed according to the physical address of the sub-command.

According to a first write command processing method of a second aspect of the present application, there is provided a seventh write command processing method according to the second aspect of the present application, wherein a corresponding node is provided for each logical unit, the node including a sub-command set corresponding to the logical unit.

According to a seventh write command processing method of the second aspect of the present application, there is provided an eighth write command processing method according to the second aspect of the present application, wherein a set of subcommands corresponding to the logic units are in one-to-one correspondence with the logic units; the subcommand sets corresponding to the active large blocks are in one-to-one correspondence with the active large blocks.

According to a ninth write command processing method according to the second aspect of the present application, there is provided the write command processing method according to the first to eighth aspects of the present application, wherein the subcommand is added to a subcommand set corresponding to a logical unit accessed by the subcommand in response to the logical unit failing to respond to the subcommand.

The write command processing method according to any one of the first to ninth aspects of the present application provides the tenth write command processing method according to the second aspect of the present application, wherein further comprising: the subcommand is deleted from the subcommand set corresponding to the active chunk.

According to a tenth write command processing method of the second aspect of the present application, there is provided an eleventh write command processing method according to the second aspect of the present application, wherein sub-commands are acquired from a sub-command set corresponding to the logic unit periodically or alternately, and the nonvolatile memory is accessed according to the acquired sub-commands.

According to a tenth to eleventh aspect of the present application, there is provided a twelfth write command processing method according to the second aspect of the present application, wherein whether the first logic unit can receive the subcommand is queried, if the first logic unit can receive the subcommand, the subcommand is obtained from the subcommand set corresponding to the first logic unit, and the nonvolatile memory is accessed according to the obtained subcommand.

According to a twelfth write command processing method of the second aspect of the present application, there is provided the thirteenth write command processing method of the second aspect of the present application, wherein if the first logical unit cannot receive the subcommand, it is queried whether the other logical unit can receive the subcommand.

According to a fourteenth write command processing method of any one of tenth to twelfth aspects of the present application, there is provided the fourteenth write command processing method according to the second aspect of the present application, wherein the first subcommand is deleted from the subcommand set corresponding to the logical unit in response to the first subcommand accessing the nonvolatile memory being processed.

According to a third aspect of the present application, there is provided the first control section according to the third aspect of the present application, wherein the first control section includes a host interface, a media interface, a command splitting section, an address converting section, a subcommand processing section; the host interface is used for exchanging commands and data with the host; a command splitting component coupled to the host interface for splitting the read command into a plurality of subcommands; the address conversion component is respectively coupled with the command splitting component and the external memory and is used for acquiring a physical address corresponding to the logical address accessed by the subcommand and providing the physical address for the subcommand processing component; the subcommand processing component is coupled with the address conversion component, adds the subcommand to a subcommand set corresponding to the logic unit accessed by the subcommand, acquires the subcommand from the subcommand set and sends the subcommand to the medium interface; the media interface is coupled to the subcommand processing means for accessing the non-volatile memory in accordance with the physical address of the subcommand.

According to a first control unit of a third aspect of the present application, there is provided a second control unit according to the third aspect of the present application, wherein the subcommand processing unit adds the subcommand to a subcommand set corresponding to a logical unit accessed by the subcommand in response to the inability of the media interface to receive the subcommand.

According to a third aspect of the present application, there is provided the control section according to the third aspect of the present application, wherein the subcommand processing section alternately accesses subcommand sets corresponding to the respective logic units, acquires subcommands to be processed from the subcommand sets, and processes the subcommands.

The control section according to any one of the first to third aspects of the present application provides the fourth control section according to the third aspect of the present application, wherein the subcommand processing section inquires the state of the medium interface, and acquires the subcommand from the subcommand set.

According to a fourth control unit of the third aspect of the present application, there is provided the fifth control unit of the third aspect of the present application, wherein the subcommand processing unit alternately inquires whether each logic unit can receive the subcommand, and if the medium interface indicates that the logic unit can receive the subcommand, obtains the subcommand from the subcommand set corresponding to the logic unit.

According to a fourth control unit of the third aspect of the present application, there is provided the sixth control unit of the third aspect of the present application, wherein if the medium interface indicates that the logical unit cannot receive the subcommand, the subcommand processing unit inquires whether the other logical unit can receive the subcommand.

The control section according to any one of the first to sixth aspects of the present application provides the seventh control section according to the third aspect of the present application, wherein the subcommand processing section acquires the execution result of the subcommand from the media interface and deletes the subcommand whose execution is completed from the subcommand set.

According to a fourth aspect of the present application, there is provided a first storage device according to the fourth aspect of the present application, comprising a control section and a nonvolatile memory, the control section being the first to seventh control sections according to the third aspect of the present application.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to these drawings for a person having ordinary skill in the art.

FIG. 1 is a block diagram of a solid state storage device of the related art;

FIG. 2 shows a schematic diagram of the internal structure of a large block;

FIG. 3 is a schematic diagram of a memory device according to the present application for processing a read command;

FIG. 4 is a flow chart of a memory device processing a read command according to the present application;

FIG. 5 is a schematic diagram of a memory device processing a write command according to the present application;

FIG. 6 is a flow chart of a memory device processing a write command according to the present application;

101-an interface; 103-a media interface; 104-a control unit; 105-a non-volatile memory;

110-an external memory; 106-a host interface; 107—command completion component;

108-a command splitting component; 109-address conversion means; 111-subcommand processing unit.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

FIG. 3 is a schematic diagram of a memory device processing a read command according to an embodiment of the application. The control section 104 shown in fig. 3 includes a host interface 106, a command splitting section 108, an address converting section 109, a subcommand processing section 111, a command completing section 107, and a media interface 103 for accessing the NVM chip 105. The command splitting section 108, address converting section 109, subcommand processing section 111, command completing section 107 may all be implemented by a CPU, dedicated hardware, or a combination thereof.

The host interface is used for exchanging commands and data with the host. As an example, the host communicates with the storage device via an NVMe/PCIe protocol, the host interface processes PCIe protocol packets, extracts NVMe protocol commands, and returns processing results of the NVMe protocol commands to the host.

The command splitting section 108 is coupled to the host interface for receiving the IO command sent by the host to the storage device, splitting the IO command into one or more sub-commands (1) accessing data units having a specified size (e.g. 4 KB), and providing the sub-commands to the address translation section 109 (2).

The control component 104 is also coupled to external memory (e.g., DRAM 110). The external memory 110 stores FTL tables. The address conversion section 109 processes the subcommand by using the FTL table.

For a subcommand (read subcommand) obtained by the read command, the address conversion section 109 refers to the FTL table with the logical address accessed by the read subcommand, and obtains a physical address (3) corresponding to the logical address.

The sub-command processing section 111 transmits the sub-command having obtained the physical address to the media interface 103, and accesses the NVM chip (6) by the media interface 103 according to the physical address. The sub-command processing section 111 also receives data read out from the NVM chip according to the sub-command in response to the sub-command being processed by the media interface 103.

The command completion unit 107 recognizes whether all sub-commands split from the same IO command are process completed (7). In response to all subcommands split from the same IO command being processed, the command completion unit 107 indicates to the IO command issuer that the read command processing is complete through the host interface (8).

One or more NVM chips are coupled to the media interface 103 of the control component 104. The NVM chip includes logic cells. FIG. 3 illustrates a plurality of logical units (LUN 0, LUN 1, LUN 2, and LUN 3) coupled to the media interface 103. Each logical unit includes a plurality of physical blocks.

According to an embodiment of the present application, the control unit 104 sets a corresponding node for each logic unit coupled thereto. Referring to FIG. 3, node 0 corresponds to LUN 0, node 1 corresponds to LUN 1, node 2 corresponds to LUN 2, and node 3 corresponds to LUN 3. Illustratively, each node is recorded in memory.

Each node has a subcommand set in which subcommands to be processed are recorded, and subcommands in the subcommand set only access LUNs corresponding to nodes to which the subcommand set belongs. For example, in FIG. 3, all of the subcommands in the subcommand set for node 0 are subcommands that access LUN 0.

For the subcommand received from the command splitting section 108, the address converting section 109, after acquiring the physical address from the FTL table for the subcommand, identifies the LUN (for example, LUN 1) accessed by the subcommand from the physical address, and adds the subcommand (together with its physical address) to the subcommand set of the node (node 1) corresponding to the LUN accessed by the subcommand (4).

The subcommand processing section 111 accesses the subcommand set corresponding to the logical unit periodically or in response to the subcommand set being added with subcommands, acquires subcommands from the subcommand set corresponding to the logical unit, and sends the subcommands to the media interface 103 for processing (5). Alternatively, for a plurality of nodes, sub-command sets of the respective nodes are accessed in turn, sub-commands to be processed are acquired from the respective sub-command sets and processed. Still alternatively, the subcommand processing unit 111 queries the state of the media interface 103, e.g., alternately queries whether each LUN can receive a read subcommand. In response to the media interface 103 indicating that a certain LUN may receive a read subcommand, the read subcommand is obtained from a set of subcommands included by the node corresponding to the LUN. If the media interface 103 indicates that a read subcommand is not currently received by a LUN (e.g., a program or erase command is being processed), the subcommand processing unit 111 queries whether another LUN can receive the read subcommand.

The sub-command processing section 111 acquires the execution result of the sub-command from the media interface 103, and deletes the sub-command whose execution is completed from the sub-command set.

By using the node record to access the read subcommands of the respective LUNs, the control element 104 can process multiple read subcommands simultaneously. The command splitting section 108 and the address converting section 109 serve as producers of nodes and their subcommand sets to which subcommands to be processed are added, and the subcommand processing section 111 serves as consumers of the nodes and their subcommand sets, acquires subcommands from the subcommand sets, and removes subcommands from the subcommand sets after processing. Thus, a plurality of subcommands waiting to be processed by the subcommand processing section 111 and being processed by the media interface 103 are recorded in the subcommand set.

FIG. 4 is a flow chart of a memory device processing a read command according to an embodiment of the application.

The command splitting component 108 splits the received read command into a plurality of subcommands (410). For the subcommand received from the command splitting section 108, the address converting section 109 refers to the FTL table with the logical address accessed by the read subcommand, and obtains the physical address corresponding to the logical address (420).

For the subcommand received from the command splitting section 108, the address converting section 109, after acquiring the physical address from the FTL table for the subcommand, identifies the logical unit (e.g., LUN 1) accessed by the subcommand from the physical address, and adds the subcommand (together with its physical address) to the subcommand set of the node (node 1) corresponding to the logical unit accessed by the subcommand (430).

The subcommand processing section 111 accesses the subcommand set corresponding to the logical unit periodically or in response to the subcommand set being added with subcommands, acquires the subcommand from the subcommand set corresponding to the logical unit (440), and sends the subcommand to the media interface 103 for processing.

The media interface 103 accesses the non-volatile memory according to the physical address of the subcommand (450), and the subcommand processing unit 111 also receives data read from the NVM chip according to the subcommand in response to the subcommand being processed by the media interface 103. The command completion component identifies whether all sub-commands split from the same IO command are processed, and in response to all sub-commands split from the same IO command being processed, the command completion component 107 indicates read command processing completion to the IO command issuer through the host interface (460).

According to an embodiment of the present application, step 430 and step 440 may be performed in parallel. For example, by adding one or more subcommands to a subcommand set corresponding to the logical unit accessed by the subcommand, via step 430; and sub-commands are fetched from the sub-command set and subsequently processed, via step 440. Still as having, the address conversion section 109 performs step 430, and the subcommand processing section performs step 440.

By providing a set of subcommands, the control unit can process multiple read commands and multiple subcommands from multiple read commands simultaneously. And by setting subcommand sets for each logic unit, the parallelism of the logic unit processing commands is utilized, so that subcommands are conveniently scheduled for idle logic units.

FIG. 5 is a schematic diagram of a memory device processing a write command according to an embodiment of the application.

The command splitting section 108 is coupled to the host interface for receiving a write IO command sent by the host to the storage device, splitting the write IO command into one or more sub-commands (1) accessing data units having a specified size (e.g., 4 KB), and providing the sub-commands to the address translation section 109 (2).

Fig. 5 illustrates a plurality of logical units (LUN 0, LUN, … …, and LUN 3) coupled to the media interface 103. Each logical unit includes a plurality of physical blocks. Fig. 5 also shows a plurality of chunks (chunk 0, chunk 1, chunk 2, and chunk 3). Chunk 0, chunk 1, and chunk 3 are active, meaning that these active chunks are being written to data, or that these active chunks may be written to data. According to an embodiment of the application, the control unit 104 maintains several active large blocks at the same time, e.g. 3, 5 or other suitable numbers. The control unit 104 records each active chunk currently, e.g., the control unit 104 records active chunk 0 as chunk 0, active chunk 1 as chunk 1, active chunk 2 as chunk 2, etc. in memory. The control unit 104 also records a set of subcommands in memory for each active chunk, with a write subcommand in the set of subcommands corresponding to each active chunk to write data to the active chunk.

With continued reference to FIG. 5, chunk 2 is inactive, meaning that chunk 2 has been written with data, or chunk 2 is blank and has not been used to carry data for a write command. When an active chunk is full of data, the active chunk becomes inactive. And the control component 104 can select one or more inactive empty chunks to become active chunks. The active chunks do not need to be physically adjacent to each other.

For a subcommand (write subcommand) derived from a write command, address translation unit 109 assigns one of the active chunks (4) to the write subcommand, with the assigned active chunk carrying the data to be written by the write subcommand. As a result of allocating the active chunk, the address conversion section 109 records the write subcommand in the subcommand set corresponding to the allocated active chunk.

Illustratively, for write subcommand 1, active chunk 0 is assigned thereto, and write subcommand 1 is recorded in the subcommand set of active chunk 0; for write subcommand 2, active chunk 0 is allocated for it, and write subcommand 2 is recorded in the subcommand set of active chunk 0; and; for write subcommand 3, active chunk 1 is assigned and write subcommand 3 is recorded in the subcommand set of active chunk 1. A variety of strategies may be used to allocate active chunks for write subcommands.

The address translation unit 109 also allocates a physical address for a write subcommand in the subcommand set of the active chunk to which the allocated physical address belongs (5). For example, the physical address allocated for a write subcommand in the subcommand set of active chunk 2 is the physical address from chunk 3.

As another example, a write subcommand is to write a large block of data of a size different from the physical page of the NVM chip, while the sum of its data to be written is assigned a physical address for multiple write subcommands of the physical page size. For example, a write subcommand will have a data size of 4KB and a physical page size of 16KB, and when at least 4 write subcommands appear in the subcommand set of an active chunk, the 4 write subcommands are assigned the physical addresses of the same physical page on the active chunk. For another example, an NVM chip supports Multi-Plane (Multi-Plane) operations in which data can be written simultaneously to multiple physical pages (e.g., 4) belonging to multiple planes (e.g., 4) in a single Multi-Plane programming operation, then when at least 16 write subcommands occur in a subcommand set of an active chunk, the 16 write subcommands are assigned physical addresses of the 4 physical pages of the 4 planes on the active chunk.

In response to the physical address being allocated for the write subcommand, the address conversion section 109 supplies the write subcommand to the subcommand processing section 111 (6). The subcommand processing section 111 transmits the subcommand for which the physical address is obtained to the media interface 103, accesses the NVM chip by the media interface 103 according to the physical address, and deletes the subcommand from the subcommand set corresponding to the active large block.

The subcommand processing section 111 also recognizes that subcommand processing is completed by the media interface 103 and notifies the command completion section 107.

The command completion unit 107 recognizes whether all write sub-commands split from the same IO command are processed to completion. In response to all subcommands split from the same IO command being processed, the command completion unit 107 indicates to the IO command issuer that the write command processing is completed through the host interface.

The control unit 104 also sets a corresponding node for each logic unit to which it is coupled. Referring to FIG. 5, node 0 corresponds to LUN 0, node 1 corresponds to LUN 1 … …, and node n corresponds to LUN n. By way of example, each node is recorded in memory. Each node has a subcommand set corresponding to the logical unit, wherein subcommands for writing data to the logical unit are recorded, and subcommands in the subcommand set access LUNs corresponding to nodes to which the subcommand set belongs. For example, in FIG. 5, all of the subcommands in the subcommand set for node 0 are subcommands that access LUN 0.

In some cases, when the subcommand processing section 111 is to transmit a write subcommand for which a physical address is obtained to the media interface 103, a logical unit to which the subcommand is to be accessed temporarily cannot receive the write subcommand. In response to the logical unit failing to respond to the write subcommand, subcommand processing unit 111 adds the write subcommand (along with its physical address) to the subcommand set of nodes corresponding to the logical unit accessed by the write subcommand (7).

The subcommand processing section 111 also periodically accesses the subcommand set of each node, acquires a write subcommand from the subcommand set of each node, and sends the subcommand to the media interface 103 for processing (8).

Alternatively, for a plurality of nodes, sub-command sets of the respective nodes are accessed in turn, sub-commands to be processed are acquired from the respective sub-command sets and processed.

Still alternatively, the subcommand processing unit 111 queries the state of the media interface 103, e.g., alternately queries whether each LUN can receive a write subcommand. In response to the media interface 103 indicating that a certain LUN may receive a write subcommand, the write subcommand is obtained from a set of subcommands included by the node corresponding to the LUN. If the media interface 103 indicates that a certain LUN is currently unable to receive a write subcommand (e.g., a program or erase command is being processed), the subcommand processing unit 111 queries whether another LUN can receive the write subcommand.

The subcommand processing section 111 acquires the execution result of the subcommand from the media interface 103 (9), and also deletes the subcommand, which has been completed in execution, from the subcommand set corresponding to the logical unit for the write subcommand acquired from the subcommand set of the node.

According to the embodiment shown in FIG. 5, by recording active blobs, write sub-commands are assigned to active blobs, aggregating data written to a solid state storage device to each of a plurality of blobs, helping to promote locality of data. By the sub-command set of the active large block, matching when the size of the write sub-command is inconsistent with the size of the physical page is also realized, and a plurality of write sub-commands are gathered into the size of the physical page. According to the embodiment of FIG. 5, control component 104 is also enabled to process multiple write subcommands simultaneously by using node records to access write subcommands of respective LUNs. The address conversion section 109 serves as a producer of a node and its subcommand set to which subcommands to be processed are added, and the subcommand processing section 111 serves as a consumer of the node and its subcommand set, acquires subcommands from the subcommand set, and removes the subcommand from the subcommand set corresponding to the logical unit after processing.

FIG. 6 is a flow chart of a memory device processing a write command according to an embodiment of the application.

The command splitting section 108 receives a write IO command sent from the host to the storage device, splits the write IO command into one or more sub-commands (610) accessing a data unit having a specified size (e.g., 4 KB), and supplies the sub-commands to the address converting section 109.

Address translation component 109 allocates an active chunk for the subcommand, records the subcommand in the subcommand set corresponding to the active chunk allocated for it (620). Further, a physical address is allocated to the subcommand, and the physical address allocated to the subcommand is recorded in the subcommand set corresponding to the active large block together with the subcommand.

The write subcommand is acquired from the subcommand set of the active large block, the address conversion section 109 supplies the subcommand to the subcommand processing section 111, the subcommand processing section 111 sends the subcommand for which the physical address is acquired to the media interface 103, and the nonvolatile memory is accessed by the media interface 103 according to the acquired subcommand (630).

The subcommand processing section 111 also recognizes through the medium 103 whether or not the logic unit accessed by the subcommand can receive the subcommand. If the logic unit is capable of receiving the subcommand, subcommand processing unit 111 further obtains the execution result of the subcommand from the logic unit (640).

In response to completion of all subcommands split from the same IO command processing section according to the execution result of the subcommand supplied from the subcommand processing section, the command completion section 107 indicates completion of write command processing to the IO command issuer through the host interface (650).

When the subcommand processing section 111 is to transmit the write subcommand for which the physical address is obtained to the media interface 103, the logical unit to which the subcommand is to be accessed temporarily cannot receive the write subcommand. In response to the logical unit failing to respond to the write subcommand, subcommand processing unit 111 adds the write subcommand (along with its physical address) to the subcommand set of nodes corresponding to the logical unit accessed by the write subcommand (660).

The subcommand processing unit 111 acquires subcommands 670 from the subcommand set corresponding to the logical units periodically or alternately, and the subcommand processing unit 111 sends the subcommand having acquired the physical addresses to the media interface 103 to access the nonvolatile memory 680.

The sub-command processing section 111 inquires whether the logic unit can respond to the sub-command acquired from the sub-command set corresponding to the logic unit, and if so, performs steps 640 and 650. If not, the subcommand is added as a pending subcommand to the subcommand set corresponding to the logical unit accessed by the subcommand (i.e., step 660), and steps 670 and 680 are continued.

It will be appreciated that although in the embodiments according to fig. 3 and 5, respective operations are provided to be performed by the command splitting section 108, the address translating section 109, the subcommand processing section 111, the command completing section 107, these operations may be performed by different sections, and may also be performed by one or more program segments running on the CPU.

While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application. It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A method of processing a read command, comprising the steps of:

acquiring a read command, and splitting the read command into a plurality of subcommands;

acquiring a physical address corresponding to a logical address accessed by a subcommand;

adding the subcommand to a subcommand set corresponding to the logic unit accessed by the subcommand;

accessing subcommand sets corresponding to each logic unit, and acquiring subcommands from each subcommand set;

accessing a nonvolatile memory according to the obtained physical address of each sub-command;

in response to all subcommand processing split from the read command being completed, the read command processing is indicated as being completed.

2. The method of claim 1, wherein the set of subcommands is accessed periodically or in response to the set of subcommands being added with subcommands.

3. The method according to any one of claims 1 to 2, wherein the logical unit accessed by the subcommand is identified based on the acquired physical address corresponding to the logical address accessed by the subcommand, and the subcommand is added to the subcommand set of the node corresponding to the logical unit accessed by the subcommand.

4. A method of processing read commands according to any of claims 1-2, characterized in that for a plurality of nodes, sub-command sets of each node are accessed in turn, sub-commands to be processed are obtained from each sub-command set and processed.

5. A write command processing method, comprising the steps of:

acquiring a write command, and splitting the write command into a plurality of subcommands;

allocating an active big block for the subcommand, and recording the subcommand in a subcommand set corresponding to the active big block allocated for the subcommand; acquiring a write subcommand from a subcommand set of the active large block, and accessing the nonvolatile memory according to the acquired subcommand;

indicating that the write command processing is complete in response to identifying that all subcommands of the write command are complete; wherein,,

in response to a subcommand writing a chunk of data of a size different from the physical page of the NVM chip, a plurality of subcommands in the subcommand set are assigned physical addresses of the same physical page on their corresponding active chunk.

6. The write command processing method of claim 5, wherein in response to the logical unit failing to respond to the subcommand, the subcommand is added to a subcommand set corresponding to the logical unit accessed by the subcommand.

7. The write command processing method according to claim 5, wherein the subcommand is acquired from the subcommand set periodically or alternately corresponding to the logic unit, and the nonvolatile memory is accessed according to the acquired subcommand.

8. The method of claim 7, wherein the first logic unit is configured to determine whether the first logic unit is configured to receive the subcommand, and if the first logic unit is configured to receive the subcommand, the first logic unit is configured to obtain the subcommand from the set of subcommands corresponding to the first logic unit, and access the nonvolatile memory according to the obtained subcommand.

9. The control component is characterized by comprising a host interface, a medium interface, a command splitting component, an address conversion component and a subcommand processing component;

the host interface is used for exchanging commands and data with the host;

a command splitting component coupled to the host interface for splitting the read command into a plurality of subcommands;

the address conversion component is respectively coupled with the command splitting component and the external memory and is used for acquiring a physical address corresponding to the logical address accessed by the subcommand and providing the physical address for the subcommand processing component;

the subcommand processing component is coupled with the address conversion component, adds the subcommand to a subcommand set corresponding to the logic unit accessed by the subcommand, acquires the subcommand from the subcommand set corresponding to each logic unit, and sends each subcommand to the medium interface;

the media interface is coupled to the subcommand processing means for accessing the non-volatile memory in accordance with the physical address of each subcommand.

10. A memory device comprising the control unit according to claim 9 and a nonvolatile memory.