CN110543430A

CN110543430A - storage device using MRAM

Info

Publication number: CN110543430A
Application number: CN201810519976.8A
Authority: CN
Inventors: 戴瑾
Original assignee: Shanghai Ciyu Information Technologies Co Ltd
Current assignee: Shanghai Ciyu Information Technologies Co Ltd
Priority date: 2018-05-28
Filing date: 2018-05-28
Publication date: 2019-12-06
Anticipated expiration: 2038-05-28
Also published as: CN110543430B

Abstract

The invention provides a storage device using MRAM (magnetic random access memory), which comprises a main memory, a main controller and a first auxiliary memory, wherein the main controller is internally integrated with a second auxiliary memory and a search accelerator; the first secondary memory and the second secondary memory are both non-volatile random access memories, and the search accelerator is used to control the content addressing operation to accelerate the search for data in the second secondary memory. The main memory is a NAND flash memory, the first auxiliary memory is an independent MRAM chip, and the second auxiliary memory is an MRAM. The second auxiliary memory integrated in the main controller is divided into a plurality of memory spaces, and a plurality of search accelerators are integrated in the main controller, and each search accelerator is responsible for retrieving one memory space. The hybrid storage device using the MRAM built in the control chip, the MRAM externally arranged and the flash memory is a storage solution with high cost-efficiency ratio.

Description

storage device using MRAM

Technical Field

The invention relates to a storage device, in particular to a storage device using MRAM (magnetic random Access memory), and belongs to the technical field of semiconductor chips.

Background

MRAM is a new memory and storage technology, can be read and written randomly as SRAM/DRAM, and can permanently retain data after power failure as Flash memory. The chip has good economy, and the silicon chip area occupied by unit capacity has great advantages compared with SRAM, NOR Flash frequently used in the chips and embedded NOR Flash. Its performance is also quite good, the read-write time delay is close to the best SRAM, and the power consumption is optimal in various memory and storage technologies. Also MRAM is not compatible with standard CMOS semiconductor processes like DRAM and Flash, and MRAM can be integrated with logic circuits in one chip.

The principle of MRAM is based on a structure called MTJ (magnetic tunnel junction). It consists of two layers of ferromagnetic material sandwiching a very thin layer of non-ferromagnetic insulating material, as shown in fig. 1 and 2. The lower layer of ferromagnetic material is a reference layer 13 with a fixed magnetization direction and the upper layer of ferromagnetic material is a memory layer 11 with a variable magnetization direction, the magnetization direction of the memory layer 11 can be parallel or anti-parallel to the reference layer 13. Due to quantum physical effects, current can pass through the middle tunnel barrier layer 12, but the resistance of the MTJ is related to the magnetization direction of the variable magnetization layer. The resistance is low when the magnetization directions of the memory layer 11 and the reference layer 13 are parallel, as shown in FIG. 1; the resistance is high in anti-parallel, as in fig. 2. The process of reading the MRAM is to measure the resistance of the MTJ. Using the newer STT-MRAM technology, writing to MRAM is also simpler: write operations are performed through the MTJ using a stronger current than read. A bottom-up current places the variable magnetization layer in an anti-parallel direction with the fixed layer. The current from top to bottom sets it in a parallel direction.

Each MRAM memory cell consists of a magnetic tunnel junction and an NMOS select transistor. Each memory cell needs to be connected to three wires: the gate of the NMOS selection tube is connected to a Word Line (Word Line)32 of the chip and is responsible for switching on or off the unit; one pole of the NMOS select transistor is connected to the Source Line (Source Line)33, the other pole of the NMOS select transistor is connected to one pole of the magnetic tunnel junction 34, and the other pole of the magnetic tunnel junction 34 is connected to the Bit Line (Bit Line)31, as shown in FIG. 3. An MRAM chip is made up of one or more arrays of MRAM memory cells, each array having a number of external circuits: a row address decoder for changing a received address to a selection of a word line; a column address decoder for changing a received address to a selection of bit lines; a read/write controller for controlling a read (measure) write (add current) operation on the bit line; and the input and output control is used for exchanging data with the outside.

currently, the development of NAND flash technology has pushed the SSD (solid state disk) industry. The SSD and the host use high-speed serial interfaces such as SATA, PICe and other technologies. The internal part of the system consists of a group of NAND chips for storing data, a DDR DRAM (memory) for supporting calculation and data storage, and a main control chip (SSD Controller), and the NAND also stores a logical address and physical address comparison table. Power-off protection systems are also sometimes required.

NAND is a one-block read-write memory device, the smallest readable unit is called a page (page), the smallest erasable unit is called a block (block), one block often consists of many pages, and the pages inside after the block is erased can be written separately. Write operations are slow, much slower than reads, while erase operations are much slower than writes.

Most NAND chips require that after a block is erased, its pages must be written in order. Between adjacent page writes of one block, pages of another block are written, which is allowed.

Since it is very time consuming to erase a NAND, especially to rewrite the contents of an entire block. NAND chips, and memory systems made up of them, typically employ multiple channel parallel writing to increase the overall write bandwidth of the system. There may be many NAND chips in a memory device, and each chip often has multiple silicon chips packaged therein, each silicon chip has a different Plane, and each Plane is an independent channel and can be written in parallel.

One problem with NAND flash memory is that NAND has a limited lifetime. After each page is erased and written for a certain number of times, the page is permanently disabled and can not be used continuously. The current industry trend is that NAND capacity and data density increase very rapidly, but at the expense of reduced lifetime. The number of times of rewriting is reduced from the first 10 ten thousand times to 3000 times at present.

the NAND flash memories generally have some damaged blocks when they are shipped, and the damaged blocks may appear continuously during use, so that all the NAND flash memories are accompanied by a damaged block table, and are generally stored in a designated area of the NAND flash memories or marked on the damaged blocks.

Because of the above characteristics of the NAND flash memory, the NAND management software inside the SSD is complicated. In order not to damage some blocks in advance where write operations often occur, a write leveling process is required. The logical and physical addresses identified by the file system software are different and a table is needed to correspond the two. Since NAND erasure is too slow, a content is generally modified without updating the original block area, but instead the new content is written to a new block area, the old block area is marked as invalid, and the CPU waits for its idle time to erase it. Thus, the lookup table of logical address physical addresses is constantly dynamically updated. This table is proportional to the total SSD capacity, and is stored in DDR DRAMs, with corresponding tags in NAND. With the rapid increase in SSD capacity on the market, this table becomes the largest consumer of DRAM.

The non-volatile and fast read and write capabilities of MRAM make it possible to improve the overall performance of NAND-based storage devices as a secondary storage medium. It can be integrated with logic circuits, and integrating SSD host chips together becomes an attractive option. The architecture of fig. 7 is proposed by US2010/0191896a 1.

The SSD host chip contains a CPU, a host interface 202, a flash interface 205, and an embedded MRAM. The logical address mapping table is used for the cache between the host interface and the flash memory interface and the logical physical address mapping table.

this architecture has a problem: as the capacity of the SSD increases, the capacity of the cache and the logical-physical address mapping table is required to increase. In high-end SSDs, the required cache already exceeds 1Gb, while the logical-physical address lookup table requires more than 8Gb of capacity.

Such a capacity is too large for embedded MRAM compatible with logic circuits. Which has not been achieved in recent years. For the external MRAM based on DRAM process development, it is hopeful to reach the external MRAM as soon as possible. The larger capacity presents another problem: searching in the cache and the comparison table takes longer and longer, and the performance of the system is affected.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, the technical problems to be solved by the present invention are: MRAM is used to optimize the overall performance of NAND flash memories.

In order to solve the above technical problems, the present invention provides a hybrid memory device using an MRAM built in a control chip, an MRAM external to the control chip, and a flash memory. The specific technical scheme is as follows:

A storage device using MRAM includes a main memory, a main controller, a first auxiliary memory, a second auxiliary memory and a search accelerator integrated in the main controller; the first secondary memory and the second secondary memory are both non-volatile random access memories, and the search accelerator is used to control the content addressing operation in order to speed up the search for data in the second secondary memory.

Further, the second auxiliary memory is MRAM.

Further, a second auxiliary memory integrated in the main controller is divided into a plurality of memory spaces, and a plurality of search accelerators are integrated in the main controller, and each search accelerator is responsible for retrieving one memory space.

Further, the main memory is a NAND flash memory, and the first auxiliary memory is an independent MRAM chip.

Further, a buffer area is established in the first auxiliary memory, and the buffer area is used for buffering data read and written by the NAND flash memory; establishing a cache table in the second auxiliary memory to record corresponding information of the logical address of each cached page of the NAND flash memory and the physical address of the cache region.

Further, when the NAND flash memory is read and written, the search accelerator is used for searching the cache table and inquiring whether the read and written page is in the cache region.

Further, a CPU is integrated in the main controller.

The invention has the beneficial effects that: compared with the prior scheme, the architecture of the invention is a storage scheme with higher cost-efficiency ratio and better performance.

Drawings

FIG. 1 is a diagram of a memory layer magnetically parallel to a reference layer when a magnetic tunnel junction is in a low resistance state;

FIG. 2 is a schematic diagram of the memory layer and the reference layer being magnetically antiparallel when the magnetic tunnel junction is in a high resistance state;

FIG. 3 is a schematic diagram of a memory cell comprising a magnetic tunnel junction and an NMOS transistor;

FIG. 4 is a diagram illustrating a chip architecture of a memory device according to a preferred embodiment of the present invention;

FIG. 5 is a schematic diagram of the complete internal external circuit structure of the memory device according to a preferred embodiment of the present invention;

FIG. 6 is a simplified flow chart of the search controller in accordance with a preferred embodiment of the present invention;

FIG. 7 is a diagram illustrating a chip architecture of a memory device according to the prior art.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. It is to be noted that the drawings are in simplified form and are not to precise scale, which is provided for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

In the prior art, the MRAM chip searches for the stored content, and the content in the memory can be read out one by one according to the address sequence only under the control of host software for comparison, which is time-consuming.

No less than 5 instructions need to be executed per search for an address in the MRAM chip:

(1) Reading data from the address;

(2) Comparing the read data with the search word;

(3) Integrating the comparison result with the mask word;

(4) If the comparison result is inconsistent, the address pointer is increased progressively to prepare for searching the next address;

(5) if the address reaches the end address, the search ends.

The invention provides a new storage architecture of hybrid embedded MRAM and external MRAM, namely a hybrid storage device using a control chip with built-in MRAM, external MRAM and flash memory, as shown in FIG. 4, comprising a main memory, a main controller, a first auxiliary memory, a second auxiliary memory, and a search accelerator; the main controller controls the main memory, the first auxiliary memory and the second auxiliary memory; the search accelerator is capable of controlling content addressing operations to accelerate the search of data in the second auxiliary memory. The main controller is an independent control chip, the second auxiliary memory is an embedded MRAM integrated in the main controller, and the main controller is integrated with a CPU. The main memory is a NAND flash memory, and the first auxiliary memory is an independent external MRAM chip. The search accelerator is also integrated within the main controller.

At least some of the MRAMs are MRAM with content addressing functionality. The MRAM with content addressing function includes one or more arrays of MRAM memory cells, each array connected to a control circuit including a row address decoder, a column address decoder, a read/write controller, and input/output controls. The comparator is used to compare the content read from the array with the search word and the search controller is used to control the content addressing operation, as shown in figure 5. When the search controller receives a search command, the row address decoder is driven to open the first row in the address area, the column address decoder is driven to open all bit lines of the row, then the read-write controller reads out the content of the row, the comparator compares the content with the search word, and if the content and the search word are consistent, the address of the row is output. If the address of the next row exceeds the address area, the content addressing is finished; if the address of the next row does not exceed the address area, the search controller drives the row address decoder to open the next row, drives the column address decoder to open all bit lines of the row, continues the read-write controller to read the content of the next row, and so on until the content addressing is finished.

and a buffer area is established in the external MRAM chip and used for caching the data read and written by the NAND flash memory. The method can play a role in improving the speed and reducing the NAND writing times. The memory requirements of the cache area are large (often >100MB) and are suitable for building in external MRAM.

And establishing a cache table in the embedded MRAM, and recording corresponding information of the logical address of each cached page of the NAND flash memory and the physical address of a cache region in the external MRAM chip. When the NAND flash memory is read and written, the search accelerator is utilized to search the cache table and inquire whether the read and written page is in the cache area. The cache table may contain thousands of cache pages and the accelerator can improve system performance well.

The second auxiliary memory which can be integrated in the main controller is divided into a plurality of memory spaces, a plurality of search accelerators are integrated in the main controller, and each search accelerator searches different built-in MRAM areas simultaneously.

The search accelerator works as follows:

The search controller obtains the search word, the starting address and the ending address input by the system main control CPU from the first appointed address field of the main memory, and the system main control CPU and the search controller transmit related information required by content addressing operation through the first appointed address field.

The search controller obtains the mask word input by the system main control CPU from the second appointed address field of the main memory, and is used for masking comparison of partial bits of the read content, so that the search is more flexible, and the length of the search word can be 8 bits, 16 bits or 32 bits, as shown in FIG. 6.

And the comparator matched with the search accelerator writes the comparison result into the third appointed address field of the main memory, the comparison result is an address with the storage content consistent with the search word, and the system main control CPU obtains the content addressing result from the third appointed address field of the main memory.

And the search controller acquires a search option input by the system main control CPU from the fourth appointed address field of the main memory, wherein the search option is used for controlling the content addressing operation to be immediately finished when a first result is searched by the search controller.

The invention belongs to the field of semiconductor chips, and is most importantly applied to the fields of handheld equipment, Internet of things, wearable electronic equipment and the like with strict requirements on standby power consumption.

The foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the prior art according to the concept of the present invention should be within the scope of protection defined by the claims.

Claims

1. The storage device is characterized by comprising a main memory, a main controller and a first auxiliary memory, wherein the main controller is internally integrated with a second auxiliary memory and a search accelerator; the first secondary memory and the second secondary memory are both non-volatile random access memories, and the search accelerator is used for controlling content addressing operation so as to accelerate searching data in the second secondary memory.

2. A storage device according to claim 1, wherein said first auxiliary memory is MRAM and said second auxiliary memory is embedded MRAM.

3. a storage device as claimed in claim 1, wherein said second auxiliary memory integrated in said main controller is divided into a plurality of storage spaces, and a plurality of said search accelerators are integrated in said main controller, each of said search accelerators being responsible for retrieving one of said storage spaces.

4. The memory device according to claim 2, wherein said main memory is NAND flash memory and said first auxiliary memory is a separate MRAM chip.

5. The storage device according to claim 4, wherein a buffer area is established in the first auxiliary memory, and the buffer area is used for buffering data read and written by the NAND flash memory; establishing a cache table in the second auxiliary memory to record corresponding information of the logical address of each cached page of the NAND flash memory and the physical address of the cache region.

6. the memory device as claimed in claim 5, wherein when reading from or writing to said NAND flash memory, said search accelerator searches said cache table to determine whether a page to be read or written is in said cache area.