CN110531651B - Rate control device suitable for Ethernet transmission - Google Patents
Rate control device suitable for Ethernet transmission Download PDFInfo
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Abstract
The invention discloses a rate control device suitable for Ethernet transmission, which comprises a central control unit (1), a rate control unit (2), an SDRAM (synchronous dynamic random access memory) storage unit (3), an Ethernet interface unit (4), a keyboard input unit (5), a clock unit (6) and a power circuit (7). The invention deeply integrates CPU software and hardware FPGA computing technology, realizes mutual independence, mutual noninterference and rate control of each interface, ensures that the rate precision is not influenced by a software timing system and a software task, controls the error in a high-power system master clock, is completely consistent with the data rate of the simulated equipment, avoids the problem of low rate precision caused by a shared channel for data sending/receiving, and has the characteristics of high rate control precision, autonomous and controllable technology, strong transportability, no foreign banning, good simulation effect, high economic benefit and the like.
Description
Technical Field
The invention belongs to the technical field of communication, and particularly relates to a rate control device suitable for Ethernet transmission.
Background
The communication equipment is easy to damage new equipment due to complex system, strong specialization, high integration level and high price, and the simulation training equipment based on software and Ethernet transmission is widely applied due to good simulation effect, low price and low difficulty in development technology. The Ethernet has the advantages of wide application, high communication rate, strong resource sharing capability, good openness and the like, and is widely applied to low-cost special communication places such as special network communication, simulation training, teaching demonstration and the like. The Ethernet transmission adopts an IP packet form, the speed is relatively fixed, the transmission burst is strong, and great influence is brought to the efficiency of accurately simulating various communication interface data. The prior communication equipment simulation training system based on Ethernet transmission is realized by adopting the schemes of software calculation and software delay, but the Ethernet transmission rate simulation based on software delay has the following problems: firstly, the method is influenced by a software timing system, the calculation precision is low, the difference between the data transmission rate and the data rate of the communication equipment is large, and the simulation effect is poor; secondly, software calculation is greatly influenced by other tasks of the system, and delay errors are increased when the software system is busy; thirdly, a data sending channel is shared, the data sending queuing influences the data sending channel, and the accuracy is low; and fourthly, parallel simulation of multiple paths of interfaces with different types cannot be realized.
Disclosure of Invention
The purpose of the invention is: the rate control device is suitable for Ethernet transmission, simultaneously realizes the rate control of various interface types/numbers, realizes the complete consistency with the interface data rate of the simulated equipment, and avoids the problem of low rate accuracy caused by a common channel for data transmission/reception.
The technical scheme of the invention is as follows: a rate control device suitable for Ethernet transmission comprises a central control unit, a rate control unit, an SDRAM storage unit, an Ethernet interface unit, a keyboard input unit, a clock unit and a power circuit;
after the central control unit receives the interface type and the interface rate input by the keyboard input unit user, a rate control table is calculated and generated and sent to the rate control unit, so that the interface rate control is realized; the speed control unit is controlled and is matched with the Ethernet interface unit to realize the simulation of different interface types and speeds; the rate control unit calculates and generates a clock frequency of sending/receiving data according to a rate control table and controls a time slot of the sending/receiving data, thereby realizing the rate control of data Ethernet transmission;
the rate control unit includes: the CPU interface module is used for adapting the CPU bus interface time sequence of the central control unit, the rate control module is used for realizing the rate control of various interfaces, the Ethernet interface module is used for realizing the adaptation with the Ethernet interface unit, the SDRAM interface module is used for adapting the external SDRAM storage unit interface time sequence, and the clock frequency doubling circuit is used for improving the clock frequency;
The rate control module includes: the device comprises a rate control word table for caching rate control words, a clock calculation module for calculating sending and receiving rate clocks, a clock frequency division module for decomposing clock frequency, a clock generation module for generating sending and receiving data clocks, a sending data reading module for reading sending data in an SDRAM (synchronous dynamic random access memory) storage unit, a sending buffer module for preventing burst data congestion and buffering the sending data, a sending control module for controlling the sending data rate, a receiving control module for controlling the receiving data rate, a receiving buffer module for preventing the SDRAM storage unit from losing the receiving data due to large operation data amount, and a receiving data writing module for writing the received data into the SDRAM storage unit;
the SDRAM storage unit is used for caching input data of various interfaces and preventing the interfaces from generating sudden big data and being incapable of sending in time to cause packet drop;
when the SDRAM storage unit has data to be sent, the sending data reading module carries the data to be sent into the sending buffer module; the central control unit calculates and generates a rate control table according to the interface type and the rate input by a user, and transmits the rate control table to the rate control module in the rate control unit through the CPU interface module in the rate control unit; the rate control word table in the control module updates or caches the rate control table in real time according to external input information; after the clock calculation module in the rate control module acquires the information of the rate control word table, a phase accumulated value is calculated according to a main frequency clock, then the phase accumulated value is brought into a direct digital frequency synthesizer, and a high-power clock required by data sending is generated through the direct digital frequency synthesizer; after the high-power clock output by the clock calculation module passes through the clock frequency division module, frequency division is carried out to obtain a data clock with the duty ratio of 50% and the frequency consistent with the frequency of the transmitted data; after the clock sent by the clock frequency division module passes through the clock generation module, a data transmission clock with the high level of a main frequency width and the frequency consistent with the frequency of the transmission data is generated; the sending control module outputs the data in the sending buffer module under the control of the sending clock sent by the clock generating module and the line permission sending enable;
The Ethernet interface unit includes: the Ethernet controller is used for finishing functions of Ethernet carrier monitoring, collision detection and code conversion, and the Ethernet transformer is used for finishing functions of signal transmission, impedance matching and voltage isolation;
the keyboard input unit is used for completing input of interface types and interface rates by a user, wherein the input interface types comprise an asynchronous serial port, a synchronous digital port, a group A port and a 2M E1 port, and the input rates comprise 0.3kbps, 0.6kbps, 1.2kbps, 2.4kbps, 4.8kbps, 7.2kbps, 9.6kbps, 14.4kbps, 16kbps, 19.2kbps, 32kbps, 38.4kbps, 57.6kbps, 64kbps, 115.2kbps, 128kbps, 230.4kbps, 256kbps, 512kbps, 1024kbps and 2048 kbps;
the clock unit is used for providing a device working clock, and the clock frequency is 22.1184MHz, 32.768MHz and 50 MHz;
the power supply circuit is used for converting an external input power supply into voltages required by each integrated circuit in the device.
The invention deeply integrates CPU software and hardware FPGA computing technology, realizes mutual independence, mutual noninterference and rate control of each interface, ensures that the rate precision is not influenced by a software timing system and a software task, controls the error in a high-power system master clock, is completely consistent with the data rate of the simulated equipment, avoids the problem of low rate precision caused by a shared channel for data sending/receiving, and has the characteristics of high rate control precision, autonomous and controllable technology, strong transportability, no foreign banning, good simulation effect, high economic benefit and the like.
Drawings
FIG. 1 is a schematic block diagram of the present invention;
fig. 2 is a schematic block diagram of a rate control unit.
Detailed Description
Example 1: referring to fig. 1 to 2, a rate control device suitable for ethernet transmission includes a central control unit 1, a rate control unit 2, an SDRAM storage unit 3, an ethernet interface unit 4, a keyboard input unit 5, a clock unit 6, and a power circuit 7;
after receiving the interface type and the interface rate input by the user of the keyboard input unit 5, the central control unit 1 calculates and generates a rate control table and sends the rate control table to the rate control unit 2 to realize interface rate control; the speed control unit 2 is controlled and the simulation of different interface types and speeds is realized under the coordination of the Ethernet interface unit 4; the rate control unit 2 calculates and generates a clock frequency of sending/receiving data according to a rate control table, and controls a time slot of the sending/receiving data, thereby realizing the rate control of data Ethernet transmission;
the rate control unit 2 includes: a CPU interface module 21 for adapting the CPU bus interface timing sequence of the central control unit 1, a rate control module 22 for realizing various interface rate control, an Ethernet interface module 23 for realizing adaptation with the Ethernet interface unit 4, an SDRAM interface module 24 for adapting the interface timing sequence of the external SDRAM storage unit 3, and a clock frequency multiplier circuit 25 for increasing the clock frequency;
The rate control module 22 includes: a rate control word table 221 for buffering rate control words, a clock calculation module 222 for calculating transmission and reception rate clocks, a clock division module 223 for dividing clock frequencies, a clock generation module 224 for generating transmission and reception data clocks, a transmission data reading module 225 for reading transmission data in the SDRAM memory unit 3, a transmission buffer module 226 for preventing bursty data congestion and buffering transmission data, a transmission control module 227 for controlling transmission data rates, a reception control module 228 for controlling reception data rates, a reception buffer module 229 for preventing the SDRAM memory unit 3 from losing reception data due to a large operation data amount, a reception data writing module 2210 for writing the received data into the SDRAM memory unit 3;
the SDRAM storage unit 3 is used for caching input data of various interfaces and preventing the interfaces from generating sudden big data and being incapable of sending in time to cause packet drop;
when the SDRAM storage unit 3 has data to be transmitted, the transmit data reading module 225 carries the data to be transmitted into the transmit buffer module 226; the central control unit 1 calculates and generates a rate control table according to the interface type and the rate input by the user, and transmits the rate control table to the rate control module 22 in the rate control unit 2 through the CPU interface module 21 in the rate control unit 2; the rate control word table 221 in the control module 22 updates or caches the rate control table in real time according to external input information; after the clock calculation module 222 in the rate control module 22 obtains the information of the rate control word table 221, a phase accumulated value is calculated according to a master frequency clock, and then the phase accumulated value is brought into a direct digital frequency synthesizer to generate a high-power clock required for sending data through the direct digital frequency synthesizer; after the high-power clock output by the clock calculation module 222 passes through the clock frequency division module 223, frequency division is performed to obtain a data clock with a duty ratio of 50% and a frequency consistent with the frequency of the transmitted data; after the clock sent by the clock frequency division module 223 passes through the clock generation module 224, a data transmission clock with a high level of a main frequency width and a frequency consistent with the frequency of the transmission data is generated; the transmission control module 227 outputs the data in the transmission buffer module 226 under the control of the transmission clock and the line-allowed transmission enable sent by the clock generation module 224;
The ethernet interface unit 4 includes: an ethernet controller 41 for performing functions of ethernet carrier sensing, collision detection, and code conversion, and an ethernet transformer 42 for performing functions of signal transmission, impedance matching, and voltage isolation;
the keyboard input unit 5 is used for completing the input of interface types and interface rates by a user, wherein the input interface types comprise an asynchronous serial port, a synchronous digital port, a group A port and a 2M E1 port, the input rates comprise 0.3kbps, 0.6kbps, 1.2kbps, 2.4kbps, 4.8kbps, 7.2kbps, 9.6kbps, 14.4kbps, 16kbps, 19.2kbps, 32kbps, 38.4kbps, 57.6kbps, 64kbps, 115.2kbps, 128kbps, 230.4kbps, 256kbps, 512kbps, 1024kbps and 2048 kbps;
the clock unit 6 is used for providing a device working clock, and the clock frequency is 22.1184MHz, 32.768MHz and 50 MHz;
the power supply circuit 7 is used for converting an external input power supply into voltages required by integrated circuits in the device.
Claims (1)
1. A rate control device adapted for ethernet transmission, comprising: the device comprises a central control unit (1), a rate control unit (2), an SDRAM (synchronous dynamic random access memory) storage unit (3), an Ethernet interface unit (4), a keyboard input unit (5), a clock unit (6) and a power circuit (7);
After the central control unit (1) receives the interface type and the interface rate input by the user of the keyboard input unit (5), calculating and generating a rate control table and sending the rate control table to the rate control unit (2) to realize interface rate control; the speed control unit (2) is controlled and the simulation of different interface types and speeds is realized under the coordination of the Ethernet interface unit (4); the rate control unit (2) calculates and generates the clock frequency of the sending/receiving data according to a rate control table and controls the time slot of the sending/receiving data, thereby realizing the rate control of the data Ethernet transmission;
the rate control unit (2) comprises: a CPU interface module (21) for adapting the CPU bus interface timing sequence of the central control unit (1), a rate control module (22) for realizing various interface rate control, an Ethernet interface module (23) for realizing adaptation with the Ethernet interface unit (4), an SDRAM interface module (24) for adapting the interface timing sequence of the external SDRAM storage unit (3), and a clock frequency doubling circuit (25) for increasing the clock frequency;
the rate control module (22) comprises: a rate control word table (221) for buffering rate control words, a clock calculation module (222) for calculating transmit and receive rate clocks, a clock division module (223) for dividing the clock frequency, a clock generation module (224) for generating a transmit and receive data clock, a send data reading module (225) for reading send data in the SDRAM memory unit (3), a transmission buffer module (226) for buffering transmission data to prevent burst data congestion, a transmit control module (227) for controlling a transmit data rate, a receive control module (228) for controlling a receive data rate, a receiving buffer module (229) for preventing the loss of received data due to a large amount of operation data in the SDRAM storage unit (3), a received data writing module (2210) for writing the received data to the SDRAM storage unit (3);
The SDRAM storage unit (3) is used for caching input data of various interfaces and preventing the interfaces from generating sudden big data which cannot be sent in time to cause packet drop;
when the SDRAM storage unit (3) has data to be transmitted, the transmission data reading module (225) carries the data to be transmitted into the transmission buffer module (226); the central control unit (1) calculates and generates a rate control table according to the interface type and the rate input by a user, and transmits the rate control table to the rate control module (22) in the rate control unit (2) through the CPU interface module (21) in the rate control unit (2); the rate control word table (221) in the rate control module (22) updates or caches the rate control table in real time according to external input information; after the clock calculation module (222) in the rate control module (22) acquires the information of the rate control word table (221), a phase accumulated value is calculated according to a main frequency clock, then the phase accumulated value is brought into a direct digital frequency synthesizer, and a high-power clock required by data transmission is generated through the direct digital frequency synthesizer; after the high-power clock output by the clock calculation module (222) passes through the clock frequency division module (223), frequency division is carried out to obtain a data clock with the duty ratio of 50% and the frequency consistent with the frequency of the transmitted data; after the clock sent by the clock frequency division module (223) passes through the clock generation module (224), a data transmission clock with a high level of a main frequency width and a frequency consistent with the frequency of the transmission data is generated; the transmission control module (227) outputs the data in the transmission buffer module (226) under the control of the transmission clock and the line-allowed transmission enable sent by the clock generation module (224);
The Ethernet interface unit (4) comprises; the Ethernet controller (41) is used for finishing functions of Ethernet carrier monitoring, collision detection and code conversion, and the Ethernet transformer (42) is used for finishing functions of signal transmission, impedance matching and voltage isolation;
the keyboard input unit (5) is used for completing the input of interface types and interface rates by a user, wherein the input interface types comprise an asynchronous serial port, a synchronous digital port, a group A port and a 2M E1 port, the input rates comprise 0.3kbps, 0.6kbps, 1.2kbps, 2.4kbps, 4.8kbps, 7.2kbps, 9.6kbps, 14.4kbps, 16kbps, 19.2kbps, 32kbps, 38.4kbps, 57.6kbps, 64kbps, 115.2kbps, 128kbps, 230.4kbps, 256kbps, 512kbps, 1024 s and 2048 kbps;
the clock unit (6) is used for providing a device working clock, and the clock frequency is 22.1184MHz, 32.768MHz and 50 MHz;
the power supply circuit (7) is used for converting an external input power supply into voltages required by integrated circuits in the device.
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| JP3005501B2 (en) * | 1997-07-02 | 2000-01-31 | 日本電気株式会社 | Rate control method |
| JP4351418B2 (en) * | 2002-04-26 | 2009-10-28 | 株式会社エヌ・ティ・ティ・ドコモ | Multimedia streaming transmission rate control method and apparatus |
| CN101150501A (en) * | 2007-10-31 | 2008-03-26 | 广州市新邮通信设备有限公司 | Self-adapted adjustment method for network speed in radio bandwidth access network |
| CN101478487B (en) * | 2009-02-09 | 2013-08-07 | 中兴通讯股份有限公司 | Control method and apparatus for Ethernet exchange device working rate |
| CN102394822B (en) * | 2011-11-02 | 2018-08-03 | 中兴通讯股份有限公司 | A kind of system and method for adjustment network transmission speed |
| CN102752212B (en) * | 2012-07-12 | 2015-08-19 | 苏州阔地网络科技有限公司 | A kind of transmission rate control |
| CN104320221B (en) * | 2014-11-13 | 2018-01-09 | 福州瑞芯微电子股份有限公司 | The bus transfer rate control method and device of a kind of communication module |
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