CN110531125A - Space convertor, probe card and its manufacturing method - Google Patents
Space convertor, probe card and its manufacturing method Download PDFInfo
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- CN110531125A CN110531125A CN201910435481.1A CN201910435481A CN110531125A CN 110531125 A CN110531125 A CN 110531125A CN 201910435481 A CN201910435481 A CN 201910435481A CN 110531125 A CN110531125 A CN 110531125A
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- 239000000523 sample Substances 0.000 title claims abstract description 58
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000013078 crystal Substances 0.000 claims abstract description 51
- 238000006243 chemical reaction Methods 0.000 claims abstract description 31
- 230000008719 thickening Effects 0.000 claims abstract description 18
- 238000001514 detection method Methods 0.000 claims abstract description 6
- 239000012792 core layer Substances 0.000 claims description 31
- 238000009826 distribution Methods 0.000 claims description 28
- 239000010410 layer Substances 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 13
- 230000005484 gravity Effects 0.000 claims description 10
- 238000005728 strengthening Methods 0.000 claims description 5
- 238000012545 processing Methods 0.000 claims description 4
- 230000007704 transition Effects 0.000 claims 1
- 238000012360 testing method Methods 0.000 description 21
- 235000012431 wafers Nutrition 0.000 description 16
- 238000010586 diagram Methods 0.000 description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 6
- 230000005611 electricity Effects 0.000 description 6
- 238000005520 cutting process Methods 0.000 description 5
- 206010010356 Congenital anomaly Diseases 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000012956 testing procedure Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/06711—Probe needles; Cantilever beams; "Bump" contacts; Replaceable probe pins
- G01R1/06733—Geometry aspects
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/06711—Probe needles; Cantilever beams; "Bump" contacts; Replaceable probe pins
- G01R1/06755—Material aspects
- G01R1/06761—Material aspects related to layers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2896—Testing of IC packages; Test features related to IC packages
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Geometry (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The present invention discloses a kind of space convertor, probe card and its manufacturing method.The space convertor and probe card proposed is suitable for detection wafer, and the wafer includes multiple crystal grain, and each crystal grain can be packaged into IC chip with integrated circuit board, and has a circuit layout between the upper surface and lower surface of the integrated circuit board.The space convertor includes thickening layer body and the first layered body.Thickening layer body includes multiple middle attachment zone blocks, and the first layered body is set to the lower surface of thickening layer body.First layered body includes that block is converted in multiple spaces of spaced-apart relation, and each space conversion block includes contact zone on first opposite to each other and the first lower contact zone, and contact zone is electrically connected in each middle attachment zone block on each first.There is a circuit layout, and the circuit layout of each space conversion block is identical to the circuit layout of the integrated circuit board on relative to each other first between contact zone and the first lower contact zone.In addition, adjacent 2 first lower contact zones axially have space D along one, each first lower contact zone has width W along above-mentioned axial direction, wherein D=n × W, and n is the positive integer more than or equal to 2.
Description
Technical field
The present invention relates to a kind of space convertor, probe card and its manufacturing methods.
Background technique
The manufacturing method of traditional IC chip is that multiple crystal grain are first formed on wafer, then cuts wafer
It cuts and forms multiple independent crystal grain, each independent crystal grain is encapsulated respectively again.Crystal grain foundation function itself is not
With and can have different sizes, the size of the crystal grain of function complexity is usually bigger, the quantity of the contact point on crystal grain also compared with
It is more, therefore the spacing of contact point is usually very narrow.Contact point on the better simply crystal grain of function is although less, but because of the ruler of crystal grain
It is very little also smaller, therefore the spacing of contact point is similarly very narrow.Therefore, general crystal grain is difficult to directly carry out electrical property with circuit board
Connection.
In order to which the circuit in crystal grain can be electrically connected with circuit board, it is necessary to by the space of the contact point on crystal grain
Distribution is amplified, this step is referred to as space conversion (space transform).Space conversion is usually by welding crystal grain
It is connected on integrated circuit board to realize.Integrated circuit board has upper surface and lower surface, the upper contact point of upper surface
Spatial distribution is identical as the corresponding spatial distribution of contact point of crystal grain, and the distribution of the lower contact point of lower surface is then more well-to-do, on
Then there is a circuit layout between surface and lower surface and the lower contact point of the upper contact point of upper surface and lower surface is given into electrical property
Connection.In this way, which the spatial distribution of the contact point on crystal grain is just able to amplify by integrated circuit board.
Crystal grain is before in conjunction with integrated circuit board, it is often necessary to program after testing, such as needle is carried out by probe card
It surveys (probing test).In order to detect to the crystal grain on wafer, the probe distribution in probe card also must be with crystalline substance
Contact point distribution on grain is identical, therefore probe equally also has compact distribution.As described earlier, the contact point on crystal grain
Because compact distribution is be difficult to directly be electrically connected with circuit board, similarly, the probe of compact distribution, which also has, to be difficult to directly
The problem of being electrically connected with test circuit board, therefore probe equally also has to pass through " space convertor " and carries out space conversion
Begin to be electrically connected with test circuit board.
Space convertor has upper surface and lower surface as integrated circuit board, wherein the following table being connected with probe
Face has compact contact point distribution identical with probe distribution, then has well-to-do connect towards the upper surface of test circuit board
Contact distribution.Between the upper surface and lower surface of space convertor equally by a circuit layout by the contact point of upper surface with
The contact point of lower surface is electrically connected with each other.
Conventional semiconductors test dealer when the space for carrying out probe distribution is converted, and only consider the following table of space convertor
The probe distribution in face must contact point identical as the contact point distribution on crystal grain and upper surface distribution allow for and test
Circuit board is electrically connected, and the circuit layout design not being contemplated between two surfaces up and down of space convertor may be to crystalline substance
The influence of grain electrical testing performance.Integrated circuit is packaged into after must further connecting with integrated circuit board due to crystal grain
Chip, therefore the electrical performance of crystal grain when testing is not necessarily packaged into the electrical table after IC chip with it
It is now consistent.
Summary of the invention
In view of this, being suitable for a probe card it is an object of the invention to propose a kind of space convertor, probe card is applicable in
In the wafer that detection includes multiple crystal grain.Each crystal grain can be packaged into IC chip with integrated circuit board, integrate electricity
There is a circuit layout between the upper surface and lower surface of road-load plate.The space convertor includes: a thickening layer body, comprising more
A middle attachment zone block；And one first layered body, it is set to the lower surface of thickening layer body, multiple skies comprising spaced-apart relation
Between convert block, each space conversion block include on relative to each other first contact zone with first descend contact zone, connect on each first
Touching area is electrically connected at each middle attachment zone block respectively, has between contact zone and the first lower contact zone on relative to each other first
One circuit layout, and the circuit layout of each space conversion block is identical to the circuit layout of integrated circuit board；Adjacent 2 first
Lower contact zone is axial with a space D along one, and each first lower contact zone edge is axial to have a width W, wherein D=n × W, and n is
Positive integer more than or equal to 2.
The present invention also proposes a kind of probe card, includes: above-mentioned space convertor；One circuit board is set to thickening layer body
Upper surface；And a probe, it is electrically connected at the first lower contact zone of each space conversion block of the first layered body.
The present invention also proposes a kind of manufacturing method of space convertor, and manufactured space convertor is suitable for a probe
Card, probe card are suitable for one wafer of detection, and wafer includes multiple crystal grain, and each crystal grain can be packaged into a collection with an integrated circuit board
At circuit chip, there is a circuit layout, the manufacturing method packet of probe card between the upper surface and lower surface of integrated circuit board
Contain: obtaining the circuit layout of integrated circuit board；Offer includes a core layer body of multiple middle attachment zone blocks；Have with multilayer
Machine technology is successively respectively formed one first layered body and one second layered body, the first layered body in two surfaces of core layer body
Block is converted in multiple spaces comprising spaced-apart relation, each space conversion block include on relative to each other first contact zone with
First descends contact zone, and contact zone is electrically connected in each middle attachment zone block on each first, contacts on relative to each other first
There is a circuit layout, and the circuit layout of each space conversion block is identical to integrated circuit load between area and the first lower contact zone
The circuit layout of plate；Adjacent 2 first lower contact zones are axial with a space D along one, and each first lower contact zone has one along axial
Width W, wherein D=n × W, and n is the positive integer more than or equal to 2；Second layered body includes that the multiple of spaced-apart relation prolong
Electrical connection block is stretched, contact zone and the second lower contact zone on each second for extending electrical connection block and including relative to each other, each second
Lower contact zone is electrically connected in each middle attachment zone block.
The present invention also proposes a kind of manufacturing method of probe card, and it includes multiple that manufactured probe card, which is suitable for detection,
The wafer of crystal grain, each crystal grain can be packaged into IC chip with integrated circuit board, and the upper surface of integrated circuit board is under
There is a circuit layout, the manufacturing method of probe card includes: obtaining the circuit layout of integrated circuit board between surface；Packet is provided
A core layer body containing multiple middle attachment zone blocks；Successively distinguished in two surfaces of core layer body with multilayer organic processing techniques
One first layered body and one second layered body are formed, the first layered body includes that block is converted in multiple spaces of spaced-apart relation,
Each space converts block and includes contact zone on first opposite to each other and the first lower contact zone, and contact zone is electrical respectively on each first
It is connected to each middle attachment zone block, there is a circuit layout between contact zone and the first lower contact zone on relative to each other first,
And the circuit layout of each space conversion block is identical to the circuit layout of integrated circuit board；Adjacent 2 first lower contact zones are along one
Axial to have a space D, each first lower contact zone has a width W along axial, wherein D=n × W, and n is more than or equal to 2
Positive integer；Second layered body includes that multiple extensions of spaced-apart relation are electrically connected block, and each electrical connection block that extends includes
Contact zone and the second lower contact zone on relative to each other second, each second lower contact zone are electrically connected in each middle attachment zone
Block；It is electrically connected a circuit board and extends contact zone on be electrically connected block second in each of the second layered body；And it is electrically connected one
Probe is in the first lower contact zone of each space of the first layered body conversion block.
Since the circuit layout design of above-mentioned space convertor is at identical as the circuit layout of integrated circuit board, so that whole
Body test condition is packaged into state when IC chip closer to crystal grain, and obtained test result is also closer to true
Real, reliability is also higher.
Below in conjunction with the drawings and specific embodiments, the present invention will be described in detail, but not as a limitation of the invention.
Detailed description of the invention
Fig. 1 is the schematic diagram (one) of one embodiment of the invention；
Fig. 2 is the schematic diagram (two) of one embodiment of the invention；
Fig. 3 is the bottom view of the space convertor of one embodiment of the invention；
Fig. 4 is the top view of the space convertor of one embodiment of the invention；
Fig. 5 is the schematic diagram of another embodiment of the present invention；
Fig. 6 is the distribution schematic diagram (one) of the empty contact zone of an illustration space convertor of the invention；
Fig. 7 is the distribution schematic diagram (two) of the empty contact zone of an illustration space convertor of the invention；
Fig. 8 is the distribution schematic diagram (three) of the empty contact zone of an illustration space convertor of the invention.
Wherein, appended drawing reference
10 probe card, 11 circuit board
The empty contact point of 112 electrical pickoff 115
13 space convertor, 131 core layer body
1311 middle attachment zone block 1311a electrical connecting passages
Convert block in 132 first layered body, 1321 space
The lower contact zone contact zone 132b first on 132a first
The 1322 lower bases of contact point 132L1~4
133 second layered body of the base of 133L1~4
The lower contact zone contact zone 133b second on 133a second
133c space interval area 1331 extends electrical connection block
Contact point on 1331a electrical connecting passage 1332
135 138 strengthening layers of empty contact point
139 circuit layout, 15 probe
151 probe, 20 thickening layer body
The lower contact zone 23 space convertor 232b first
Contact zone on 233 second layered body 233a second
Contact point on 233d sky contact zone 2332
235 90 wafers of empty contact point
91 crystal grain D spacing
W width
Specific embodiment
Structural principle and working principle of the invention are described in detail with reference to the accompanying drawing:
Fig. 1 and Fig. 2, the respectively schematic diagram (one) of one embodiment of the invention and schematic diagram (two) are please referred to, is painted
A probe card 10 out comprising circuit board 11, is electrically connected at the space convertor 13 of circuit board 11 and is electrically connected at space
The probe 15 of converter 13.Each element of the structure of space convertor 13 for convenience of description, above-mentioned probe card 10 does not press reality
Border ratio is drawn.Actually thickness of the thickness of circuit board 11 greater than space convertor 13.
Probe card 10 is suitable for carrying out needle survey to multiple crystal grain 91 on wafer 90.Wafer 90 cut obtain it is other
After crystal grain 91, each crystal grain 91 can further be packaged into integrated electricity jointly with the integrated circuit board (not shown) to match
Road chip.Integrated circuit board itself for combining with crystal grain 91 has a circuit layout, to by integrated circuit board
Each contact point of upper surface be electrically connected at each contact point of lower surface.When crystal grain 91 is welded in integrated circuit board
It when upper surface, is converted by the space of integrated circuit board, crystal grain 91 just can be with the integrated electricity with well-to-do spatial distribution
The contact point of the lower surface of road-load plate is electrically connected with extraneous circuit board.
Space convertor 13 includes thickening layer body 20 and the first layered body 132.The thickening layer body 20 of the present embodiment includes core
Central layer body 131 and the second layered body 133, but in another embodiment, thickening layer body 20 itself can only include core layer body
131 without the second layered body 133.Core layer body 131 is a substrate with hardness, and the hardness of core layer body 131 is greater than the
One layered body 132.Core layer body 131 includes multiple middle attachment zone blocks 1311, and each middle attachment zone block 1311 includes more
It is a that multiple electrical connecting passage 1311a are formed by by machine drilling mode.
First layered body 132 includes that block 1321 is converted in multiple spaces of spaced-apart relation, and block is converted in each space
1321 include the lower contact zone 132b of contact zone 132a and first on first opposite to each other.Contact zone 132a is electric respectively on each first
Property be connected to each middle attachment zone block 1311 of core layer body 131, connect under contact zone 132a and first on relative to each other first
Touching has a circuit layout 139 between area 132b, and the circuit layout 139 of each space conversion block 1321 is identical to integrated circuit
The circuit layout of support plate.But in another embodiment, the circuit layout 139 at least 70% of each space conversion block 1321 is with first-class
It is same as the circuit layout of integrated circuit board.Why can variant (less than 30%) be because in this embodiment, space turns
Change block 1321 circuit layout 139 can increase such as with feedback (Loopback) test function circuit, capacitor.
Second layered body 133 of thickening layer body 20 is set to the upper surface of core layer body 131.Second layered body 133 includes
Multiple extensions of spaced-apart relation are electrically connected block 1331, and each extend is electrically connected on block 1331 includes relative to each other second
Contact zone 133b under contact zone 133a and second, each second lower contact zone 133b are electrically connected in each middle attachment zone block
1311.In the present embodiment, the second layered body 133 upper surface that is, thickening layer body 20 upper surface.
It is the specific structure of the space convertor 13 of one embodiment of the invention above, if further electrically by circuit board 11
It is connected to each of the second layered body 133 and extends contact zone 133a on be electrically connected block 1331 second, and probe 15 is electric
Property be connected to the first layered body 132 each space conversion block 1321 the first lower contact zone 132b, that is, constituting can be to wafer 90
Multiple crystal grain 91 carry out needle survey probe card 10.
With further reference to Fig. 3 and Fig. 4, respectively the bottom view of the space convertor 13 of one embodiment of the invention with bow
View.As shown in figure 3, the lower contact zone 132b of adjacent the 2 first of space convertor 13 has along one axial (such as x-axis direction)
One space D, each first lower contact zone 132b have a width W along X axis, and each test system on wafer to be measured (DUT,
Device Under Test) between Cutting Road width be C (not shown), wherein D=n × W+ (n+1) C, and n be positive integer.
When n=1, width (being equivalent to the first lower contact zone 132b along the width of X axis) W that space D is a DUT is added
Width C of the DUT along two Cutting Roads of two side of X axis；When n=2, the width that space D is two DUT is plus DUT along X
The width C of three Cutting Roads of axial two sides, and so on.It is the embodiment of n=2 depicted in Fig. 3.Why phase is limited
Space D=n × W+ (n+1) C between the lower contact zone 132b of neighbour 2 first is in order to because should crystal grain to be measured on wafer to be measured
When the arrangement of (or test system) is very close, since probe arranging density has its congenital limitation, it is therefore necessary to take and jump DUT
The test mode of (Device Under Test).That is, the continuous adjacent two being located in same axial direction (even connects to side crystal grain
Continue three or more adjacent crystal grain) in same testing procedure, only one can be tested probe card and be tested.Further come
It says, probe arranging density has its congenital limitation to refer to that space convertor 13 has its congenital limitation, under first under contact zone 132b
Contact point 1322 is via the upper contact point 1332 for corresponding to contact zone 133a on second after the conversion of space, upper 1332 ability of contact point
It is electrically connected with circuit board 11, therefore each first lower contact zone 132b is needed with contact zone in unification corresponding second
133a, space convertor 13 is in the range of a corresponding crystal grain to be measured, it should convert block 1321 as examining using a space
Amount, so space convertor 13 must take the space layout mode for jumping DUT in lower surface.
Hold, space convertor 13 observed in itself if single, can by the size of the first lower contact zone 132b come
Learn DUT along specific axial width W.If but do not know the DUT pattern corresponding to space convertor 13 to side wafer, still
DUT can not be learnt along the width C of the Cutting Road of specific two side of axial direction, that is, only it is observed that D=n × W, n > 1, but affiliated skill
Having usually intellectual in art field still can be appreciated that the DUT worked as know corresponding to space convertor 13 to side wafer along specific axis
To the Cutting Road of two sides width C when, D will meet D=n × W+ (n+1) C, and n is positive integer.
Above-mentioned is the specific structure of the space convertor 13 of one embodiment of the invention, if further by 11 electricity of a circuit board
Property is connected to the upper surface of the thickening layer body 20 of space convertor 13, and a probe 15 is electrically connected at space convertor
13 lower surface may make up the probe card 10 that can be used to that multiple crystal grain 91 of wafer 90 are carried out with needle survey.Such as Fig. 1 and Fig. 2 institute
Show, the surface of circuit board 11 towards space convertor 13 is provided with multiple upper contact points relative to contact zone 133a on second
1332 electrical pickoff 112, and the empty contact point 115 relative to the empty contact point 135 of contact zone 133a on second.It is corresponding
Upper contact point 1332 and electrical pickoff 112 between can be electrically connected by tin ball.Similarly, on probe 15
More probes 151 can also individually be electrically connected at the lower contact point 1322 of corresponding first layered body 132 by tin ball.
Needing special emphasis herein is, the first layered body 132 of the space convertor 13 of the present embodiment and the second layered body
133 be and the integrating of being applicable in of the circuit layout 139 of the first layered body 132 and crystal grain 91 to be tested with made by MLO technique
The circuit layout of circuit board is identical.It can allow integrated testability condition that can be packaged into integrated circuit closer to crystal grain 91 whereby
State when chip, obtained test result is also more close to confidence level that is true, and increasing test result.
It referring to figure 5., is the schematic diagram of another embodiment of the present invention.In another embodiment of the invention, the first multilayer
Body 132 is identical as the number of plies of the second layered body 133, includes four bases, wherein the first layered body 132 includes four bases
132L1~132L4, the second layered body 133 include four base 133L1~133L4.If the first layered body more than 132 and second
The number of plies of layer body 133 is different, then space convertor 13 is easy to happen the case where plate is stuck up, cause upper surface upper contact point 1332 or
Person is that the lower contact point 1322 of lower surface is not coplanar, in turn results in that 10 yield of probe card is bad or the service life is reduced.In addition, empty
Between the second layered body 133 of converter 13 be also provided with a strengthening layer 138 towards the surface of core layer body 131, can increase
Add the intensity of the entirety of space convertor 13.When strengthening layer 138 itself is made using copper or other conductive materials, on circuit
Also it is used with can be used as whole ground plane (ground plane) or power plane (power plane).In addition to this,
Strengthening layer 138, which can also change, to be arranged in backwards to the surface of core layer body 131, or is arranged in simultaneously towards core layer body 131
Surface and backwards to core layer body 131 surface, be possibly even arranged in the second layered body 133 any two bases it
Between.Core layer body 131 is made of using glass fibre as backbone and to fill colloid, therefore thickness can be compared with the first layered body 132
Four base 132L1~132L4 therein one are thick.
In the present embodiment, the upper contact point 1332 of the second layered body 133 of space convertor 13 defines contacts on one
Space of points distribution, the lower contact point 1322 of the first layered body 132 of space convertor 13 then define the contact space of points point
Cloth, wherein lower contact point spatial distribution can carry out get Geng Mi than upper contact point spatial distribution.It is so-called " closeer " to be meant that every list
The quantity of the contact point of plane product is more or the distance between adjacent two contact point is relatively close, i.e., space convertor 13 is upper
Contact point spatial distribution carries out space in the internal circuit of space convertor 13 and is converted into lower contact point spatial distribution.In this implementation
In example, the electrical connecting passage 1331a of the second layered body 133 of space convertor 13 and the electrical connecting passage of core layer body 131
1311a is vertical perforation, indicates that there is no the situations of aforesaid space conversion in the second layered body 133 and core layer body 131, empty
Between the layout type converted only occur in the first layered body 132.
Referring to figure 4., on the second of the probe card 10 of the present embodiment either two neighboring second around contact zone 133a
It is for a space interval area 133c between upper contact zone 133a.Empty contact point can be further set in space interval area 133c
135.The empty contact point 135 of the present embodiment is not electrically connected in the test electronic loop of probe card 10, and empty contact is arranged
One of purpose of point 135 is connect when circuit board 11 carries out reflow (reflow) technique by tin ball with space convertor 13
When together, the tin ball on empty contact point 135 can be used as support construction, that is, be used to increase space convertor 13 and electricity
The support strength of linkage interface between road plate 11.In addition it is also possible to make each tin ball mean allocation stress, avoid in upper contact point
The case where individually excessively meeting with stresses in 1332 region and cause tin ball fractured generation.In one embodiment, space interval area
133c can also go out an at least electronic component rest area depending on demand planning other than empty contact point 135 is arranged IC core is arranged
Piece.In addition, the electrical pickoff between IC chip and the second layered body 133 also may include more than one empty contact point 135.
Fig. 6 is please referred to, shows the empty contact zone 233d of an illustration space convertor 23 in the upper of the second layered body 233
Distribution on surface.Second layered body 233 includes contact zone 233a on four second, corresponds respectively to four first lower contact zones
232b.In this embodiment, the upper surface of the second layered body 233 includes multiple (being five in figure) sky contact zone 233d, each
Empty contact zone 233d includes multiple empty contact points 235.As shown in fig. 6, sky contact zone 233d distinguishes position in four corners and the
The center of gravity of the upper surface of two layered bodies 233.
Fig. 7 is please referred to, the second layered body 233 can also be arranged in individually in the empty contact zone 233d of the second layered body 233
The center of gravity of upper surface and the top surface edge on the basis of center of gravity along X axis and Y-axis extension and with the second layered body 233
Four blocks of intersection, the line of these sky contact zones 233d constitute two mutually orthogonal straight lines.In addition, in the present embodiment
In, the spacing of the upper contact point 2332 of contact zone 233a is identical in the spacing and second of the empty contact point 235 of empty contact zone 233d.
Fig. 8 is please referred to, the empty contact zone 233d of the second layered body 233 is in addition to can be set in four corners and more than second
Except the center of gravity of the upper surface of layer body 233, it can also be arranged in simultaneously on the basis of the center of gravity of the upper surface of the second layered body 233
Four regions at the edge of the upper surface of the second layered body 233 are extended to along X axis and Y-axis.
In one embodiment, the thickness summation of 133 the two of core layer body 131 and the second layered body can be greater than 0.3mm, with
Reach specific structural strength.In one embodiment, the quantity of block 1321 is converted as even number in the space of the first layered body 132.
Another embodiment of the present invention is for the manufacturing method of above-mentioned space convertor 13, the system of the space convertor 13
Making method includes steps described below, but is not limited to manufacture according to the sequencing of following steps, is hereby described as follows.
The circuit layout of integrated circuit board used in the chip to be tested first is obtained first.Then such as Fig. 1 is provided
Shown in include multiple middle attachment zone blocks 1311 core layer body 131, wherein middle attachment zone block 1311 includes multiple
Multiple electrical connecting passage 1311a are formed by the way of machine drilling.Referring to figure 5., multilayer organic processing techniques are utilized
(Multi-layer Organic, MLO) is respectively formed the sublayer of the first layered body 132 in two surfaces of core layer body 131
The sublayer 133L1 of 132L1 and the second layered body 133.Then pre- on the sublayer 132L1 of the first layered body 132 using laser
The standby position as space conversion block 1321 forms multiple perforation, and the preparation on the sublayer 133L1 of the second layered body 133
Multiple perforation are formed as the position for extending electrical connection block 1331.Then, continue with MLO technique formed sublayer 132L2 and
Sublayer 133L2；Similarly, it is also necessary to prepared on sublayer 132L2 using laser as the position shape of space conversion block 1321
At perforation, and is prepared on sublayer 133L2 and form multiple perforation as the position for extending electrical connection block 1331.The rest may be inferred
Until the number of plies meet demand (such as with four sublayer 132L1~132L4) of the first layered body 132 and the second layered body
Until 133 number of plies meet demand (such as with four sublayer 133L1~133L4).Wherein, the sublayer of the first layered body 132
Perforation on 132L1~132L4 can be interconnected, and lead as long as forming conductive material (such as copper or silver) in perforation and can be formed
Electric line, and all conducting wires of each space conversion block 1321 just constitute circuit layout 139.Similarly, each extension electricity
Connection block 1331 can also have multiple conducting wires, and each conducting wire is respectively communicated in each of middle attachment zone block 1311
A electrical connecting passage 1311a.
It holds, the first manufactured layered body 132 includes that block 1321 is converted in multiple spaces of spaced-apart relation, respectively
Space converts block 1321 and includes the lower contact zone 132b of contact zone 132a and first on first opposite to each other, and on each first
Each middle attachment zone block 1311 in core layer body 131 is electrically connected in contact zone 132a.It is contacted on relative to each other first
There is circuit layout 139 between the lower contact zone 132b of area 132a and first.As shown in figure 3, adjacent two first lower contact zones
132b has a space D along one axial (such as x-axis), and each first lower contact zone 132b has a width W along the same axis, wherein
D=n × W, and n must be greater than or equal to 2 positive integer.In addition, the circuit layout 139 of each space conversion block 1321 is necessary
It is substantially identical or at least 70% or more is equal to chip to be measured and arranges in pairs or groups the circuit layout of the integrated circuit board used.This
While the circuit layout referred to is identical, refer to that client provides the circuit layout of integrated circuit board, according to space convertor 13 and integrates
Circuit board uses the difference of material, can match and be finely adjusted to impedance line, such as line width, line-spacing etc..
Another embodiment of the present invention is for the manufacturing method of probe card 10, and the manufacturing method of the probe card 10 is in addition to packet
Except the step of manufacturing method containing above-mentioned space convertor 13 is included, further comprise be electrically connected a circuit board 11 in
The each of second layered body 133 of space convertor 13 extends contact zone 133a on be electrically connected block 1331 second, and electrically
A probe 15 is connected in the first lower contact zone 132b of each space of the first layered body 132 conversion block 1321.
The various embodiments described above include following common feature: the lower contact zone of adjacent two first of (one) space convertor 13
132b axially has a space D along one, and each first lower contact zone 132b has a width W along the same axis, wherein D=n × W,
And n is the positive integer more than or equal to 2；And the circuit layout 139 of (two) each space conversion block 1321 must be identical to
The crystal grain 91 of test is arranged in pairs or groups the circuit layout of the integrated circuit board used.(3) experiment display only uses merely the first multilayer
Body 132 be used as space convertor, once with circuit board 11 with BGA technique combine have flatness it is bad situation generation.Pass through
First layered body 132 is combined with thickening layer body 20, integral strength is substantially increased, with circuit board 11 with reflow process in conjunction with after
It will not that there is a situation where flatness be bad.
Certainly, the present invention can also have other various embodiments, without deviating from the spirit and substance of the present invention, ripe
It knows those skilled in the art and makes various corresponding changes and modifications, but these corresponding changes and change in accordance with the present invention
Shape all should fall within the scope of protection of the appended claims of the present invention.
Claims (15)
1. a kind of space convertor is suitable for a probe card, the probe card is suitable for one wafer of detection, and the wafer includes more
A crystal grain, each crystal grain can be packaged into an IC chip with an integrated circuit board, the integrated circuit board it is upper
There is a circuit layout, it is characterised in that the space convertor includes between surface and lower surface:
One thickening layer body includes multiple middle attachment zone blocks；And
One first layered body is set to the lower surface of the thickening layer body, multiple space transition zones comprising spaced-apart relation
Block, each space conversion block include on relative to each other one first contact zone with one first descend contact zone, each described first
Upper contact zone is electrically connected in each middle attachment zone block, contact zone and described first on relative to each other described first
There is a circuit layout, and the circuit layout at least 70% or more of each space conversion block is equal between lower contact zone
The circuit layout of the integrated circuit board；Adjacent two described first lower contact zones along one it is axial there is a space D, each described the
Once contact zone has a width W along the axial direction, wherein D=n × W, and n is greater than 1.
2. space convertor according to claim 1, which is characterized in that the thickening layer body includes a core layer body and one
Second layered body, the multiple middle attachment zone block are located at the core layer body, and second layered body is set to the core
The upper surface of layer body, multiple extensions comprising spaced-apart relation are electrically connected block, and each extension electrical connection block includes that
This contact zone and one second lower contact zone on opposite one second, each described second lower contact zone is electrically connected in each described
Middle attachment zone block.
3. space convertor according to claim 2, which is characterized in that further include a strengthening layer, be set to described second
Surface of the layered body towards the core layer body or the surface backwards to the core layer body.
4. space convertor according to claim 2, which is characterized in that further include multiple empty contact points, be set to each institute
It states on multiple second around contact zone.
5. space convertor according to claim 4, which is characterized in that on two adjacent described second between contact zone
Region be a space interval area, it is the multiple sky contact point be arranged in the space interval area.
6. space convertor according to claim 5, which is characterized in that the space interval area has more an electronic component
Rest area.
7. space convertor according to claim 2, which is characterized in that the core layer body and second layered body
Overall thickness is greater than 0.3mm.
8. space convertor according to claim 2, which is characterized in that the quantity of the multiple space conversion block is even
Number.
9. space convertor according to claim 8, which is characterized in that further include multiple empty contact zones, each sky connects
Touching area includes multiple empty contact points, and the upper surface of second layered body is in rectangle, and the multiple sky contact zone is laid in described
Four corners of the upper surface of the second layered body and center of gravity.
10. space convertor according to claim 8, which is characterized in that further include multiple empty contact zones, each sky connects
Touching area includes multiple empty contact points, and the upper surface of second layered body is in rectangle, and the multiple sky contact zone is laid in described
The center of gravity of the upper surface of second layered body and on the basis of center of gravity along an X axis and a Y-axis extend and with second multilayer
Four blocks of the upper surface periphery intersection of body.
11. space convertor according to claim 8, which is characterized in that further include multiple empty contact zones, each sky connects
Touching area includes multiple empty contact points, and the upper surface of second layered body is in rectangle, and the multiple sky contact zone is laid in described
Four corners, centers of gravity of the upper surface of the second layered body and on the basis of center of gravity along an X axis and a Y-axis extend and with institute
State four blocks of the upper surface periphery intersection of the second layered body.
12. space convertor according to claim 2, which is characterized in that connect under the first of each space conversion block
The contact point distribution that the contact point in touching area is distributed contact zone on than described first is more dense.
13. a kind of probe card, which is characterized in that the probe card includes:
Such as the described in any item space convertors of claim 1 to 12；
One circuit board is set to the upper surface of the thickening layer body；And
One probe is electrically connected at the first lower contact zone of each space conversion block of first layered body.
14. a kind of manufacturing method of space convertor, manufactured space convertor is suitable for a probe card, the probe card
Suitable for detecting a wafer, the wafer includes multiple crystal grain, and each crystal grain can be packaged into a collection with an integrated circuit board
At circuit chip, there is a circuit layout, which is characterized in that described between the upper surface and lower surface of the integrated circuit board
Method includes:
Obtain the circuit layout of the integrated circuit board；
One core layer body is provided, includes multiple middle attachment zone blocks；And
One first layered body and one second successively are respectively formed in two surfaces of the core layer body with multilayer organic processing techniques
Layered body, first layered body include that block is converted in multiple spaces of spaced-apart relation, and block packet is converted in each space
Containing contact zone on relative to each other first and the first lower contact zone, contact zone is electrically connected in each described on each described first
Middle attachment zone block has a circuit layout between contact zone and the first lower contact zone on relative to each other described first,
And the circuit layout at least 70% or more of each space conversion block is equal to the circuit layout of the integrated circuit board；
Adjacent two described first lower contact zones are axial with a space D along one, and each described first lower contact zone has one along the axial direction
Width W, wherein D=n × W, and n is greater than 1；Second layered body includes that multiple extensions of spaced-apart relation are electrically connected area
Block, each described extend is electrically connected contact zone and the second lower contact zone on block includes relative to each other second, under each described second
Contact zone is electrically connected in each middle attachment zone block.
15. a kind of manufacturing method of probe card, manufactured probe card is suitable for one wafer of detection, and the wafer includes multiple
Crystal grain, each crystal grain can be packaged into an IC chip, the upper table of the integrated circuit board with an integrated circuit board
There is a circuit layout, which is characterized in that the method includes between face and lower surface:
Obtain the circuit layout of the integrated circuit board；
Offer includes a core layer body of multiple middle attachment zone blocks；
One first layered body and one second successively are respectively formed in two surfaces of the core layer body with multilayer organic processing techniques
Layered body, first layered body include that block is converted in multiple spaces of spaced-apart relation, and block packet is converted in each space
Containing contact zone on relative to each other first and the first lower contact zone, contact zone is electrically connected in each described on each described first
Middle attachment zone block has a circuit layout between contact zone and the first lower contact zone on relative to each other described first,
And the circuit layout at least 70% or more of each space conversion block is equal to the circuit layout of the integrated circuit board；
Adjacent two described first lower contact zones are axial with a space D along one, and each described first lower contact zone has one along the axial direction
Width W, wherein D=n × W, and n is greater than 1；Second layered body includes that multiple extensions of spaced-apart relation are electrically connected area
Block, each described extend is electrically connected contact zone and the second lower contact zone on block includes relative to each other second, under each described second
Contact zone is electrically connected in each middle attachment zone block；
A circuit board is electrically connected in contact zone on the second of each extension electrical connection block of second layered body；And
A probe is electrically connected in the first lower contact zone of each space conversion block of first layered body.
Applications Claiming Priority (4)
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| TW107117637 | 2018-05-23 | ||
| TW107117637 | 2018-05-23 | ||
| TW108116979A TWI721424B (en) | 2018-05-23 | 2019-05-16 | Space transformer, probe card, and manufacturing methods thereof |
| TW108116979 | 2019-05-16 |
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| CN110531125A true CN110531125A (en) | 2019-12-03 |
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| CN110531125B (en) | 2022-05-17 |
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