CN110504251A - Integrated circuit and ESD protection circuit - Google Patents
Integrated circuit and ESD protection circuit Download PDFInfo
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- CN110504251A CN110504251A CN201810477845.8A CN201810477845A CN110504251A CN 110504251 A CN110504251 A CN 110504251A CN 201810477845 A CN201810477845 A CN 201810477845A CN 110504251 A CN110504251 A CN 110504251A
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- 238000001514 detection method Methods 0.000 claims abstract description 83
- 238000012360 testing method Methods 0.000 claims abstract description 33
- 230000008878 coupling Effects 0.000 claims description 41
- 238000010168 coupling process Methods 0.000 claims description 41
- 238000005859 coupling reaction Methods 0.000 claims description 41
- 230000003139 buffering effect Effects 0.000 claims description 13
- 239000003990 capacitor Substances 0.000 claims description 13
- 239000000725 suspension Substances 0.000 claims description 4
- 238000007689 inspection Methods 0.000 claims 3
- 230000006378 damage Effects 0.000 abstract description 7
- 230000009286 beneficial effect Effects 0.000 abstract 1
- 230000005611 electricity Effects 0.000 description 16
- 230000003068 static effect Effects 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007667 floating Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention proposes a kind of integrated circuit and ESD protection circuit, couples a joint sheet and a core circuit, and including electrostatic discharge testing circuit, discharge circuit and switch.Electrostatic discharge testing circuit is detected on joint sheet an electrostatic discharge event whether occurs to generate a first detection signal.Discharge circuit receives first detection signal.When electrostatic discharge event occurs on joint sheet, discharge circuit provides the discharge path between joint sheet and a ground terminal according to first detection signal.Switch is coupled between core circuit and ground terminal, and is controlled by first detection signal.When in electrostatic discharge event occurs on joint sheet, switch is closed according to first detection signal.The present invention, which has, to be protected the element in core circuit not by the destruction of electrostatic charge and avoids electrostatic discharge event that caused high voltage occurs by the beneficial effect of core circuit maloperation.
Description
Technical field
The invention relates to a kind of integrated circuits, in particular to a kind of integrated with ESD protection circuit
Circuit.
Background technique
Integrated circuit is with the development of semiconductor technology, and component size has been contracted to time micron stage, to promote integrated electricity
, but there is the problem of some reliabilitys, especially with integrated circuit pair in the performance and arithmetic speed on road, but the reduction of component size
The protective capacities of static discharge (Electrostatic Discharge, ESD) influences maximum.When component size is due to advanced
Technology and reduce, the protective capacities of static discharge also reduces many, and the ESD tolerance of element is as a result caused to be greatly reduced.
Therefore, it is necessary to ESD protection circuits to be damaged to protect the components from static discharge.
Summary of the invention
Therefore, the present invention provides a kind of ESD protection circuit, couples a joint sheet and a core circuit, and including
Electrostatic discharge testing circuit, discharge circuit and switch.Electrostatic discharge testing circuit is detected on joint sheet whether to occur one quiet
Discharge event is to generate a first detection signal.Discharge circuit receives first detection signal.It is put when electrostatic occurs on joint sheet
Electric event, discharge circuit provide the discharge path between joint sheet and a ground terminal according to first detection signal.Switch
It is coupled between core circuit and ground terminal, and is controlled by first detection signal.When in electrostatic discharge event occurs on joint sheet,
Switch is closed according to first detection signal.
In one embodiment, it includes a N-type transistor that switch, which includes above-mentioned switch, has the first of coupling core circuit
The control terminal at end, the second end of coupling ground terminal and reception first detection signal.
In one embodiment, ESD protection circuit further includes a P-type transistor, has the first of coupling joint sheet
End, the second end and control terminal for coupling core circuit.When core circuit is non-is in normal manipulation mode, this P-type transistor
Control terminal suspension joint.
The present invention provides a kind of integrated circuit comprising core circuit and ESD protection circuit.Core circuit coupling
A joint sheet is connect, and there is a power end of one ground terminal of coupling.ESD protection circuit couples a joint sheet and core electricity
Road.When an electrostatic discharge event occurs on joint sheet, ESD protection circuit provide between joint sheet and ground terminal it
Between a discharge path, and block the current path between power end and ground terminal.ESD protection circuit includes electrostatic
Discharge detection circuit, discharge circuit and N-type transistor.Electrostatic discharge testing circuit is detected on joint sheet whether electrostatic occurs
Electric discharge event is to generate a detection signal.Discharge circuit receives detection signal.When putting in electrostatic discharge event occurs on joint sheet
Circuit provides discharge path according to detection signal.N-type transistor has the first end of coupling core circuit, couples ground terminal
Second end and the control terminal for receiving first detection signal.When in electrostatic discharge event, the first N-type transistor occur on joint sheet
It is closed according to detection signal to block current path.
In one embodiment, ESD protection circuit further includes a P-type transistor.This P-type transistor, which has, to be connect
It closes the first end of pad, couple the second end and control terminal of core circuit.When core circuit is non-is in a normal manipulation mode,
The control terminal suspension joint of this P-type transistor.
ESD protection circuit proposed by the invention can not only be provided when electrostatic discharge event occurs on joint sheet
Discharge current between joint sheet and ground terminal can also block the current path between core circuit and ground terminal.In this way,
The element in core circuit can be protected not by the destruction of electrostatic charge, be also avoided that caused height electricity occurs for electrostatic discharge event
Pressure allows core circuit maloperation.
Detailed description of the invention
Fig. 1 shows an embodiments according to the present invention, the ESD protection circuit for an integrated circuit.
Fig. 2 indicates ESD protection circuit according to another embodiment of the present invention.
Fig. 3 indicates ESD protection circuit according to another embodiment of the present invention.
Fig. 4 indicates the ESD protection circuit of another embodiment according to the present invention.
Fig. 5 indicates an embodiment according to the present invention, the ESD protection circuit for an integrated circuit.
Fig. 6 indicates ESD protection circuit according to another embodiment of the present invention.
Fig. 7 indicates an embodiment according to the present invention, the ESD protection circuit for an integrated circuit.
Fig. 8 shows ESD protection circuits according to another embodiment of the present invention.
Drawing reference numeral
1、7Integrated circuit:
10、70Core circuit；
11、71ESD protection circuit；
20Buffer；
30、80Control circuit；
50Reverser；
110、710Electrostatic discharge testing circuit；
111、711Discharge circuit；
112、712Switch；
113、713Reverser；
C10、C70Capacitor；
GNDGround terminal；
N10…N12、N20、N21、N50、N70…N72N-type transistor；
ND10、ND11、ND20、ND21、ND50、ND70、ND71Common node；
P10、P20、P21、P30、P50、P70、P80P-type transistor；
PADJoint sheet；
R10、R70Resistor；
S10、S11、S70Detect signal；
S20Buffering signals；
S50、S71Reverse signal；
T10、T11、T70、T71Power end；
VDDOperate voltage.
Specific embodiment
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, a preferred embodiment is cited below particularly, and match
Institute's accompanying drawings are closed, are described in detail below.
Fig. 1 is to indicate integrated circuit according to an embodiment of the invention.Refering to fig. 1, integrated circuit 1 includes core circuit
10, ESD protection circuit 11 and joint sheet PAD.ESD protection circuit 11 include electrostatic discharge testing circuit 110,
Discharge circuit 111, switch 112, power end T11.ESD protection circuit 11 couples joint sheet PAD through power end T11.Core
Electrocardio road 10 couples joint sheet PAD.In one embodiment, core circuit 10 includes that an at least single programs (one-time
Programmable, OTP) element.The power end T10 of core circuit 10 couples ground terminal GND through switch 112.When core electricity
When road 10 is in a normal manipulation mode, an operation voltage VDD is provided to joint sheet PAD；And when core circuit 10 is non-in just
When normal operation mode, joint sheet PAD will not then receive operation voltage VDD.Electrostatic discharge testing circuit 110 couples joint sheet
PAD.Core circuit 10 it is non-be in normal manipulation mode during, electrostatic discharge testing circuit 110, which is detected on joint sheet PAD, is
No upper generation electrostatic discharge event.When detecting generation electrostatic discharge event on joint sheet PAD, electrostatic discharge testing circuit
110 control discharge circuit 111 and provide a discharge path between joint sheet PAD and ground terminal GND, to allow joint sheet PAD
On electrostatic charge (static discharge current) conduct through this discharge path to ground terminal GND, protect in core circuit 10 whereby
Element not by the destruction of electrostatic charge.In addition, when detecting generation electrostatic discharge event on joint sheet PAD, static discharge
Also control switch 112 blocks the current path between power end T10 and ground terminal GND to detection circuit 110, so that without electricity
Stream flows through core circuit 10.In this way, which avoiding electrostatic discharge event occurs caused high voltage accidentally programming core circuit
10 single programmed element.It will be detailed below the various embodiments of ESD protection circuit 11.
Refering to fig. 1, electrostatic discharge testing circuit 110 includes resistor R10 and capacitor C10.Resistor R10 is coupled to electricity
Between source T11 and common node ND11, capacitor C10 is coupled between common node ND11 and ground terminal GND.Discharge circuit
111 include P-type transistor P10 and N-type transistor N10 and N11.In an embodiment of the present invention, P-type transistor P10 is with P
Type metal oxide semiconductor (P-type Metal-Oxide-Semiconductor, PMOS) is implemented, and N-type transistor
N10 and N11 are implemented with N-type metal-oxide semiconductor (MOS) (N-type Metal-Oxide-Semiconductor, NMOS).
The first end (source electrode) of P-type transistor P10 couples power end T11, and second end (drain electrode) couples common node ND11, and it is controlled
End (grid) processed couples common node ND10.The first end (drain electrode) of N-type transistor N10 couples common node ND11, and second
(source electrode) is held to couple ground terminal GND, and its control terminal (grid) couples common node ND10.According to the company of transistor P10 and N10
Framework is connect, transistor P10 and N10 form a reverser 113.The first end of N-type transistor N11 couples power end T11, and second
End coupling ground terminal GND, and its control terminal couples common node ND11.Switch 112 includes that (for example, NMOS is brilliant for N-type transistor
Body pipe) N12.The power end T10 of the first end coupling core circuit 10 of N-type transistor N12, second end couple ground terminal GND,
And its control terminal couples common node ND10.
When core circuit 10 is under normal manipulation mode, an operation voltage VDD is supplied to joint sheet PAD, ground terminal
GND has ground voltage (such as 0 volt (V)).At this point, the detection signal S10 on common node ND10 has high voltage level,
It is that common node ND10 has high voltage.The detection signal S10 of high voltage level is carried out reverse phase common by reverser 113
The detection signal S11 of low-voltage level is generated on node ND11.Specifically, the high voltage on common node ND10 turns on N
Transistor npn npn N10 simultaneously ends P-type transistor P10.Therefore, the detection signal S11 on common node ND11 has low-voltage level,
It is that common node ND11 has low-voltage (ground voltage (0V)), to end N-type transistor N11.At this point, discharge circuit 111
Discharge path for electrostatic discharge (ESD) protection is not provided.In addition, the high voltage on common node ND10 is also switched on N-type transistor
N12, to form the current path between power end T10 and ground terminal GND.Due between power end T10 and ground terminal
The formation of current path between GND, core circuit 10 this can be programmed (write-in or erasing) under normal operation.
When core circuit 10 is non-to be under normal manipulation mode, operation voltage VDD is not applied to joint sheet PAD.When
When electrostatic discharge event (for example, positive electrostatic discharge event) occurring on joint sheet PAD, the voltage instantaneous on power end T11 is improved.
At this point, the element characteristic based on capacitor C10, it is altogether that the detection signal S10 on common node ND10, which has low-voltage level,
There is low-voltage with node ND10.The detection signal S10 of low-voltage level is carried out reverse phase in common node by reverser 113
The detection signal S11 of high voltage level is generated on ND11.Specifically, the low-voltage on common node ND10 turns on p-type crystalline substance
Body pipe P10 simultaneously ends N-type transistor N10.Therefore, the detection signal S11 on common node ND11 has high voltage level, is
Common node ND11 has high voltage, N-type transistor N11 is connected.Due to the conducting of N-type transistor N11, in power end
A discharge path is formd (i.e. between joint sheet PAD and ground terminal GND) between T11 and ground terminal GND, to allow joint sheet
Electrostatic charge on PAD is conducted through this discharge path protects the element in core circuit 10 not by quiet whereby to ground terminal GND
The destruction of charge.In addition, the low-voltage on common node ND10 has been also switched off N-type transistor N12, to block between power end
Current path between T10 and ground terminal GND.Due to no longer having current path between core circuit 10 and ground terminal GND, because
Element in this core circuit 10 will not the single programmed element in maloperation, that is, core circuit 10 will not be put because of electrostatic
Electric event occurs caused high voltage and is accidentally programmed.
In other embodiments, ESD protection circuit 11 further includes buffer 20.Referring to Fig.2, buffer 20 couples
Common node ND10 detects signal S10 to receive.20 Buffer output of buffer detects signal S10, to generate buffering signals S20.
As shown in Fig. 2, buffer 20 includes N-type transistor N20~N21 and P-type transistor P20 and P21.In the embodiment of the present invention
In, P-type transistor P20 and P21 is to be implemented with PMOS transistor, and N-type transistor N20~N21 is come with NMOS transistor
Implement.The first end (source electrode) of P-type transistor P20 couples power end T11, and second end (drain electrode) couples common node ND20,
And its control terminal (grid) couples common node ND10.The first end (drain electrode) of N-type transistor N20 couples common node ND20,
Its second end (source electrode) couples ground terminal GND, and its control terminal (grid) couples common node ND10.The of P-type transistor P21
One end couples power end T11, and second end couples common node ND21, and its control terminal couples common node ND20.N-type crystal
The first end of pipe N21 couples common node ND21, and second end couples ground terminal GND, and its control terminal couples common node
ND20.Buffering signals S20 results from common node ND21.
When core circuit 10 is under normal manipulation mode, the detection signal S10 on common node ND10 has high electricity
Level is pressed, is that common node ND10 has high voltage.High voltage on common node ND10 turns on N-type transistor N20 simultaneously
End P-type transistor P20.Therefore, the signal on common node ND20 has low-voltage level, is that common node ND20 has
Low-voltage (ground voltage (0V)), to turn on P-type transistor P21 and end N-type transistor N21.At this point, common node ND21
On buffering signals S20 have high voltage level so that N-type transistor N12 be connected, with form between power end T10 with connect
Current path between ground terminal GND.
When core circuit 10 is non-to be under normal manipulation mode, operation voltage VDD is not applied to joint sheet PAD.When
When electrostatic discharge event occurring on joint sheet PAD, the voltage instantaneous on power end T11 is improved.At this point, based on capacitor C10's
Element characteristic, the detection signal S10 on common node ND10 have low-voltage level, are that common node ND10 has low electricity
Pressure.Low-voltage on common node ND10 turns on P-type transistor P20 and ends N-type transistor N20.Therefore, common node
Signal on ND20 has high voltage level, is that node ND20 has high voltage, to turn on N-type transistor N21 and end P
Transistor npn npn P21.At this point, the buffering signals S20 on common node ND21 has low-voltage level, so that N-type transistor N12 is cut
Only, to block the current path between power end T10 and ground terminal GND.Other circuit/element circuit framves in Fig. 2
Structure and operation as earlier figures 1 operation as described in the examples, in this description will be omitted.
Refering to Fig. 3, in some embodiments, ESD protection circuit 11 further includes P-type transistor P30 and control electricity
Road 30.In an embodiment of the present invention, P-type transistor P30 is implemented with PMOS transistor.The first end of P-type transistor P30
(source electrode) couples joint sheet PAD, and second end (drain electrode) couples core circuit 10, and its control terminal (grid) couples control circuit
30.When core circuit 10 is in normal manipulation mode and will be programmed, control circuit 30 generates control signal S30 so that P is connected
Transistor npn npn P30.When core circuit 10 is non-to be under normal manipulation mode, control circuit 30, which does not operate, does not also generate control letter
Number S30, so that the control terminal of P-type transistor P30 is in floating.When electrostatic discharge event occurs on joint sheet PAD,
The internal driving of P-type transistor P30 can stop electrostatic charge to enter core circuit 10.Other circuit/element circuit framves in Fig. 3
Structure and operation as earlier figures 1 operation as described in the examples, in this description will be omitted.
Refering to Fig. 4, in some embodiments, ESD protection circuit 11 further includes p-type crystalline substance in addition to including buffer 20
Body pipe P30 and control circuit 30.In Fig. 4 the circuit framework of each circuit/element of ESD protection circuit 11 and operation as
The operation as described in the examples of earlier figures 1- Fig. 3, in this description will be omitted.
In the embodiment of above-mentioned Fig. 1-Fig. 2, the control terminal of N-type transistor N12 is to receive detection signal S10 or reception
The buffering signals S20 that will test signal S10 Buffer output and obtain.In other embodiments, the control terminal of N-type transistor N12
It can receive the reverse signal obtained after will test signal S11 reverse phase.Refering to Fig. 5, ESD protection circuit 11 further includes anti-
To device 50, couple between common node ND11 and the control terminal of N-type transistor N12.Reverser 50 receives detection signal S11,
Reverse signal S50 will be generated after its reverse phase, and be provided to the control terminal of N-type transistor N12.Refering to Fig. 5, reverser 50 includes N
Transistor npn npn N50 and P-type transistor P50.In an embodiment of the present invention, P-type transistor P50 is come in fact with PMOS transistor
It applies, and N-type transistor N50 is implemented with NMOS transistor.The first end (source electrode) of P-type transistor P50 couples power end
T11, second end (drain electrode) couples common node ND50, and its control terminal (grid) couples common node ND11.N-type transistor
The first end (drain electrode) of N50 couples common node ND50, and second end (source electrode) couples ground terminal GND, and its control terminal (grid
Pole) coupling common node ND11.Reverse signal S50 results from common node ND50.
When core circuit 10 is under normal manipulation mode, the detection signal S10 on common node ND10 has high electricity
Level is pressed, is that common node ND10 has high voltage.Through the operation of reverser 113, low electricity is generated on common node ND11
Press the signal S11 of level.Low-voltage on common node ND11 turns on P-type transistor P50 and ends N-type transistor N50.Cause
This, the reverse signal S50 on common node ND50 has high voltage level, is that common node ND50 has high voltage, so that N
Transistor npn npn N12 conducting, to form the current path between power end T10 and ground terminal GND.
When core circuit 10 is non-to be under normal manipulation mode, operation voltage VDD is not applied to joint sheet PAD.When
When electrostatic discharge event occurring on joint sheet PAD, the voltage instantaneous on power end T11 is improved.At this point, based on capacitor C10's
Element characteristic, the detection signal S10 on common node ND10 have low-voltage level, are that common node ND10 has low electricity
Pressure.Through the operation of reverser 113, the signal S11 of high voltage level is generated on common node ND11.On common node ND11
High voltage turns on N-type transistor N50 and ends P-type transistor P50.Therefore, the reverse signal S50 tool on common node ND50
There is low-voltage level, is that common node ND50 has low-voltage, so that N-type transistor N12 ends, to block between power end
Current path between T10 and ground terminal GND.Other circuit/element circuit frameworks and operation in Fig. 5 are such as earlier figures 1
Operation as described in the examples, in this description will be omitted.
In the embodiment of above-mentioned Fig. 3, the control terminal of N-type transistor N12 is to receive detection signal S10.In other realities
It applies in example, as shown in fig. 6, the control terminal of N-type transistor N12, which can receive, will test with P-type transistor P30
The reverse signal obtained after signal S11 reverse phase.Refering to Fig. 6, the embodiment with Fig. 3 is comparatively, ESD protection circuit
11 further include reverser 50.The circuit framework of reverser 50 and operation as earlier figures 5 operation as described in the examples, herein
It omits the description.
Fig. 7 is to indicate integrated circuit according to another embodiment of the present invention.Refering to Fig. 7, integrated circuit 7 includes core circuit
70, ESD protection circuit 71 and joint sheet PAD.ESD protection circuit 71 include electrostatic discharge testing circuit 710,
Discharge circuit 711, switch 712, reverser 713, power end T71.ESD protection circuit 71 connects through power end T71
Close pad PAD.Core circuit 70 couples joint sheet PAD.In one embodiment, core circuit 70 is programmed including an at least single
(one-time programmable, OTP) element.The power end T70 of core circuit 70 couples ground terminal through switch 712
GND.When core circuit 70 is in a normal manipulation mode, an operation voltage VDD is provided to joint sheet PAD；And when core electricity
Road 70 it is non-be in normal manipulation mode when, joint sheet PAD will not then receive operation voltage VDD.Electrostatic discharge testing circuit 710
Couple joint sheet PAD.Core circuit 70 it is non-be in normal manipulation mode during, electrostatic discharge testing circuit 710 is detected on
Whether joint sheet PAD is upper to occur electrostatic discharge event.When detecting generation electrostatic discharge event on joint sheet PAD, electrostatic is put
Power detection circuit 710 then controls a discharge path of the offer of discharge circuit 711 between joint sheet PAD and ground terminal GND, to allow
Electrostatic charge (static discharge current) on joint sheet PAD is conducted through this discharge path to ground terminal GND, protects core whereby
Element in circuit 70 is not by the destruction of electrostatic charge.In addition, when detecting generation electrostatic discharge event on joint sheet PAD,
Also control switch 712 blocks the current path between power end T70 and ground terminal GND to electrostatic discharge testing circuit 710, makes
It obtains no electric current and flows through core circuit 70.It is accidentally programmed in this way, avoid electrostatic discharge event and caused high voltage occurs
The single programmed element of core circuit 10.It will be detailed below the various embodiments of ESD protection circuit 71.
Refering to Fig. 7, electrostatic discharge testing circuit 710 includes capacitor C70 and resistor R70.Capacitor C70 is coupled to electricity
Between source T71 and common node ND70, it is coupled between common node ND70 and ground terminal GND.Discharge circuit 711 includes N
Transistor npn npn N70.In an embodiment of the present invention, N-type transistor N70 is implemented with NMOS transistor.N-type transistor N70
First end (drain electrode) couple power end T71, second end (source electrode) couple ground terminal GND, and its control terminal (grid) couple
Common node ND70.Reverser 713 is coupled between common node ND70 and switch 712.Reverser 713 includes N-type transistor
N71 and P-type transistor P70.In an embodiment of the present invention, P-type transistor P70 is implemented with PMOS transistor, and N-type
Transistor N71 is implemented with NMOS transistor.The first end (source electrode) of P-type transistor P70 couples power end T71, and second
(drain electrode) is held to couple common node ND71, and its control terminal (grid) couples common node ND70.The first of N-type transistor N71
(drain electrode) is held to couple common node ND71, second end (source electrode) couples ground terminal GND, and the coupling of its control terminal (grid) is common
Node ND70.Switch 712 includes N-type transistor N72.The power end of the first end coupling core circuit 70 of N-type transistor N72
T70, second end couples ground terminal GND, and its control terminal couples common node ND71.
When core circuit 70 is under normal manipulation mode, an operation voltage VDD is supplied to joint sheet PAD, ground terminal
GND has ground voltage (such as 0 volt (V)).At this point, the detection signal S70 on common node ND70 has low-voltage level,
It is that common node ND70 has low-voltage, to end N-type transistor N11.At this point, discharge circuit 711 is not provided for electrostatic
The discharge path of discharge prevention.The detection signal S70 of low-voltage level is carried out reverse phase in common node ND71 by reverser 713
The upper reverse signal S71 for generating low-voltage level.Specifically, the low-voltage on common node ND70 turns on P-type transistor
P70 simultaneously ends N-type transistor N71.Therefore, the reverse signal S71 on common node ND71 has high voltage level, is common
Node ND71 has high voltage, N-type transistor N72 is connected.Therefore, it forms between power end T70 and ground terminal GND
Current path.Due to the formation of the current path between power end T70 and ground terminal GND, core circuit 70 can be just
Lower this of often operation is programmed (write-in or erasing).
When core circuit 10 is non-to be under normal manipulation mode, operation voltage VDD is not applied to joint sheet PAD.When
When electrostatic discharge event (for example, positive electrostatic discharge event) occurring on joint sheet PAD, the voltage instantaneous on power end T71 is improved.
At this point, the element characteristic based on capacitor C70, it is altogether that the detection signal S70 on common node ND70, which has high voltage level,
There is high voltage with node ND70, N-type transistor N70 is connected.Due to the conducting of N-type transistor N70, in power end
A discharge path is formd (i.e. between joint sheet PAD and ground terminal GND) between T71 and ground terminal GND, to allow joint sheet
Electrostatic charge on PAD is conducted through this discharge path protects the element in core circuit 70 not by quiet whereby to ground terminal GND
The destruction of charge.The detection signal S70 of high voltage level is carried out reverse phase to generate on common node ND71 by reverser 713
The reverse signal S71 of low-voltage level.Specifically, the high voltage on common node ND70 is connected N-type transistor N71 and cuts
Only P-type transistor P70.Therefore, the reverse signal S71 on common node ND71 has low-voltage level, is common node
ND71 has low-voltage, to end N-type transistor N72.The N-type transistor N72 of cut-off has been blocked between power end T70 and ground connection
Hold the current path between GND.Due to no longer having current path, core electricity between core circuit 70 and ground terminal GND
Element in road 70 will not the single programmed element in maloperation, that is, core circuit 70 will not be sent out because of electrostatic discharge event
It gives birth to caused high voltage and is accidentally programmed.
In some embodiments, refering to Fig. 8, ESD protection circuit 71 further includes P-type transistor P80 and control electricity
Road 80.In an embodiment of the present invention, P-type transistor P80 is implemented with PMOS transistor.The first end of P-type transistor P80
(source electrode) couples joint sheet PAD, and second end (drain electrode) couples core circuit 70, and its control terminal (grid) couples control circuit
80.When core circuit 70 is in normal manipulation mode and will be programmed, control circuit 80 generates control signal S80 so that P is connected
Transistor npn npn P80.When core circuit 70 is non-to be under normal manipulation mode, control circuit 80, which does not operate, does not also generate control letter
Number S80, so that the control terminal of P-type transistor P80 is in floating.When electrostatic discharge event occurs on joint sheet PAD,
The internal driving of P-type transistor P80 can stop electrostatic charge to enter core circuit 80.Other circuit/element circuit framves in Fig. 8
Structure and operation as earlier figures 7 operation as described in the examples, in this description will be omitted.
According to the above embodiments, static discharge occurs on joint sheet for ESD protection circuit proposed by the invention
When event, the discharge current between joint sheet and ground terminal can not only be provided, can also be blocked between core circuit and ground terminal
Current path.In this way, which the element in core circuit can be protected not by the destruction of electrostatic charge, it is also avoided that static discharge thing
Caused high voltage occurs for part by core circuit maloperation.
Though the present invention is disclosed above in the preferred embodiment, the range that however, it is not to limit the invention, art technology
Personnel, without departing from the spirit and scope of the present invention, when can do a little change and retouching, therefore protection scope of the present invention
Subject to view claim institute defender.
Claims (28)
1. a kind of ESD protection circuit couples a joint sheet and a core circuit characterized by comprising
One electrostatic discharge testing circuit is detected on the joint sheet and an electrostatic discharge event whether occurs to generate one first detection
Signal；
One discharge circuit receives the first detection signal, wherein when in the electrostatic discharge event occurs on the joint sheet, this is put
Circuit provides the discharge path between the joint sheet and a ground terminal according to the first detection signal；And
One switch, is coupled between the core circuit and the ground terminal, is controlled by the first detection signal, wherein connect when in this
It closes and the electrostatic discharge event occurs on pad, which closes according to the first detection signal.
2. ESD protection circuit as described in claim 1, which is characterized in that the switch includes:
One N-type transistor, have couple the core circuit first end, couple the second end of the ground terminal and receive this first
Detect the control terminal of signal.
3. ESD protection circuit as described in claim 1, which is characterized in that further include:
One buffer is coupled between the electrostatic discharge testing circuit and the switch, receives the first detection signal and according to this
First detection signal and generate a buffering signals to the switch；
Wherein, when in the electrostatic discharge event occurs on the joint sheet, which surveys signal according to the buffering and close.
4. ESD protection circuit as claimed in claim 3, which is characterized in that the buffer includes:
One first P-type transistor has the first end for coupling the joint sheet, couples the second end of a first node and receive and be somebody's turn to do
The control terminal of first detection signal；
One first N-type transistor has the first end for coupling the first node, couples the second end of the ground terminal and receive and be somebody's turn to do
The control terminal of first detection signal；
One second P-type transistor, the second end and coupling that there is the first end for coupling the joint sheet, couple a second node
The control terminal of one node；And
One second N-type transistor, the second end and coupling that there is the first end for coupling the second node, couple the ground terminal
The control terminal of one node；
Wherein, which results from the second node.
5. ESD protection circuit as described in claim 1, which is characterized in that the discharge circuit generates and first detection
One second reversed each other detection signal of signal, and the ESD protection circuit further include:
One reverser is coupled between the discharge circuit and the switch, to receive the second detection signal and according to second inspection
It surveys signal and generates a reverse signal to the switch；
Wherein, when in the electrostatic discharge event occurs on the joint sheet, which closes according to the reverse signal.
6. ESD protection circuit as described in claim 1, which is characterized in that further include:
One reverser is coupled between the electrostatic discharge testing circuit and the switch, with receive the first detection signal and according to
The first detection signal and generate a reverse signal to the switch；
Wherein, when in the electrostatic discharge event occurs on the joint sheet, which closes according to the reverse signal.
7. ESD protection circuit as claimed in claim 6, which is characterized in that the electrostatic discharge testing circuit includes:
One capacitor is coupled between the joint sheet and a first node；And
One resistor is coupled between the first node and the ground terminal；
Wherein, which results from the first node.
8. ESD protection circuit as described in claim 1, which is characterized in that further include:
One first P-type transistor, the second end and control that there is the first end for coupling the joint sheet, couple the core circuit
End；
Wherein, when the core circuit is non-is in a normal manipulation mode, the control terminal suspension joint of first P-type transistor.
9. ESD protection circuit as claimed in claim 8, which is characterized in that when the core circuit is in a normal operating
When mode, the control terminal of first P-type transistor receives a control signal.
10. ESD protection circuit as claimed in claim 8, which is characterized in that the switch includes:
One N-type transistor, have couple the core circuit first end, couple the second end of the ground terminal and receive this first
Detect the control terminal of signal.
11. ESD protection circuit as claimed in claim 8, which is characterized in that further include:
One buffer is coupled between the electrostatic discharge testing circuit and the switch, receives the first detection signal and according to this
First detection signal and generate a buffering signals to the switch；
Wherein, when in the electrostatic discharge event occurs on the joint sheet, which surveys signal according to the buffering and close.
12. ESD protection circuit as claimed in claim 11, which is characterized in that the buffer includes:
One second P-type transistor, the second end and reception that there is the first end for coupling the joint sheet, couple a first node
The control terminal of the first detection signal；
One first N-type transistor has the first end for coupling the first node, couples the second end of the ground terminal and receive and be somebody's turn to do
The control terminal of first detection signal；
One third P-type transistor, the second end and coupling that there is the first end for coupling the joint sheet, couple a second node
The control terminal of first node；And
One second N-type transistor, the second end and coupling that there is the first end for coupling the second node, couple the ground terminal
The control terminal of one node；
Wherein, which results from the second node.
13. ESD protection circuit as claimed in claim 8, which is characterized in that the discharge circuit generates and first inspection
Survey one second reversed each other detection signal of signal, and the ESD protection circuit further include:
One reverser is coupled between the discharge circuit and the switch, to receive the second detection signal and according to second inspection
It surveys signal and generates a reverse signal to the switch；
Wherein, when in the electrostatic discharge event occurs on the joint sheet, which closes according to the reverse signal.
14. ESD protection circuit as claimed in claim 8, which is characterized in that further include:
One reverser is coupled between the electrostatic discharge testing circuit and the switch, with receive the first detection signal and according to
The first detection signal and generate a reverse signal to the switch；
Wherein, when in the electrostatic discharge event occurs on the joint sheet, which closes according to the reverse signal.
15. ESD protection circuit as claimed in claim 14, which is characterized in that the electrostatic discharge testing circuit includes:
One capacitor is coupled between the joint sheet and a first node；And
One resistor is coupled between the first node and the ground terminal；
Wherein, which results from the first node.
16. a kind of integrated circuit characterized by comprising
One core circuit couples a joint sheet, has a power end of one ground terminal of coupling；And
One ESD protection circuit, the coupling one joint sheet and core circuit, wherein when in an electrostatic occurs on the joint sheet
When electric discharge event, which provides the discharge path between the joint sheet and the ground terminal, and hinders
The current path to break between the power end and the ground terminal, wherein the ESD protection circuit includes:
One electrostatic discharge testing circuit is detected on the joint sheet and the electrostatic discharge event whether occurs to generate one first detection
Signal；
One discharge circuit receives the first detection signal, wherein when in the electrostatic discharge event occurs on the joint sheet, this is put
Circuit provides the discharge path according to the first detection signal；And
One first N-type transistor has the first end for coupling the core circuit, couples the second end of the ground terminal and receive and be somebody's turn to do
The control terminal of first detection signal, wherein when in the electrostatic discharge event occurs on the joint sheet, the first N-type transistor root
It closes according to the first detection signal to block the current path.
17. integrated circuit as claimed in claim 16, which is characterized in that further include:
One buffer is coupled between the electrostatic discharge testing circuit and the control terminal of first N-type transistor, receive this first
Detection signal and the control terminal that a buffering signals to first N-type transistor are generated according to the first detection signal；
Wherein, when in the electrostatic discharge event occurs on the joint sheet, which surveys signal according to the buffering and close
It closes to block the current path.
18. integrated circuit as claimed in claim 17, which is characterized in that the buffer includes:
One first P-type transistor has the first end for coupling the joint sheet, couples the second end of a first node and receive and be somebody's turn to do
The control terminal of first detection signal；
One second N-type transistor has the first end for coupling the first node, couples the second end of the ground terminal and receive and be somebody's turn to do
The control terminal of first detection signal；
One second P-type transistor, the second end and coupling that there is the first end for coupling the joint sheet, couple a second node
The control terminal of one node；And
One third N-type transistor, the second end and coupling that there is the first end for coupling the second node, couple the ground terminal
The control terminal of one node；
Wherein, which results from the second node.
19. integrated circuit as claimed in claim 16, which is characterized in that the discharge circuit generates mutual with the first detection signal
Signal, and the ESD protection circuit are detected for reversed one second further include:
One reverser is coupled between the discharge circuit and the control terminal of first N-type transistor, to receive the second detection letter
Number and the control terminal of a reverse signal to first N-type transistor is generated according to the second detection signal；
Wherein, when in the electrostatic discharge event occurs on the joint sheet, which closes according to the reverse signal
To block the current path.
20. integrated circuit as claimed in claim 16, which is characterized in that the ESD protection circuit further include:
One reverser is coupled between the electrostatic discharge testing circuit and the control terminal of first N-type transistor, with receive this
One detection signal and the control terminal that a reverse signal to first N-type transistor is generated according to the first detection signal；
Wherein, when in the electrostatic discharge event occurs on the joint sheet, which closes according to the reverse signal
To block the current path.
21. integrated circuit as claimed in claim 20, which is characterized in that the electrostatic discharge testing circuit includes:
One capacitor is coupled between the joint sheet and a first node；And
One resistor is coupled between the first node and the ground terminal；
Wherein, which results from the first node.
22. integrated circuit as claimed in claim 16, which is characterized in that the ESD protection circuit further include:
One first P-type transistor, the second end and control that there is the first end for coupling the joint sheet, couple the core circuit
End；
Wherein, when the core circuit is non-is in a normal manipulation mode, the control terminal suspension joint of first P-type transistor.
23. integrated circuit as claimed in claim 22, which is characterized in that when the core circuit is in a normal manipulation mode
When, the control terminal of first P-type transistor receives a control signal.
24. integrated circuit as claimed in claim 22, which is characterized in that further include:
One buffer is coupled between the electrostatic discharge testing circuit and the control terminal of first N-type transistor, receive this first
Detection signal and the control terminal that a buffering signals to first N-type transistor are generated according to the first detection signal；
Wherein, when in the electrostatic discharge event occurs on the joint sheet, which surveys signal according to the buffering and close
It closes to block the current path.
25. integrated circuit as claimed in claim 24, which is characterized in that the buffer includes:
One second P-type transistor has the first end for coupling the joint sheet, couples the second end of a first node and receive and be somebody's turn to do
The control terminal of first detection signal；
One second N-type transistor has the first end for coupling the first node, couples the second end of the ground terminal and receive and be somebody's turn to do
The control terminal of first detection signal；
One third P-type transistor, the second end and coupling that there is the first end for coupling the joint sheet, couple a second node
The control terminal of one node；And
One third N-type transistor, the second end and coupling that there is the first end for coupling the second node, couple the ground terminal
The control terminal of one node；
Wherein, which results from the second node.
26. integrated circuit as claimed in claim 22, which is characterized in that the discharge circuit generates mutual with the first detection signal
Signal, and the ESD protection circuit are detected for reversed one second further include:
One reverser is coupled between the discharge circuit and the control terminal of first N-type transistor, to receive the second detection letter
Number and the control terminal of a reverse signal to first N-type transistor is generated according to the second detection signal；
Wherein, when in the electrostatic discharge event occurs on the joint sheet, which closes according to the reverse signal
To block the current path.
27. integrated circuit as claimed in claim 22, which is characterized in that further include:
One reverser is coupled between the electrostatic discharge testing circuit and the control terminal of first N-type transistor, with receive this
One detection signal and the control terminal that a reverse signal to first N-type transistor is generated according to the first detection signal；
Wherein, when in the electrostatic discharge event occurs on the joint sheet, which closes according to the reverse signal
To block the current path.
28. integrated circuit as claimed in claim 27, which is characterized in that the electrostatic discharge testing circuit includes:
One capacitor is coupled between the joint sheet and a first node；And
One resistor is coupled between the first node and the ground terminal；
Wherein, which results from the first node.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810477845.8A CN110504251B (en) | 2018-05-18 | 2018-05-18 | Integrated circuit and electrostatic discharge protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810477845.8A CN110504251B (en) | 2018-05-18 | 2018-05-18 | Integrated circuit and electrostatic discharge protection circuit |
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| CN110504251A true CN110504251A (en) | 2019-11-26 |
| CN110504251B CN110504251B (en) | 2021-12-24 |
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| CN201810477845.8A Active CN110504251B (en) | 2018-05-18 | 2018-05-18 | Integrated circuit and electrostatic discharge protection circuit |
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| CN112350290A (en) * | 2019-08-06 | 2021-02-09 | 世界先进积体电路股份有限公司 | Operating circuit |
| CN114069580A (en) * | 2020-08-04 | 2022-02-18 | 世界先进积体电路股份有限公司 | Protective circuit |
| US11387649B2 (en) * | 2019-09-11 | 2022-07-12 | Vanguard International Semiconductor Corporation | Operating circuit having ESD protection function |
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Also Published As
| Publication number | Publication date |
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| CN110504251B (en) | 2021-12-24 |
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