CN110491829A - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

Info

Publication number
CN110491829A
CN110491829A CN201811571109.5A CN201811571109A CN110491829A CN 110491829 A CN110491829 A CN 110491829A CN 201811571109 A CN201811571109 A CN 201811571109A CN 110491829 A CN110491829 A CN 110491829A
Authority
CN
China
Prior art keywords
substrate
face
component substrate
rie
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201811571109.5A
Other languages
English (en)
Other versions
CN110491829B (zh
Inventor
志摩真也
久米一平
秦栄一
高野英治
白野贵士
藤井美香
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asahi Co Ltd
Original Assignee
Asahi Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asahi Co Ltd filed Critical Asahi Co Ltd
Publication of CN110491829A publication Critical patent/CN110491829A/zh
Application granted granted Critical
Publication of CN110491829B publication Critical patent/CN110491829B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02013—Grinding, lapping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02016—Backside treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H01L2221/68386—Separation by peeling

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

实施方式提供一种能够抑制贯通电极的不良的半导体装置的制造方法。实施方式的半导体装置的制造方法包含如下步骤：经由接着剂而将在第1面形成着元件的元件衬底的第1面贴合在支撑衬底；将元件衬底贴合在所述支撑衬底后，基于通过RIE形成半导体衬底时的面内加工速率，对元件衬底的第1面的相反面的第2面侧进行研磨使其薄化；将元件衬底薄化后，通过RIE而形成从第2面侧朝向第1面侧贯通元件衬底的孔；及在孔中填入金属而形成贯通电极。

Description

半导体装置的制造方法
[相关申请案]
本申请案享有以日本专利申请2018-92900号(申请日：2018年5月14日)为基础申请案的优先权。本申请案通过参照该基础申请案而包含基础申请案的所有内容。
技术领域
本发明的实施方式涉及一种半导体装置的制造方法。
背景技术
在半导体装置形成贯通电极的方法中，有以下方法：在形成着半导体元件的一侧的元件衬底的正面贴合支撑衬底，在对支撑衬底进行支撑的状态下从背面侧对元件衬底进行研磨使其薄化后，通过RIE(Reactive Ion Etching，反应性离子蚀刻)进行加工而形成用来形成贯通电极的孔。
在通过RIE对半导体衬底进行加工而形成孔时，有时在半导体元件的每个区域蚀刻速率(加工速率)会产生偏差。如果蚀刻速率在每个区域产生偏差，那么在对元件衬底过度地进行加工的情况下，孔的底部的形状与开口部相比成为宽幅的形状，在元件衬底的加工不充分的情况下，孔的底部的形状与开口部相比成为较细的形状。在形成了在深度方向上宽度不同的贯通电极(TSV，THROUGH SILICON VIA)的情况下，与具有同样宽度的贯通电极相比，由于电阻不同而成为元件不良的原因。
因此，需要适当管理孔的底部的宽度。然而，在晶圆的中心区域与外周区域会产生RIE制程的面内倾向。为了减小这种面内倾向的影响，提高孔的加工精度，有使用较慢的蚀刻速率的条件进行加工的方法，但存在生产性降低的问题。
发明内容
实施方式提供一种能够抑制贯通电极的不良的半导体装置的制造方法。
实施方式的半导体装置的制造方法包含如下步骤：经由接着剂而将在第1面形成着元件的元件衬底的第1面贴合在支撑衬底；将元件衬底贴合在所述支撑衬底后，基于通过RIE形成半导体衬底时的面内加工速率，对元件衬底的第1面的相反面的第2面侧进行研磨使其薄化；将元件衬底薄化后，通过RIE形成从第2面侧朝向第1面侧贯通元件衬底的孔；及在孔中填入金属而形成贯通电极。
附图说明
图1(a)～(d)是实施方式1的半导体装置的制造步骤的剖视说明图。
图2是对实施方式的RIE的面内的蚀刻速率进行说明的图。
图3(a)～(d)是实施方式2的半导体装置的制造步骤的剖视说明图。
图4(a)～(d)是实施方式3的半导体装置的制造步骤的剖视说明图。
具体实施方式
以下，参照附图，对实施方式的半导体装置的制造方法详细地进行说明。此外，本发明并不由该实施方式限定。
(实施方式1)
图1是实施方式1的半导体装置的制造步骤的剖视说明图。如图1(a)所示，准备在正面(第1面)侧包含多个半导体元件102a的元件衬底101a。多个半导体元件102a例如为具有NAND(Not AND，与非)型EEPROM(ELECTRICALLY ERASABLE AND PROGRAMMABLE READ-ONLYMEMORY，电可擦编程只读存储器)等的半导体存储芯片。元件衬底10例如为具有大致圆盘形状的硅晶圆等。
其后，如图1(b)所示，经由第1接着剂104而将元件衬底101a的正面侧贴合在支撑衬底103。由此，在下述对元件衬底101a进行研磨的步骤中能够良好地对元件衬底101a的背面进行加工。支撑衬底103例如为使用玻璃或硅等，且直径及厚度与元件衬底10大致相同的圆盘状的衬底。此外，支撑衬底103的材料、直径、及厚度等形状并不限定于此。
然后，如图1(c)所示，基于下述元件衬底101a的面内的RIE的蚀刻速率，使用研磨机从背面(第2面)101b侧对元件衬底101a进行研磨使其薄化。经薄化的衬底设为元件衬底101c。在本实施方式中，元件衬底101c的中心区域的厚度例如比元件衬底101c的外周区域的厚度更厚。另外，元件衬底101c的外周区域向内侧倾斜。由于下述RIE制程中对元件衬底(Si)等向地进行蚀刻，因而为了将孔的底部的直径偏差抑制到2μm以下而必须进行薄化以将元件衬底(Si)的厚度设为所期望的厚度的±2μm以下。
然后，如图1(d)所示，通过RIE对元件衬底101c的背面侧进行加工而形成多个孔H。多个孔H为贯通元件衬底101c的孔。经加工的衬底设为元件衬底101d。在图1(d)中，每个元件衬底101c的区域的RIE的加工速率例如设为在元件衬底101c的中心区域较大，在元件衬底101c的外周区域较小。
其后，在多个孔中填入金属而形成多个贯通电极(未图示)。将形成了贯通电极的元件衬底101d从支撑衬底103剥离，将该元件衬底101d单片化。通过积层多层经单片化的元件衬底101d而形成半导体芯片。
图2是对实施方式1的元件衬底的面内的RIE的蚀刻速率进行说明的图。在图2中，横轴表示距元件衬底的中心的距离，纵轴表示通过RIE进行加工时的加工速率。在本实施方式中，RIE的加工速率在元件衬底101a的中心区域较大，在外周区域较小，进而，在外周区域，越远离中心区域越小。因此，在想要通过RIE来加工厚度均匀的元件衬底时，会产生元件衬底101被过度加工的情况或元件衬底101a未被充分加工的情况。
在元件衬底101a被过度加工的情况下，孔的底部的直径变大。形成孔后，在孔内通过PVD(Physical Vapor Deposition，物理气相沉积)等形成包含Ti等金属的阻隔金属，但在孔的底部难以形成膜厚充分的阻隔金属。因此，会阻碍在孔内形成贯通电极时的镀层生长，导致产生开路不良。另外，因阻隔性不充分而导致贯通电极所包含的Cu等金属扩散到半导体衬底，引起产生漏电不良。
在元件衬底101a的加工不充分的情况下，产生开路不良。
在本实施方式中，基于元件衬底101c的利用RIE的面内的蚀刻速率(加工速率)，以外周区域的厚度比中心区域的厚度变得更薄的方式对元件衬底101c的背面进行研磨、薄化。由此，能够防止元件衬底被过度加工，或元件衬底未被充分加工。由此，能够抑制形成直径随深度不同的孔。也就是说，能够形成多个具有均匀直径的贯通电极。
此外，在本实施方式中，也可以通过RIE对预先另外准备的元件衬底101a进行加工，并对加工后元件衬底进行测定，从而根据获得的测定结果来推算每个区域的蚀刻速率。
(实施方式2)
如图3(a)所示，准备在正面侧包含多个半导体元件202a的元件衬底201a。
在实施方式1中，元件衬底101a与支撑衬底103是经由厚度均匀的第1接着剂104而贴合，但在实施方式2中，基于RIE的面内的蚀刻速率(加工速率)来控制第2接着剂204的厚度。由此，形成在第2接着剂204上的元件衬底201a是以因下方凸起而翘起的状态贴合在支撑衬底203。第2实施方式的其他构成可以与第1实施方式的对应构成相同。
其后，如图3(b)所示，经由第2接着剂204而将元件衬底201a的正面侧贴合在支撑衬底203。此时，例如基于如图2所示的RIE的面内的蚀刻速率(加工速率)来控制第2接着剂204的厚度。例如，第2接着剂204的外周区域的厚度相比中心区域的厚度更厚。由此，经由接着剂204而将元件衬底201a以因下方凸起而翘起的状态贴合在支撑衬底203。
其后，如图3(c)所示，从背面201b侧以变得平坦的方式利用研磨机对元件衬底201a进行加工、薄化。经薄化的元件衬底设为元件衬底201c。
其后，如图3(d)所示，通过RIE对元件衬底201c进行加工，在背面侧形成多个孔H，设为元件衬底201d。
其后，在多个孔H中填入金属而形成多个贯通电极(未图示)。将形成了贯通电极的元件衬底201d从支撑衬底203剥离，将该元件衬底201d单片化。通过积层多层经单片化的元件衬底201d而形成半导体芯片。
在本实施方式中，通过基于RIE的面内的蚀刻速率(加工速率)来控制第1接着剂204的厚度，而在利用研磨机进行研磨薄化时，能够获得每个区域具有所期望的厚度的元件衬底201c。由此，在通过RIE形成孔时，能够防止元件衬底201a被过度加工，或元件衬底201a未被充分加工。由此，能够抑制形成直径随深度不同的孔H。也就是说，能够形成具有均匀的直径的多个贯通电极。
(实施方式3)
在实施方式2中，使用第2接着剂204而将元件衬底贴合在支撑衬底203，但在实施方式3中，使用多种接着剂来形成多层构造的接着剂。第3实施方式的其他构成可以与第1实施方式的对应构成相同。
如图4(a)所示，准备在正面侧包含多个半导体元件302a的元件衬底301a。
其后，如图4(b)所示，经由多种接着剂而将元件衬底301a的正面侧贴合在支撑衬底303。在支撑衬底303的整面涂布第3接着剂304，在第3接着剂304的外周区域涂布第4接着剂305。此时，第3接着剂304及第4接着剂305相加的厚度例如是基于如图2所示的RIE的面内的每个区域的蚀刻速率(加工速率)来控制。其后，经由第3接着剂304及第4接着剂305而将元件衬底301a贴合在支撑衬底203。此时，元件衬底301a成为翘起第2接着剂305的厚度的状态。
其后，如图4(c)所示，从背面301b侧以变得平坦的方式利用研磨机对元件衬底301a进行加工、薄化。经薄化的元件衬底设为元件衬底301c。
然后，如图4(d)所示，通过RIE对元件衬底301c进行加工，获得在背面侧形成着多个孔H的元件衬底301d。
其后，在多个孔中填入金属而形成多个贯通电极(未图示)。将形成了贯通电极的元件衬底301d从支撑衬底303剥离，将该元件衬底301d单片化。通过积层多层经单片化的元件衬底301d而形成半导体芯片。
在本实施方式中，基于RIE的面内的每个区域的蚀刻速率(加工速率)来控制积层的接着剂的厚度，因此在从背面301b侧对元件衬底301a进行加工而使其平坦化，并对所得的元件衬底301c进行加工而形成孔时，能够防止元件衬底301c被过度加工，或元件衬底301c未被充分加工。由此，能够抑制形成直径随深度不同的孔H。也就是说，能够形成具有均匀的直径的多个贯通电极。
此外，在本实施方式中，通过组合形成在整面的第3接着剂304与局部形成的第4接着剂305来控制接着剂厚度，不过为了获得所期望的厚度的元件衬底301d，也可以视需要在内周形成第4接着剂305。另外，也可以将接着剂积层3层以上而控制接着剂的厚度。进而，在利用第3接着剂304便能足够将支撑衬底303与元件衬底301a接着的情况下，第4接着剂305也可以是不具有接着功能而仅具有厚度控制功能的材料。
对本发明的若干实施方式进行了说明，但这些实施方式是作为示例而提出的，并非意在限定发明的范围。这些新颖的实施方式能够以其他各种方式实施，在不脱离发明的主旨的的范围内，能够进行各种省略、置换、变更。这些实施方式及其变化包含在发明的范围及主旨中，且包含在权利要求书记载的发明及与其均等的范围内。

Claims (9)

1.一种半导体装置的制造方法，其包含如下步骤：
经由接着剂而将在第1面形成着元件的元件衬底的第1面贴合在支撑衬底；
将所述元件衬底贴合在所述支撑衬底后，基于通过RIE形成所述半导体衬底时的面内加工速率，对所述元件衬底的所述第1面的相反面的第2面侧进行研磨使其薄化；
将所述元件衬底薄化后，通过RIE而形成从所述第2面侧朝向所述第1面侧贯通所述元件衬底的孔；及
在所述孔中填入金属而形成贯通电极。
2.根据权利要求1所述的半导体装置的制造方法，其中在所述进行薄化的步骤中，以外周区域的厚度变得比中心区域的厚度更薄的方式对所述元件衬底进行加工。
3.根据权利要求2所述的半导体装置的制造方法，其中在所述形成孔的步骤中，所述元件衬底的外周区域的加工速率小于中心区域的加工速率。
4.根据权利要求1至3中任一项所述的半导体装置的制造方法，其中通过所述RIE形成所述半导体衬底时的面内加工速率是预先通过RIE对与所述元件衬底不同的另一衬底进行加工，并测定加工后的所述另一衬底而得到的。
5.一种半导体装置的制造方法，其包含如下步骤：
基于通过RIE形成所述半导体衬底时的面内加工速率，将在第1面形成着元件的元件衬底的第1面经由第1接着剂与第2接着剂而贴合在支撑衬底；
将所述元件衬底贴合在所述支撑衬底后，对所述第1面的相反面的第2面侧进行研磨而使其薄化；
将所述元件衬底薄化后，通过RIE而形成从所述第2面侧朝向所述第1面侧贯通所述元件衬底的孔；及
在所述孔中填入金属而形成贯通电极。
6.根据权利要求5所述的半导体装置的制造方法，其中在所述进行贴合的步骤中，
所述第1接着剂设置在所述元件衬底的第1面整面，且
第2接着剂局部设置在所述第1接着剂上。
7.根据权利要求6所述的半导体装置的制造方法，其中在所述进行薄化的步骤中，以外周区域的厚度变得比中心区域的厚度更薄的方式对所述元件衬底进行加工。
8.根据权利要求7所述的半导体装置的制造方法，其中在所述形成孔的步骤中，所述元件衬底的外周区域的加工速率小于中心区域的加工速率。
9.根据权利要求5至8中任一项所述的半导体装置的制造方法，其中通过所述RIE形成所述半导体衬底时的面内加工速率是预先通过RIE对与所述元件衬底不同的另一衬底进行加工，并测定加工后的所述另一衬底而得到的。
CN201811571109.5A 2018-05-14 2018-12-21 半导体装置的制造方法 Active CN110491829B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018-092900 2018-05-14
JP2018092900A JP2019201030A (ja) 2018-05-14 2018-05-14 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
CN110491829A true CN110491829A (zh) 2019-11-22
CN110491829B CN110491829B (zh) 2023-08-29

Family

ID=68465246

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811571109.5A Active CN110491829B (zh) 2018-05-14 2018-12-21 半导体装置的制造方法

Country Status (3)

Country Link
US (1) US10804152B2 (zh)
JP (1) JP2019201030A (zh)
CN (1) CN110491829B (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001345380A (ja) * 2000-05-31 2001-12-14 Toshiba Corp 半導体装置の製造方法および半導体装置
CN101359595A (zh) * 2007-07-30 2009-02-04 中芯国际集成电路制造(上海)有限公司 晶圆表面平坦化的方法
US20130203265A1 (en) * 2012-02-08 2013-08-08 Advanced Semiconductor Engineering, Inc. Carrier bonding and detaching processes for a semiconductor wafer
US20160020129A1 (en) * 2014-07-15 2016-01-21 Micron Technology, Inc. Methods for temporarily bonding a device wafer to a carrier wafer, and related assemblies
US20160126148A1 (en) * 2014-10-31 2016-05-05 Veeco Precision Surface Processing Llc System and method for performing a wet etching process
CN107078047A (zh) * 2014-11-07 2017-08-18 国际商业机器公司 用于晶片接合的低温黏着树脂

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07235741A (ja) 1993-12-27 1995-09-05 Ngk Spark Plug Co Ltd 多層配線基板
JP2002009043A (ja) 2000-06-23 2002-01-11 Hitachi Ltd エッチング装置及びそれを用いた半導体装置の製造方法
JP2006114847A (ja) 2004-10-18 2006-04-27 Sony Corp 半導体装置、及び貼り合わせ基板の製造方法
JP2008053308A (ja) 2006-08-22 2008-03-06 Nec Electronics Corp 半導体装置の製造方法およびプラズマ処理装置
JP6042182B2 (ja) 2012-11-16 2016-12-14 株式会社ディスコ ウェーハ研削方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001345380A (ja) * 2000-05-31 2001-12-14 Toshiba Corp 半導体装置の製造方法および半導体装置
CN101359595A (zh) * 2007-07-30 2009-02-04 中芯国际集成电路制造(上海)有限公司 晶圆表面平坦化的方法
US20130203265A1 (en) * 2012-02-08 2013-08-08 Advanced Semiconductor Engineering, Inc. Carrier bonding and detaching processes for a semiconductor wafer
US20160020129A1 (en) * 2014-07-15 2016-01-21 Micron Technology, Inc. Methods for temporarily bonding a device wafer to a carrier wafer, and related assemblies
US20160126148A1 (en) * 2014-10-31 2016-05-05 Veeco Precision Surface Processing Llc System and method for performing a wet etching process
CN107078047A (zh) * 2014-11-07 2017-08-18 国际商业机器公司 用于晶片接合的低温黏着树脂

Also Published As

Publication number Publication date
CN110491829B (zh) 2023-08-29
US20190348324A1 (en) 2019-11-14
JP2019201030A (ja) 2019-11-21
US10804152B2 (en) 2020-10-13

Similar Documents

Publication Publication Date Title
US10840205B2 (en) Chemical mechanical polishing for hybrid bonding
US7902069B2 (en) Small area, robust silicon via structure and process
TWI294160B (en) Method of plugging through-holes in silicon substrate
US7425499B2 (en) Methods for forming interconnects in vias and microelectronic workpieces including such interconnects
TWI495071B (zh) 具有穿透基板互連之半導體
CN106057756B (zh) 半导体结构及其制造方法
US10199275B2 (en) Systems and methods for producing flat surfaces in interconnect structures
TWI451530B (zh) 為多晶圓積體電路形成矽穿孔
US20100133645A1 (en) Method for stacking and interconnecting integrated circuits
TWI451544B (zh) 平坦化矽貫孔之方法
CN104347481B (zh) 金属镀层处理方法
US7510968B2 (en) Cap for semiconductor device package, and manufacturing method thereof
CN103887226A (zh) 晶圆堆叠结构及其制作方法与晶圆的制作方法
CN104064513A (zh) 半导体装置的制造方法及半导体装置
JP2010503216A (ja) 選択的に物質を堆積するために被加工物を表面改質する方法及び装置
US9418933B2 (en) Through-substrate via formation with improved topography control
JP4552770B2 (ja) 半導体基板への貫通配線の形成方法
CN110491829A (zh) 半导体装置的制造方法
Henry et al. Via first technology development based on high aspect ratio trenches filled with doped polysilicon
US20070138140A1 (en) Method for controlling polishing process
CN100477120C (zh) 抛光工艺的控制方法
KR20080047541A (ko) 반도체 장치 상에 캐핑 레이어를 형성하는 방법
CN102194683A (zh) 电极部的构造
EP3358612A1 (en) Method for selective etching using dry film photoresist
CN100385595C (zh) 穿透式电子显微镜试片的制备方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information
CB02 Change of applicant information

Address after: Tokyo

Applicant after: Kaixia Co.,Ltd.

Address before: Tokyo

Applicant before: TOSHIBA MEMORY Corp.

GR01 Patent grant
GR01 Patent grant