CN110473909B - Standard wafer and method for manufacturing the same - Google Patents
Standard wafer and method for manufacturing the same Download PDFInfo
- Publication number
- CN110473909B CN110473909B CN201910808692.5A CN201910808692A CN110473909B CN 110473909 B CN110473909 B CN 110473909B CN 201910808692 A CN201910808692 A CN 201910808692A CN 110473909 B CN110473909 B CN 110473909B
- Authority
- CN
- China
- Prior art keywords
- thin film
- type
- film layer
- different
- film layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000010409 thin film Substances 0.000 claims abstract description 109
- 239000010408 film Substances 0.000 claims abstract description 75
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims description 12
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 10
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 5
- 239000003989 dielectric material Substances 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 229910052763 palladium Inorganic materials 0.000 claims description 5
- 229910052697 platinum Inorganic materials 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 235000012431 wafers Nutrition 0.000 description 45
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 34
- 235000012239 silicon dioxide Nutrition 0.000 description 16
- 239000000377 silicon dioxide Substances 0.000 description 16
- 229910052581 Si3N4 Inorganic materials 0.000 description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 14
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000007774 longterm Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- -1 silicon nitride) Chemical class 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- G01B11/00—Measuring arrangements characterised by the use of optical techniques
- G01B11/02—Measuring arrangements characterised by the use of optical techniques for measuring length, width or thickness
- G01B11/06—Measuring arrangements characterised by the use of optical techniques for measuring length, width or thickness for measuring thickness ; e.g. of sheet material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Disclosed herein is a standard wafer and a method of manufacturing the same, the standard wafer including: a substrate; at least two types of thin film layers, wherein the materials contained in the different types of thin film layers are different; at least two types of thin film layers are formed on different preset areas of the plane of the substrate. According to the method and the device, the different types of film layers are arranged in the different areas of the plane where the standard wafer is located, when the standard wafer is used for calibration, the different types of film layers can be calibrated at one time, and the standard wafer of various types does not need to be replaced, so that the calibration steps are simplified, and the calibration efficiency is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a standard wafer and a manufacturing method thereof.
Background
As semiconductor manufacturing processes have evolved, process dimensions have decreased, and accordingly, the thickness of thin films in semiconductor devices has also decreased. In order to maintain uniformity of film thickness, higher demands are placed on the accuracy and stability of film thickness measurements. To ensure accuracy and stability of film thickness measurements, standard wafers (Wafer) are used, and periodic calibration of the metrology tool is required.
In the related art, a plurality of thin type standard wafers are generally included: for example silicon dioxide (SiO) 2 ) Thin film standard wafers, silicon nitride (SiN) thin film standard wafers, polysilicon thin film standard wafers, and the like; meanwhile, in consideration of precision, standard wafers of each film type correspond to films of various thicknesses: taking a silicon dioxide film as an example, the silicon dioxide films respectively correspond to silicon dioxide film standard wafers with thicknesses of T1, T2 and T3.
Fig. 1 is a schematic diagram of a standard wafer provided in the related art, and as shown in fig. 1, the standard wafer 100 is a silicon dioxide thin film standard wafer with a thickness T1, when the standard wafer 100 is used, the standard wafer 100 is usually fixed on a measuring machine, the measuring machine is calibrated by using a Laser (Laser) irradiation area 110, and then other types of standard wafers are replaced or other thickness standard wafers are calibrated again, so that the operation process is complicated. Meanwhile, since the laser irradiates the area 110 each time calibration is performed using the standard wafer 100, damage is caused to the surface of the area 110 during long-term use, thereby affecting the accuracy of calibration.
Disclosure of Invention
The application provides a standard wafer and a manufacturing method thereof, which can solve the problem that the standard wafer provided in the related art is complicated to operate in the calibration process.
In one aspect, the present application provides a standard wafer for thickness calibration of a metrology bench in a semiconductor manufacturing process, comprising:
a substrate;
at least two types of thin film layers, wherein the materials contained in different types of thin film layers are different;
the at least two types of thin film layers are formed on different preset areas of the plane of the substrate.
Optionally, each type of thin film layer includes at least two thicknesses, and thin film layers of different thicknesses are formed on the different preset regions.
Optionally, each type of thin film layer includes at least two thicknesses, and thin film layers of different thicknesses are formed on the different preset regions.
Optionally, at least one type of thin film layer exists in the at least two types of thin film layers, so that the same thickness is formed on different preset areas.
Alternatively, there are thin film layers of the same type and different thickness located in adjacent predetermined areas.
Optionally, there are different types of film layers located in adjacent preset areas.
Optionally, the thin film layer comprises at least one of nitride, oxide, polysilicon, high K dielectric material, silicon germanium, titanium, platinum, palladium.
In another aspect, the present application provides a method of manufacturing a standard wafer for thickness calibration of a metrology bench in a semiconductor manufacturing process, the method comprising:
step S1: providing a substrate;
step S2: depositing a thin film layer of a first type on the substrate;
step S3: removing the first type thin film layer in other areas through an etching process in a preset area corresponding to the first type thin film layer of the photomask;
step S4: depositing an i-th type film layer in the other areas, wherein i is more than or equal to 2 and less than or equal to n, n is more than or equal to 2, i and n are positive integers, n is a preset film layer type number, and the i-th type film layer is different from the first type film layer in material;
step S5: removing the thin film layers in other areas through an etching process in preset areas corresponding to the thin film layers deposited by the photomask, wherein the preset areas corresponding to each type of thin film layer in the n types of thin film layers are different;
step S6: let i=i+1, repeat step S4 and step S5 until i=n.
Optionally, each type of thin film layer includes at least two thicknesses, thin film layers with different thicknesses are formed on the different preset areas, and the method further includes:
and etching the thin film layers in the preset area in sequence, so that each type of thin film layer comprises at least two thicknesses.
Optionally, at least one type of thin film layer exists in the at least two types of thin film layers, so that the same thickness is formed on different preset areas.
Alternatively, there are thin film layers of the same type and different thickness located in adjacent predetermined areas.
Optionally, there are different types of film layers located in adjacent preset areas.
Optionally, the thin film layer comprises at least one of nitride, oxide, polysilicon, high K dielectric material, silicon germanium, titanium, platinum, palladium.
The technical scheme of the application at least comprises the following advantages:
by arranging different types of film layers in different areas of the plane of the standard wafer, when the standard wafer is used for calibration, the different types of film layers can be calibrated at one time without replacing multiple types of standard wafers, so that the calibration steps are simplified, and the calibration efficiency is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic view of a standard wafer provided in the related art;
FIG. 2 is a schematic illustration of a standard wafer provided in one exemplary embodiment of the present application;
FIG. 3 is a schematic illustration of a standard wafer provided in one exemplary embodiment of the present application;
fig. 4 is a flowchart of a method of manufacturing a standard wafer according to an exemplary embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made apparent and complete in conjunction with the accompanying drawings, in which embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
Example 1:
referring to fig. 2, a schematic diagram of a standard wafer provided in an exemplary embodiment of the present application is shown. As shown in fig. 2, the standard wafer 200 includes a substrate 210 and at least two types of thin film layers (two different types of thin film layers 221 and 222 are illustrated in fig. 2).
Among the at least two types of thin film layers, the different types of thin film layers include different materials, for example, the thin film layer 221 is a silicon nitride thin film, and the thin film layer 222 is a silicon dioxide thin film; at least two types of thin film layers are formed on different predetermined areas of the plane of the substrate 210, for example, the thin film layer 221 and the thin film layer 222 are formed on different predetermined areas of the plane of the substrate 210. The preset area is an area on the plane of the substrate 210, and when preparing the standard wafer, the preset area needs to be divided on the plane of the substrate 210 for depositing the thin film layer.
In summary, in this embodiment, different types of thin film layers are disposed in different areas of the plane of the standard wafer, so that when the standard wafer is used for calibration, the different types of thin film layers can be calibrated at one time without replacing multiple types of standard wafers, thereby simplifying the calibration steps and improving the calibration efficiency.
Example 2:
with reference to example 1, example 2 differs from example 1 in that: each type of film layer includes at least two thicknesses, with film layers of different thicknesses being formed on different predetermined areas. The thickness relationship between the different types of film layers is not limited.
For example, a standard wafer includes two types of thin film layers: the silicon nitride film comprises three thicknesses of T1, T2 and T3, and the silicon dioxide film comprises three thicknesses of T4, T5 and T6, so that the silicon nitride film with the thickness of T1, the silicon nitride film with the thickness of T2, the silicon nitride film with the thickness of T3, the silicon dioxide film with the thickness of T4, the silicon dioxide film with the thickness of T5 and the silicon dioxide film with the thickness of T6 are respectively formed in different preset areas.
In this embodiment, different types of thin film layers are disposed in different areas of the plane of the standard wafer, and each type of thin film layer includes at least two thicknesses, when the standard wafer is used for calibration, the thin film layers with different types and different thicknesses can be calibrated at one time, and the standard wafer with multiple types and multiple thicknesses does not need to be replaced, so that the calibration steps are further simplified, and the calibration efficiency is improved.
Example 3:
with reference to example 2, example 3 differs from example 2 in that: at least one type of thin film layer exists among the at least two types of thin film layers, and the same thickness is satisfied to be formed on different preset areas.
For example, a standard wafer includes two types of thin film layers: the silicon nitride film comprises three thicknesses of T1, T2 and T3, wherein the silicon nitride film with the thickness of T1 is positioned in a first preset area and a second preset area, the silicon nitride film with the thickness of T2 is positioned in a third preset area and a fourth preset area, and the silicon nitride film with the thickness of T3 is positioned in a fifth preset area and a sixth preset area; the silicon dioxide film comprises three thicknesses of T4, T5 and T6, the silicon dioxide film with the thickness of T4 is positioned in a seventh preset area and an eighth preset area, the silicon dioxide film with the thickness of T5 is positioned in a ninth preset area and a tenth preset area, and the silicon dioxide film with the thickness of T6 is positioned in an eleventh preset area and a twelfth preset area. It should be noted that this embodiment is only illustrative, and the thin film layers with the same thickness may be formed in different preset areas, or may be formed in one preset area, so long as it is satisfied that one type of thin film layer exists, and the same thickness is distributed in different preset areas.
In this embodiment, by distributing the thin film layers with the same thickness and the same type in different preset areas, when one of the thin film layers is damaged due to long-time use, the thin film layers with the same type and the same thickness in the other preset area can be used for calibration.
Example 4:
with reference to example 3, example 4 differs from example 3 in that: the film layers with the same type and different thicknesses are positioned in adjacent preset areas. For example, in the above embodiment, the silicon nitride layer with the thickness of T1 and the silicon nitride layer with the thickness of T2 may be located in adjacent preset regions.
Example 5:
with reference to example 3 and example 4, example 5 differs from example 3, example 4 in that: there are different types of film layers located in adjacent preset areas. For example, in the above embodiments, the silicon oxide layer and the silicon oxide layer may be located in adjacent preset regions.
Optionally, the thin film layer in the embodiments of the present application includes at least one of nitride (e.g., silicon nitride), oxide (e.g., silicon dioxide), polysilicon, high-K dielectric material (e.g., a material having a dielectric constant "K" greater than 10), silicon germanium, titanium, platinum, palladium.
An exemplary embodiment of the present application is described with reference to a standard wafer comprising three types of thin film layers, each type of thin film layer comprising two thicknesses. As shown in fig. 3, the standard wafer 300 provided in the present embodiment includes a substrate 310 and thin film layers including a first type of thin film layer 3111 of thickness T1, a first type of thin film layer 3112 of thickness T2, a second type of thin film layer 3121 of thickness T3, a second type of thin film layer 3122 of thickness T4, a third type of thin film layer 3131 of thickness T5, and a third type of thin film layer 3132 of thickness T6. Wherein, T1 thickness and T2 thickness are different, T3 thickness and T4 thickness are different, T5 thickness and T6 thickness are different, thickness relation between the film layers of different types is not limited.
As shown in fig. 3, the thin film layers with the same thickness are located in different preset areas; the film layers with the same type and different thicknesses are positioned in adjacent areas; different types of film layers are located in adjacent regions.
Example 6:
referring to fig. 4, a flowchart of a method of manufacturing a standard wafer according to an exemplary embodiment of the present application is shown. The standard wafer provided in the above embodiment can be manufactured by the method, which includes:
step S1, a substrate is provided.
Step S2, depositing a thin film layer of a first type on the substrate.
And S3, removing the first type thin film layer in other areas through an etching process in a preset area corresponding to the first type thin film layer of the photomask.
And S4, depositing an i-th type film layer in other areas, wherein i is more than or equal to 2 and less than or equal to n, n is more than or equal to 2, i and n are positive integers, n is a preset film layer type number, and the i-th type film layer is different from the first type film layer in material.
And S5, removing the thin film layers in other areas through an etching process in preset areas corresponding to the thin film layers deposited by the photomask, wherein the preset areas corresponding to each type of thin film layer in the n types of thin film layers are different.
Step S6, let i=i+1, repeat step S4 and step S5 until i=n.
Taking n=3 as an example, example 6 will be described:
after step 403, a second type of thin film layer is deposited in the other areas; removing the second type thin film layer in other areas through an etching process in a preset area corresponding to the first type thin film layer and the second type thin film layer of the photomask; depositing a third type of thin film layer in other areas; and removing the third type thin film layer in other areas through an etching process in the preset areas corresponding to the first type thin film layer, the second type thin film layer and the third type thin film layer of the photomask.
In the above embodiment, when each type of thin film layer corresponds to a different thickness, the method further includes: and etching the thin film layers in the preset area in sequence, so that each type of thin film layer comprises at least two thicknesses.
The film layer can be deposited to the maximum thickness, and the preset areas corresponding to other thicknesses are etched through the preset areas corresponding to the film layer with the larger thickness of the step-by-step photomask, so that the film layer with the lower thickness is obtained.
For example, a standard wafer includes two types of thin film layers thereon: a first type of thin film layer corresponding to the two thicknesses T1 and T2 and (T1 > T2), and a second type of thin film layer corresponding to the two thicknesses T3 and T4 (T3 > T4), the first type of thin film layer having a thickness of T1 and the second type of thin film layer having a thickness of T3 being deposited by the above-described method; carrying out photomask on a preset area corresponding to the first type thin film layer and the second type thin film layer with the thickness of T1, and etching the first type thin film layer with the thickness of T1 of other areas to obtain the first type thin film layer with the thickness of T2; and carrying out photomask on a preset area corresponding to the first type film layer with the thickness of T1, the second type film layer with the thickness of T2 and the second type film layer with the thickness of T3, and etching the second type film layer with the thickness of T3 of other areas to obtain the second type film layer with the thickness of T4.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While nevertheless, obvious variations or modifications may be made to the embodiments described herein without departing from the scope of the invention.
Claims (4)
1. A master wafer for thickness calibration of a metrology bench in a semiconductor manufacturing process, comprising:
a substrate;
at least two types of film layers, wherein the different types of film layers contain different materials, each type of film layer comprises at least two thicknesses, the film layers with different thicknesses are formed on the different preset areas, at least one type of film layer exists in the at least two types of film layers, the same thickness is formed on the different preset areas, the film layers with the same type of thickness are located in the adjacent preset areas, and the film layers with different types are located in the adjacent preset areas;
the at least two types of thin film layers are formed on different preset areas of the plane of the substrate.
2. The standard wafer of claim 1, wherein the thin film layer comprises at least one of nitride, oxide, polysilicon, high K dielectric material, silicon germanium, titanium, platinum, palladium.
3. A method of manufacturing a standard wafer for thickness calibration of a metrology bench in a semiconductor manufacturing process, the method comprising:
step S1: providing a substrate;
step S2: depositing a thin film layer of a first type on the substrate;
step S3: removing the first type thin film layer in other areas through an etching process in a preset area corresponding to the first type thin film layer of the photomask;
step S4: depositing an i-th type film layer in other areas, wherein i is more than or equal to 2 and less than or equal to n, n is more than or equal to 2, i and n are positive integers, n is a preset film layer type number, and the i-th type film layer is different from the first type film layer in material;
step S5: removing the thin film layers in other areas through an etching process in preset areas corresponding to the thin film layers deposited by the photomask, wherein the preset areas corresponding to each type of thin film layer in the n types of thin film layers are different;
step S6: let i=i+1, repeat step S4 and step S5 until i=n;
wherein each type of film layer comprises at least two thicknesses, film layers with different thicknesses are formed on different preset areas, and the film layers in the preset areas are sequentially etched to ensure that each type of film layer comprises at least two thicknesses;
at least one type of film layer exists in the at least two types of film layers, the film layers with the same thickness are formed on different preset areas, the film layers with the same type and different thicknesses exist in adjacent preset areas, and the film layers with different types exist in adjacent preset areas.
4. The method of claim 3, wherein the thin film layer comprises at least one of nitride, oxide, polysilicon, high K dielectric material, silicon germanium, titanium, platinum, palladium.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910808692.5A CN110473909B (en) | 2019-08-29 | 2019-08-29 | Standard wafer and method for manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910808692.5A CN110473909B (en) | 2019-08-29 | 2019-08-29 | Standard wafer and method for manufacturing the same |
Publications (2)
Publication Number | Publication Date |
---|---|
CN110473909A CN110473909A (en) | 2019-11-19 |
CN110473909B true CN110473909B (en) | 2023-06-09 |
Family
ID=68514045
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201910808692.5A Active CN110473909B (en) | 2019-08-29 | 2019-08-29 | Standard wafer and method for manufacturing the same |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN110473909B (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111024017B (en) * | 2019-12-04 | 2021-10-15 | 中国电子科技集团公司第十三研究所 | Film thickness sample and preparation method of film thickness sample |
CN111024016B (en) * | 2019-12-04 | 2021-10-15 | 中国电子科技集团公司第十三研究所 | Film thickness sample and preparation method of film thickness sample |
CN112466744A (en) * | 2020-11-17 | 2021-03-09 | 深圳宝铭微电子有限公司 | Novel crystal element and preparation method thereof |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1157478A (en) * | 1996-02-17 | 1997-08-20 | 台湾茂矽电子股份有限公司 | Method for preparation of standard chip |
CN104716125A (en) * | 2013-12-17 | 2015-06-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor film thickness measurement calibration standard sheet and manufacturing method thereof |
-
2019
- 2019-08-29 CN CN201910808692.5A patent/CN110473909B/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1157478A (en) * | 1996-02-17 | 1997-08-20 | 台湾茂矽电子股份有限公司 | Method for preparation of standard chip |
CN104716125A (en) * | 2013-12-17 | 2015-06-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor film thickness measurement calibration standard sheet and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
CN110473909A (en) | 2019-11-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN110473909B (en) | Standard wafer and method for manufacturing the same | |
CN111276416B (en) | Method for detecting alignment of semiconductor structure alignment and method for manufacturing 3D memory device | |
JP2008134103A (en) | Standard member for calibration, its manufacturing method and scanning electron microscope using standard member for calibration | |
KR20020038458A (en) | Method and system for manufacturing semiconductor device, and semiconductor device | |
JP2008300842A (en) | Measuring apparatus for contact resistivity between metal and semiconductor | |
US8735181B2 (en) | Manufacturing system for semiconductor device capable of controlling variation in electrical property of element in wafer surface and method for manufacturing the semiconductor device | |
US7861421B2 (en) | Method for measuring rotation angle of bonded wafer | |
CN112885772B (en) | Method for manufacturing semiconductor structure | |
US8674355B2 (en) | Integrated circuit test units with integrated physical and electrical test regions | |
CN107342254B (en) | The calibration method of crystal edge etching machine bench | |
US20090283860A1 (en) | High precision semiconductor chip and a method to construct the semiconductor chip | |
CN102005436B (en) | Measurement calibrating wafer | |
US20220359317A1 (en) | Stress measuring structure and stress measuring method | |
CN113485073A (en) | Method for compensating critical dimension | |
CN208142177U (en) | Active array and random access memory | |
CN100481317C (en) | Sample structure of scanning electron microscope made by IC and manufacturing method thereof | |
CN111103767B (en) | Semiconductor device, manufacturing method thereof and electronic equipment | |
KR100499412B1 (en) | Method for measuring CD using capacitance | |
CN112582422B (en) | Preparation method of three-dimensional memory and three-dimensional memory | |
US20160126194A1 (en) | Measurement mark structure and manufacturing method thereof | |
CN115966482A (en) | Wafer measuring method | |
US9711624B1 (en) | Methods for direct measurement of pitch-walking in lithographic multiple patterning | |
CN114038739A (en) | Etching method of polycrystalline silicon | |
TWI226095B (en) | Calibration wafer and manufacturing method thereof | |
KR100548723B1 (en) | Semiconductor Wafer having Patterns for Monitoring Thickness of Layer and Method for Monitoring Thickness of Layer using such Patterns |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |