CN110473844B - Packaging structure - Google Patents

Packaging structure Download PDF

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Publication number
CN110473844B
CN110473844B CN201910681479.2A CN201910681479A CN110473844B CN 110473844 B CN110473844 B CN 110473844B CN 201910681479 A CN201910681479 A CN 201910681479A CN 110473844 B CN110473844 B CN 110473844B
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Prior art keywords
shielding layer
layer
semiconductor chip
substrate
functional surface
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CN110473844A (en
Inventor
缪小勇
王洪辉
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Nantong Fujitsu Microelectronics Co Ltd
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Nantong Fujitsu Microelectronics Co Ltd
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Priority to CN201910681479.2A priority Critical patent/CN110473844B/en
Publication of CN110473844A publication Critical patent/CN110473844A/en
Priority to US17/629,549 priority patent/US20220270982A1/en
Priority to PCT/CN2020/102758 priority patent/WO2021017896A1/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492Bases or plates or solder therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A packaging structure comprises a plurality of semiconductor chips which are inversely arranged on the front surface of a substrate; the first shielding layer coats the non-functional surface and the side wall surface of the semiconductor chip and the side surface of the bottom filling layer; a second shielding layer on the first shielding layer; be located the outside contact structure of the back of base plate with output port connection, the second shielding layer can cover the place that thickness is inhomogeneous and edge cover is not good in the first shielding layer to make the whole shielding layer that first shielding layer and second shielding layer both constitute complete, improved shielded effect.

Description

Packaging structure
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a packaging structure with electromagnetic shielding.
Background
The rapid development of new generation electronic products pushes the integrated circuit package to develop towards high density, high frequency, miniaturization and high integration, and the high frequency chip often generates strong electromagnetic waves to cause undesirable interference or noise inside and outside the package and the chip; in addition, the density of electronic components is increasing, and the distance of transmission lines is becoming closer, so that the problem of electromagnetic interference from inside and outside the integrated circuit package is becoming more serious, and the quality, the service life and the like of the integrated circuit are also being reduced.
In electronic devices and products, Electromagnetic Interference (Electromagnetic Interference) energy is transmitted by conductive coupling and radiative coupling. In order to meet the requirement of electromagnetic compatibility, a filtering technology is required to be adopted for conductive coupling, namely an EMI filtering device is adopted for inhibiting; the radiation coupling is suppressed by shielding. The importance of the method is more prominent under the condition that the electromagnetic environment of equipment and a system is increasingly deteriorated due to the factors that the current electromagnetic spectrum is increasingly dense, the electromagnetic power density in a unit volume is sharply increased, a large number of high-level devices or low-level devices are mixed for use and the like.
An existing electromagnetic shielding solution is mainly to provide a magnetic field shielding layer on a semiconductor package structure for shielding electromagnetic interference between chips, but the effect of the existing electromagnetic shielding still needs to be improved.
Disclosure of Invention
The technical problem to be solved by the invention is how to improve the electromagnetic shielding effect of the existing packaging structure.
The present invention provides a package structure, comprising:
the circuit structure comprises a substrate, a plurality of circuit structures and a plurality of output ports, wherein the substrate is internally provided with the plurality of circuit structures;
the semiconductor chip comprises a functional surface and a non-functional surface opposite to the functional surface, wherein the functional surface is provided with a plurality of bonding pads, the bonding pads are provided with metal bumps, and the metal bumps on each semiconductor chip are connected with corresponding input ports on the front surface of the substrate;
the underfill layer is positioned between the functional surface of the semiconductor chip and the front surface of the substrate;
the first shielding layer coats the non-functional surface and the side wall surface of the semiconductor chip and the side surface of the bottom filling layer;
a second shielding layer on the first shielding layer;
and an external contact structure located on the back surface of the substrate and connected to the output port.
Optionally, the first shielding layer is formed by a sputtering process, the first shielding layer at least covers a part of the substrate surface between the semiconductor chips, and the second shielding layer is formed by a selective plating process, a dispensing process, or a screen printing process.
Optionally, the first shielding layer is made of copper, tungsten or aluminum, and the second shielding layer is made of copper, solder or conductive silver paste.
Optionally, the first shielding layer is a magnetic field shielding layer, and the second shielding layer is an electric field shielding layer; or the first shielding layer is an electric field shielding layer, and the second shielding layer is a magnetic field shielding layer.
Optionally, the electric field shielding layer is made of copper, tungsten, or aluminum; the magnetic field shielding layer is made of CoFeB alloy, CoFeTa, NiFe, Co, CoFe, CoPt or Ni, Co and Fe alloy.
Optionally, the functional surface of the semiconductor chip is further provided with a bottom shielding layer, the bottom shielding layer covers the whole functional surface of the semiconductor chip, the peripheral edge of the bottom shielding layer is flush with the peripheral side wall of the semiconductor chip, the plurality of bonding pads penetrate through the bottom shielding layer, and the bonding pads are isolated from the bottom shielding layer through an isolation layer; the first shielding layer is connected with the peripheral edge of the bottom shielding layer.
Optionally, the external contact structure is a solder ball, or the external contact structure includes a metal pillar and a solder ball located on the metal pillar.
Optionally, the method further includes: a conductive contact structure in the substrate, the conductive contact structure being electrically connected to the first shielding layer.
The invention also provides an independent packaging structure formed by dividing the packaging structure, which comprises:
the circuit structure is arranged in the substrate, the front surface of the substrate is provided with a plurality of input ports, the back surface of the substrate is provided with a plurality of output ports, and the input ports and the output ports are respectively connected with the circuit structure;
the semiconductor chip is inversely arranged on the front surface of the substrate and comprises a functional surface and a non-functional surface opposite to the functional surface, wherein the functional surface is provided with a plurality of bonding pads, the bonding pads are provided with metal bumps, and the metal bumps on each semiconductor chip are connected with corresponding input ports on the front surface of the substrate;
the underfill layer is positioned between the functional surface of the semiconductor chip and the front surface of the substrate;
the first shielding layer coats the non-functional surface and the side wall surface of the semiconductor chip and the side surface of the bottom filling layer;
a second shielding layer on the first shielding layer
And an external contact structure located on the back surface of the substrate and connected to the output port.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the packaging structure, a plurality of semiconductor chips are inversely arranged on the front surface of a substrate; the first shielding layer coats the non-functional surface and the side wall surface of the semiconductor chip and the side surface of the bottom filling layer; a second shielding layer on the first shielding layer; be located the outside contact structure of the back of base plate with output port connection, the second shielding layer can cover the place that thickness is inhomogeneous and edge cover is not good in the first shielding layer to make the whole shielding layer that first shielding layer and second shielding layer both constitute complete, improved shielded effect.
Furthermore, the second shielding layer is only positioned on the surface of the first shielding layer covering the non-functional surface and the side wall surface of the semiconductor chip, the surface of the second shielding layer is an ellipsoid, and the second shielding layer is formed through a selective electroplating process, a dispensing process or a screen printing process, so that the formed second shielding layer can better cover the first shielding layer, the place with poor coverage in the second shielding layer is prevented, the integrity of the whole shielding layer formed by the first shielding layer and the second shielding layer is further ensured, and the semiconductor chip is removed without extra masks and etching processes.
Further, the first shielding layer is a magnetic field shielding layer, and the formed second shielding layer is an electric field shielding layer; or first shielding layer is electric field shielding layer, then the second shielding layer that forms is magnetic field shielding layer, through first shielding layer and the second shielding layer that forms aforementioned structure for first shielding layer and second shielding layer shield to electric field or magnetic field respectively, thereby improved the shielding effect of shielding layer, and the second shielding layer can cover the place that thickness is inhomogeneous and edge cover is not good in the first shielding layer to make the whole shielding layer that first shielding layer and second shielding layer both constitute complete, further improved the effect of shielding.
Furthermore, after the external contact structure is formed, the pre-sealing panel is cut to form a plurality of separated packaging structures, so that batch manufacturing of the packaging structures with the first shielding layer and the second shielding layer is realized, and production efficiency is improved.
Furthermore, a bottom shielding layer is further arranged on the functional surface of the semiconductor chip and covers the whole functional surface of the semiconductor chip, the peripheral edge of the bottom shielding layer is flush with the peripheral side wall of the semiconductor chip, a plurality of bonding pads penetrate through the bottom shielding layer, and the bonding pads are isolated from the bottom shielding layer through an isolation layer; when the first shielding layer is formed, the first shielding layer is connected with the peripheral edge of the bottom shielding layer. That is, in this embodiment, after the first shielding layer is formed, the second shielding layer is formed on the first shielding layer, so that the second shielding layer can cover the place with uneven thickness and poor edge coverage in the first shielding layer, so that the whole shielding layer formed by the first shielding layer and the second shielding layer is complete, the shielding effect is improved, and because the bottom shielding layer is further provided on the functional surface of the semiconductor chip, when the first shielding layer is formed, the first shielding layer is connected with the peripheral edge of the bottom shielding layer, so that the semiconductor chip in the package structure is completely or omnidirectionally covered by the bottom shielding layer and the first shielding layer, and therefore the electric field and the magnetic field cannot enter the package structure through the bottom of the package structure to bring electromagnetic interference to the semiconductor chip, thereby realizing the omnidirectional electromagnetic shielding of the semiconductor chip, the electromagnetic shielding effect is further improved.
Drawings
Fig. 1-12 are schematic structural views illustrating a process of forming a package structure according to a first embodiment of the invention;
fig. 13-18 are schematic structural views illustrating a process of forming a package structure according to a second embodiment of the invention.
Detailed Description
As mentioned in the background, the effectiveness of the conventional electromagnetic shielding is still to be improved.
Research finds that the existing magnetic field shielding layer is generally formed through a sputtering process, and because the thickness of the semiconductor packaging structure is generally thick and the semiconductor packaging structure is generally rectangular, the semiconductor packaging structure is provided with a plurality of top angles and has steep side walls, when the magnetic field shielding layer covering the semiconductor packaging structure is formed through the sputtering process, the thickness of the formed magnetic field shielding layer is easily uneven, and the edge of the semiconductor packaging structure can have an uncovered condition, so that the shielding effect of the magnetic field shielding layer is difficult to guarantee.
To this end, the present invention provides a package structure and a method of forming the same, the method of forming an underfill layer between a functional side of a plurality of semiconductor chips and a front surface of a substrate by flip-chip mounting the semiconductor chips on the front surface of the substrate; forming a first shielding layer for coating the surface of the non-functional surface and the side wall of the semiconductor chip and the surface of the side surface of the bottom filling layer; forming a second shielding layer on the first shielding layer; forming a plastic packaging layer on the second shielding layer and the substrate between the semiconductor chips; and forming an external contact structure connected with the output port on the back surface of the substrate. Through forming the second shielding layer on first shielding layer, the second shielding layer can cover the place that thickness is inhomogeneous and edge cover is not good in the first shielding layer to make the whole shielding layer that first shielding layer and second shielding layer both constitute complete, improved shielded effect.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In describing the embodiments of the present invention in detail, the drawings are not to be considered as being enlarged partially in accordance with the general scale, and the drawings are only examples, which should not be construed as limiting the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
Fig. 1-12 are schematic structural views illustrating a process of forming a package structure according to a first embodiment of the invention.
Referring to fig. 1-4, fig. 2 is a schematic cross-sectional view along a cutting line AB in fig. 1, a plurality of semiconductor chips 101 are provided, each semiconductor chip 101 includes a functional surface and a non-functional surface opposite to the functional surface, the functional surface has a plurality of bonding pads 102, and metal bumps 130 are formed on the bonding pads 102.
An integrated circuit (not shown) is formed in the functional surface of the semiconductor chip 101, the functional surface of the semiconductor chip 101 has a plurality of pads 102, the pads 102 are electrically connected to the integrated circuit in the semiconductor chip 101, and the pads 102 serve as ports for electrically connecting the integrated circuit in the semiconductor chip 101 to the outside.
The functional surface of the semiconductor chip 101 is a surface for forming an integrated circuit, the non-functional surface is a surface opposite to the functional surface, and the peripheral surface between the functional surface and the non-functional surface is a sidewall of the semiconductor chip 101.
The semiconductor chip 101 is formed by a semiconductor integrated manufacturing process, specifically referring to fig. 1 and 2, a wafer 100 is provided, and the wafer 100 includes a plurality of chip regions arranged in rows and columns and scribe line regions located between the chip regions; correspondingly forming a plurality of semiconductor chips 101 in a plurality of chip areas of the wafer 100; forming a plurality of bonding pads 102 on a functional surface of the semiconductor chip 101; referring to fig. 3, a metal bump 130 is formed on the surface of the pad 102, the material of the metal bump 130 is one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver, the forming process of the metal bump 130 may be electroplating, sputtering, or a physical vapor deposition process, the metal bump 130 is formed to raise the pad 102 for subsequent wiring, and the metal bump 130 also has the functions of protecting the pad and conducting heat; referring to fig. 4, the wafer 100 is diced along dicing streets to form a plurality of discrete semiconductor chips 101.
In one embodiment, the material of the wafer 100 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide.
In an embodiment, the integrated circuit in the semiconductor chip 101 may include several semiconductor devices (such as transistors, memories, diodes and/or transistors, etc.) and an interconnection structure (including metal lines and metal plugs) for connecting the semiconductor devices.
In this embodiment, the semiconductor chip 101 is a semiconductor chip that needs to be electromagnetically shielded.
Referring to fig. 5, a substrate 301 is provided, the substrate 301 has a plurality of circuit structures therein, the front surface of the substrate 301 has a plurality of input ports, the back surface of the substrate has a plurality of output ports, and the input ports and the output ports are respectively connected with the corresponding circuit structures; the flip-chip mounting of the plurality of semiconductor chips 101 is performed on the front surface of the substrate such that the metal bumps 130 on each of the semiconductor chips 101 are connected to corresponding input ports on the front surface of the substrate.
The substrate 301 may be a PCB substrate or a circuit carrier. The substrate 301 has a plurality of circuit structures therein, and the plurality of circuit structures may be in row and column portions in the substrate, and each circuit structure is connected to a corresponding input port and output port. In this embodiment, an integrated package of the substrate 301 and the semiconductor chip having the first shielding layer and the second shielding layer is realized subsequently.
When the semiconductor chips 101 are flip-chip mounted on the front surface of the substrate, the metal bumps 130 on each semiconductor chip 101 are connected to the corresponding input ports on the substrate 301 through a solder layer.
The solder layer is made of one or more of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-bismuth-indium, tin-gold, tin-copper, tin-zinc-indium or tin-silver-antimony.
In one embodiment, the method further comprises: the substrate 301 further has a conductive contact structure (not shown) therein, and the conductive contact structure is electrically connected to a first shielding layer formed later, so that the shielding layer can discharge electricity or block external electrostatic interference through a portion of the redistribution layer 123.
Referring to fig. 6, an underfill layer 132 is formed between the functional surface of the semiconductor chip 101 and the front surface of the substrate 301.
The underfill layer 132 covers the sides of the metal bump 130.
The forming process of the underfill layer 132 is an injection molding or transfer molding process, the material of the underfill layer 132 is resin, and the resin may be epoxy resin, polyimide resin, benzocyclobutene resin or polybenzoxazole resin.
Referring to fig. 7, a first shielding layer 103 is formed to cover the non-functional surface and sidewall surfaces of the semiconductor chip 101 and the side surface of the underfill layer 132.
In this embodiment, the first shielding layer 103 may cover not only the non-functional surface and the sidewall surface (and the side surface of the underfill layer 132) of the semiconductor chips 101, but also the substrate 301 surface between the semiconductor chips 101 with the first shielding layer 103. In other embodiments, the first shielding layer 103 may be formed to cover only the non-functional surface and the sidewall surface (and the side surface of the underfill layer 132) of the semiconductor chip 101.
In an embodiment, the first shielding layer 103 is formed by a sputtering process, the material of the first shielding layer 103 may be copper, tungsten or aluminum, and since the semiconductor chip 101 has four vertical corners (which are right angles) and the semiconductor chip 101 has a thicker semiconductor chip 101 sidewall (which is a 90-degree included angle with the surface of the substrate 301), the first shielding layer 103 formed by the sputtering process has the problems of non-uniform thickness and poor edge coverage.
In this embodiment, the first shielding layer 103 is formed as a shielding layer for an electric field and a magnetic field, the first shielding layer 103 is used for shielding the electric field and the magnetic field, the second shielding layer formed subsequently is also formed as a shielding layer for the electric field and the magnetic field, and the second shielding layer is used for shielding the electric field and the magnetic field.
Research shows that the existing shielding layer needs to shield both an electric field and a magnetic field, while the existing single-layer shielding layer made of a specific material or multiple layers of shielding layers made of the same material or similar materials only have a good shielding effect on the electric field, and the shielding effect on the magnetic field is relatively weak, so that the shielding effect of the shielding layer is influenced. Thus, in other embodiments, the first shielding layer 103 is a magnetic field shielding layer for shielding a magnetic field, and the second shielding layer formed subsequently is an electric field shielding layer for shielding an electric field; or the first shielding layer is an electric field shielding layer, the first shielding layer is used for shielding an electric field, the second shielding layer is a magnetic field shielding layer, the second shielding layer is used for shielding a magnetic field, and the first shielding layer and the second shielding layer are respectively shielded against the electric field or the magnetic field by forming the first shielding layer and the second shielding layer of the structure, so that the shielding effect of the shielding layer is improved. When the first shielding layer 103 is an electric field shielding layer, the material of the first shielding layer 103 (electric field shielding layer) is copper, tungsten, or aluminum; when the first shielding layer 103 is a magnetic field shielding layer, the material of the first shielding layer 103 (magnetic field shielding layer) is CoFeB alloy, CoFeTa, NiFe, Co, CoFe, CoPt, or an alloy of Ni, Co, and Fe. The first shielding layer 103 may be formed by sputtering, physical vapor deposition, atomic layer deposition, or chemical vapor deposition, or other suitable processes.
Referring to fig. 8, a second shield layer 104 is formed on the first shield layer 103.
Through forming second shielding layer 104 on first shielding layer 103, second shielding layer 104 can cover the place that thickness is inhomogeneous and the edge coverage is not good in first shielding layer 103 to make the whole shielding layer that first shielding layer 103 and second shielding layer 104 both constitute complete, improved the effect of shielding.
In this embodiment, the second shielding layer 104 is only located the cladding the first shielding layer 103 on the surface of the non-functional face and the sidewall surface of the semiconductor chip, just the surface of the second shielding layer 104 is ellipsoid-shaped, the second shielding layer 104 is formed by selective plating process, dispensing process or screen printing process, so that the second shielding layer 104 formed can better cover the first shielding layer, prevent the place with poor coverage in the second shielding layer 104, further ensure the integrity of the whole shielding layer composed of the first shielding layer 103 and the second shielding layer 104, and subsequently remove the semiconductor chip without extra mask and etching process.
The material of the second shielding layer 104 is copper, solder or conductive silver paste. In an embodiment, the second shielding layer 104 is formed by: forming a mask layer (not shown) on the substrate 301, wherein the mask layer has an opening exposing the non-functional surface of the semiconductor chip 101 and the first shielding layer 103 on the sidewall surface; using the first shielding layer 103 as a conductive layer during electroplating, and electroplating to form a second shielding layer 104 in the opening, or directly brushing solder into the opening to form the second shielding layer 104; and removing the mask layer.
In another embodiment, the material of the second shielding layer 104 is solder or conductive silver paste, and the second shielding layer 104 can be formed by a dispensing process or a screen printing process. Specifically, when the dispensing process is performed, solder or conductive silver paste is dispensed on the sidewall of the semiconductor chip 101 and the surface of the first shielding layer 103 on the nonfunctional surface. When screen printing is carried out, firstly, part of the first shielding layer 103 on the substrate 301 around the semiconductor chip 101 is removed, so that the rest of the first shielding layer 103 covers the non-functional surface and the side wall surface of the semiconductor chip and the side surface of the underfill layer, and the rest of the first shielding layer 103 also extends to cover part of the substrate 301 around the semiconductor chip 101; then, a screen plate with meshes is arranged on the substrate 301, and each semiconductor chip 101 is correspondingly positioned in one mesh in the screen plate; brushing solder into the mesh, wherein the solder covers the side wall of the semiconductor chip 101 and the surface of the first shielding layer 103 on the non-functional surface; removing the web; the solder is reflowed to form a second shield layer 104 on the first shield layer 103.
In one embodiment, the solder is one or more of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-bismuth-indium, tin-gold, tin-copper, tin-zinc-indium, or tin-silver-antimony.
In other embodiments, the first shielding layer 103 is a magnetic field shielding layer, and the formed second shielding layer 104 is an electric field shielding layer; or the first shielding layer 103 is an electric field shielding layer, the formed second shielding layer 104 is a magnetic field shielding layer, and the first shielding layer and the second shielding layer of the aforementioned structure are formed to shield the electric field or the magnetic field respectively, so that the shielding effect of the shielding layer is improved. When the second shielding layer 104 is an electric field shielding layer, the material of the second shielding layer 104 (electric field shielding layer) is copper, tungsten, or aluminum; when the second shielding layer 104 is a magnetic field shielding layer, the material of the second shielding layer 104 (magnetic field shielding layer) is CoFeB alloy, CoFeTa, NiFe, Co, CoFe, CoPt, or an alloy of Ni, Co, and Fe. The second shielding layer 104 may be formed by sputtering, physical vapor deposition, atomic layer deposition, or chemical vapor deposition, or other suitable processes.
In an embodiment, after the second shielding layer 104 is formed, the first shielding layer on the substrate between the adjacent semiconductor chips 101 may be removed through an etching process.
Referring to fig. 9, the first shielding material layer 103 on the substrate 301 at both sides of the semiconductor chip 101 is removed.
The first shielding material layer 103 on the substrate 301 at both sides of the semiconductor chip 101 may be removed using a dry etching process, such as a plasma etching process.
Referring to fig. 10, a molding layer 105 is formed on the second shielding layer 104 and on the substrate 301 between the semiconductor chips 101.
The molding compound layer 105 is used to seal and fix the semiconductor chip 101, so as to form a pre-packaged panel in the following.
The plastic sealing layer 105 may be made of one or more of epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, or polyvinyl alcohol.
The molding layer 105 may be formed by injection molding (injection molding) or transfer molding (transfer molding) or other suitable processes.
Referring to fig. 11, an external contact structure 124 connected to an output port is formed on the rear surface of the substrate 301.
The external contact structures 124 are solder balls in this embodiment, and in other embodiments, the external contact structures include metal posts and solder balls on the metal posts.
Referring to fig. 11 and 12, after the external contact structure 124 is formed, the pre-cover board is cut to form a plurality of separated package structures.
Referring to fig. 12, each package structure includes a substrate 301, the substrate 301 has a circuit structure therein, a front surface of the substrate has a plurality of input ports, a back surface of the substrate has a plurality of output ports, and the input ports and the output ports are respectively connected to the circuit structure;
the semiconductor chip 101 is flip-chip mounted on the front surface of the substrate 301, the semiconductor chip 101 includes a functional surface and a non-functional surface opposite to the functional surface, the functional surface has a plurality of pads 102 thereon, the pads 102 have metal bumps 130 thereon, and the metal bumps 130 on each semiconductor chip 101 are connected to corresponding input ports on the front surface of the substrate;
an underfill layer 132 between the functional surface of the semiconductor chip 101 and the front surface of the substrate 301;
a first shielding layer 103 covering the non-functional surface and sidewall surface of the semiconductor chip 101 and the side surface of the underfill layer 132;
a second shielding layer 104 on the first shielding layer 103
An external contact structure 124 on the back side of the substrate 301 connected to an output port.
The external contact structure 124 is a solder ball, or the external contact structure includes a metal pillar and a solder ball on the metal pillar.
The invention realizes the batch production of the packaging structure with the first shielding layer 103 and the second shielding layer 104 through the semiconductor integrated manufacturing process, and improves the production efficiency.
Fig. 13-18 are schematic structural views illustrating a process of forming a package structure according to a second embodiment of the invention. The second embodiment differs from the first embodiment in that: the semiconductor chip comprises a semiconductor chip, a plurality of bonding pads and a bottom shielding layer, wherein the functional surface of the semiconductor chip is also provided with the bottom shielding layer, the bottom shielding layer covers the whole functional surface of the semiconductor chip, the peripheral edge of the bottom shielding layer is flush with the peripheral side wall of the semiconductor chip, the bonding pads penetrate through the bottom shielding layer, and the bonding pads are isolated from the bottom shielding layer through an isolation layer; when the first shielding layer is formed, the first shielding layer is connected with the peripheral edge of the bottom shielding layer. That is, in this embodiment, after the first shielding layer is formed, the second shielding layer is formed on the first shielding layer, so that the second shielding layer can cover the place with uneven thickness and poor edge coverage in the first shielding layer, so that the whole shielding layer formed by the first shielding layer and the second shielding layer is complete, the shielding effect is improved, and because the bottom shielding layer is further provided on the functional surface of the semiconductor chip, when the first shielding layer is formed, the first shielding layer is connected with the peripheral edge of the bottom shielding layer, so that the semiconductor chip in the package structure is completely or omnidirectionally covered by the bottom shielding layer and the first shielding layer, and therefore the electric field and the magnetic field cannot enter the package structure through the bottom of the package structure to bring electromagnetic interference to the semiconductor chip, thereby realizing the omnidirectional electromagnetic shielding of the semiconductor chip, the electromagnetic shielding effect is further improved.
The forming process of the semiconductor chip with the bottom shielding layer comprises the following steps: referring to fig. 13, a wafer 100 is provided, a plurality of semiconductor chips 101 are formed on the wafer 100, the semiconductor chips 101 include a top dielectric layer 108 and a top interconnection structure 109 located in the top dielectric layer 108, the semiconductor chips further include a plurality of semiconductor devices (such as transistors, etc.) formed on a surface of the wafer (or semiconductor substrate), a plurality of interlayer dielectric layers located between the top dielectric layer 108 and the surface of the wafer 100, each interlayer dielectric layer has a corresponding interconnection structure therein, the interconnection structures in the interlayer dielectric layers can be interconnected with each other from top to bottom or electrically connected to the semiconductor devices, and the top interconnection structure 109 in the top dielectric layer 108 can be electrically connected to the interconnection structure in the interlayer dielectric layer of the adjacent layer; an isolation layer is formed on the top dielectric layer 108.
In this embodiment, the isolation layer is a double-layer stacked structure, and includes a first isolation layer 110 and a second isolation layer 111 located on the first isolation layer 110, where the materials of the first isolation layer 110 and the second isolation layer 111 are different, and the materials of the first isolation layer 110 and the second isolation layer 111 may be one of silicon oxide, silicon nitride, and silicon oxynitride, so as to facilitate accurate control of the depth of the formed second opening, prevent over-etching of the isolation layer when the second opening is formed, so that the second opening exposes a part of the surface of the top-layer interconnect structure 109 in the top-layer dielectric layer 108, and cause a short circuit between the top-layer interconnect structures 109 when a bottom shielding layer is formed in the second opening. In other embodiments, the isolation layer may be a single layer structure.
Referring to fig. 14, the isolation layer is etched, a plurality of first openings 112 and a second opening 113 surrounding the plurality of first openings 112 are formed in the isolation layer, and the remaining isolation layer 111 is only located between the first openings 112 and the second opening 113, separating the first openings 112 and the second opening 113.
The first openings 112 are discrete, the first openings 112 penetrate the isolation layer, each first opening 112 may correspondingly expose a portion of the surface of the top-level interconnect structure 109, and a pad is formed by filling metal into the first opening 112.
The second opening 113 surrounds the first opening 112, the second opening 113 and the first opening 112 are separated by the isolation layer 111, and the depth of the second opening 113 is smaller than the thickness of the isolation layer, the first opening 112 and the area outside the isolation layer 111 surrounding the first opening 112 all correspond to the area of the second opening 113, the second opening 113 is connected, when a bottom shielding layer is formed in the second opening 113, the bottom shielding layer can cover all areas of the functional surface of the semiconductor chip 101 except for the pad (formed in the first opening 112) and the isolation layer surrounding the pad, when the first shielding layer is formed on the surface of the non-functional surface and the sidewall of the semiconductor chip 101, the first shielding layer is connected with the peripheral edge of the bottom shielding layer, so that the semiconductor chip in the package structure is completely or omnidirectionally covered by the bottom shielding layer and the first shielding layer, therefore, the electric field and the magnetic field can not enter the packaging structure through the bottom of the packaging structure to bring electromagnetic interference to the semiconductor chip, so that the semiconductor chip is electromagnetically shielded in all directions, and the electromagnetic shielding effect is further improved.
In this embodiment, a first etching process is used to etch the second isolation layer 111, and the first isolation layer 110 is used as a stop layer, so as to form a second opening in the second isolation layer 111; then, a second etching process is performed to etch the second isolation layer 111 and the first isolation layer 110, a first opening is formed in the second isolation layer 111 and the first isolation layer 110, and a corresponding mask layer may be formed on the surface of the second isolation layer 111 before the first etching process or the second etching process is performed. It should be noted that the second etching process may also be performed before the first etching process.
In other embodiments, when the isolation layer is a single-layer structure, two etching processes may be performed to form the first opening and the second opening, respectively, and the depth of the formed second opening is controlled by controlling the time of the etching process (the depth of the second opening is smaller than the thickness of the isolation layer).
Referring to fig. 15, a metal material is filled in the first openings to form pads 102, and a metal material is filled in the second openings to form a bottom shielding layer 114; forming a metal bump 130 on the pad 102; referring to fig. 16, after forming the metal bumps 130, the wafer is diced to form a plurality of discrete semiconductor chips 101 having the bottom shield layer 114.
In one embodiment, the pads 102 and the bottom shield layer 114 are formed by the same process, including the steps of: forming a metal material layer in the first opening and the second opening and on the surface of the isolation layer, wherein the metal material layer is formed by physical vapor deposition, sputtering or electroplating technology, and the metal material layer can be made of one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold and silver; and removing the metal material layer higher than the surface of the isolation layer by planarization, forming the bonding pad 102 in the first opening, and forming the bottom shielding layer 114 in the second opening.
Referring to fig. 17, fig. 17 is a schematic top view structure diagram of the pads 102 and the bottom shielding layer 114 in fig. 16, and referring to fig. 16 and fig. 17 in combination, the functional surface of the semiconductor chip 101 has the bottom shielding layer 114, the bottom shielding layer 114 covers the entire functional surface of the semiconductor chip 101, the peripheral edge of the bottom shielding layer 114 is flush with the peripheral sidewall of the semiconductor chip 101, the pads 102 penetrate through the bottom shielding layer 114, and the pads 102 and the bottom shielding layer 114 are isolated by the isolation layer 111.
The process of forming the bottom shielding layer 114 is integrated with the existing semiconductor chip manufacturing process, and the manufacturing process of the bottom shielding layer 114 can be performed synchronously with the manufacturing process of the bonding pad 102, so that the manufacturing process is simplified, the process difficulty is reduced, and the efficiency is improved.
Referring to fig. 18, the semiconductor chip 101 having the bottom shield layer 114 is flip-chip mounted on the substrate 301 such that the metal bump 130 on each semiconductor chip 101 is connected to the corresponding input port on the front surface of the substrate 301; forming an underfill layer 132 between the functional surface of the semiconductor chip 101 and the front surface of the substrate 301; forming a first shielding layer 103 covering the non-functional surface and the sidewall surface of the semiconductor chip 101 and the side surface of the underfill layer 132; forming a second shield layer 104 on the first shield layer 103; forming a plastic packaging layer 105 on the second shielding layer 104 and the substrate 301 between the semiconductor chips 101; an external contact structure 124 connected to an output port is formed on the back surface of the substrate 301.
It should be noted that other definitions or descriptions of the same or similar structures in the second embodiment as in the first embodiment are omitted in the second embodiment, and specific reference is made to the definitions or descriptions of corresponding parts in the first embodiment.
An embodiment of the present invention further provides a package structure, please refer to fig. 11 or fig. 18, including:
the circuit board comprises a substrate 301, wherein the substrate 301 is provided with a plurality of circuit structures, the front surface of the substrate 301 is provided with a plurality of input ports, the back surface of the substrate is provided with a plurality of output ports, and the input ports and the output ports are respectively connected with the corresponding circuit structures;
a plurality of semiconductor chips 101 flip-chip mounted on the front surface of the substrate 301, each semiconductor chip 101 including a functional surface and a non-functional surface opposite to the functional surface, the functional surface having a plurality of pads 102 thereon, the pads 102 having metal bumps 130 thereon, the metal bumps 130 on each semiconductor chip 101 being connected to corresponding input ports on the front surface of the substrate 301;
an underfill layer 132 between the functional surface of the semiconductor chip 101 and the front surface of the substrate 301;
a first shielding layer 103 covering the non-functional surface and sidewall surface of the semiconductor chip 101 and the side surface of the underfill layer 132;
a second shield layer 104 on the first shield layer 103;
an external contact structure 124 on the back side of the substrate 301 connected to an output port.
In an embodiment, the first shielding layer 103 is formed by a sputtering process, and the second shielding layer 104 is formed by a selective plating process, a dispensing process, or a screen printing process. The first shielding layer 103 is made of copper, tungsten or aluminum, and the second shielding layer 104 is made of copper, solder or conductive silver paste.
In another embodiment, the first shielding layer 103 is a magnetic field shielding layer and the second shielding layer 104 is an electric field shielding layer; or the first shielding layer 103 is an electric field shielding layer, and the second shielding layer 104 is a magnetic field shielding layer. The electric field shielding layer is made of copper, tungsten and aluminum; the magnetic field shielding layer is made of CoFeB alloy, CoFeTa, NiFe, Co, CoFe, CoPt or Ni, Co and Fe alloy.
In an embodiment, referring to fig. 18, the functional surface of the semiconductor chip 101 further has a bottom shielding layer 114, the bottom shielding layer 114 covers the entire functional surface of the semiconductor chip 101, a peripheral edge of the bottom shielding layer 114 is flush with a peripheral sidewall of the semiconductor chip 101, the pads 102 penetrate through the bottom shielding layer 114, and the pads 102 are isolated from the bottom shielding layer 114 by an isolation layer 111; the first shielding layer 103 is connected with the peripheral edge of the bottom shielding layer 114.
The external contact structure 124 is a solder ball, or the external contact structure includes a metal pillar and a solder ball on the metal pillar.
In one embodiment, the method further comprises: a conductive contact structure in the substrate 301, the conductive contact structure being electrically connected to the first shielding layer.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims (8)

1. A package structure, comprising:
the circuit structure comprises a substrate, a plurality of circuit structures and a plurality of output ports, wherein the substrate is internally provided with the plurality of circuit structures;
the semiconductor chip structure comprises a substrate, a plurality of semiconductor chips, a bottom shielding layer and an isolation layer, wherein the semiconductor chips are inversely arranged on the front surface of the substrate, each semiconductor chip comprises a functional surface and a non-functional surface opposite to the functional surface, the functional surfaces are provided with a plurality of bonding pads, metal lugs are arranged on the bonding pads, the metal lugs on each semiconductor chip are connected with corresponding input ports on the front surface of the substrate, the functional surfaces of the semiconductor chips are also provided with the bottom shielding layer, the bottom shielding layer covers the whole functional surface of the semiconductor chip, the peripheral edge of the bottom shielding layer is flush with the peripheral side walls of the semiconductor chip, the bonding pads penetrate through the bottom shielding layer, and the bonding pads are isolated from the bottom; and the forming process of the semiconductor chip with the bottom shielding layer is as follows: providing a wafer, wherein a plurality of semiconductor chips are formed on the wafer, and each semiconductor chip comprises a top dielectric layer and a top interconnection structure positioned in the top dielectric layer; forming an isolation layer on the top dielectric layer; etching the isolation layer, forming a plurality of first openings and second openings surrounding the first openings in the isolation layer, wherein the rest of the isolation layer is only positioned between the first openings and the second openings, and the first openings and the second openings are separated; filling metal materials into the first openings to form a plurality of bonding pads, and filling metal materials into the second openings to form a bottom shielding layer; after forming a bonding pad and a bottom shielding layer, cutting the wafer to form a plurality of discrete semiconductor chips with the bottom shielding layer;
the underfill layer is positioned between the functional surface of the semiconductor chip and the front surface of the substrate;
the first shielding layer coats the non-functional surface and the side wall surface of the semiconductor chip and the side surface of the bottom filling layer, and the first shielding layer is connected with the peripheral edge of the bottom shielding layer;
a second shielding layer on the first shielding layer;
and an external contact structure located on the back surface of the substrate and connected to the output port.
2. The package structure of claim 1, wherein the first shielding layer is formed by a sputtering process, the first shielding layer further covers at least a portion of the substrate surface between the semiconductor chips, and the second shielding layer is formed by a selective plating process, a dispensing process, or a screen printing process.
3. The package structure of claim 2, wherein the material of the first shielding layer is copper, tungsten or aluminum, and the material of the second shielding layer is copper, solder or conductive silver paste.
4. The package structure of claim 1, wherein the first shielding layer is a magnetic field shielding layer and the second shielding layer is an electric field shielding layer; or the first shielding layer is an electric field shielding layer, and the second shielding layer is a magnetic field shielding layer.
5. The package structure of claim 4, wherein the material of the electric field shielding layer is copper, tungsten, aluminum; the magnetic field shielding layer is made of CoFeB alloy, CoFeTa, NiFe, Co, CoFe, CoPt or Ni, Co and Fe alloy.
6. The package structure of claim 1, wherein the external contact structure is a solder ball, or the external contact structure comprises a metal pillar and a solder ball on the metal pillar.
7. The package structure of claim 1, further comprising: a conductive contact structure in the substrate, the conductive contact structure being electrically connected to the first shielding layer.
8. An individual package structure formed by dividing the package structure according to claims 1 to 7, comprising:
the circuit structure is arranged in the substrate, the front surface of the substrate is provided with a plurality of input ports, the back surface of the substrate is provided with a plurality of output ports, and the input ports and the output ports are respectively connected with the circuit structure; the semiconductor chip is inversely arranged on the front surface of the substrate, the semiconductor chip comprises a functional surface and a non-functional surface opposite to the functional surface, the functional surface is provided with a plurality of bonding pads, the bonding pads are provided with metal lugs, the metal lugs on the semiconductor chip are connected with corresponding input ports on the front surface of the substrate, the functional surface of the semiconductor chip is also provided with a bottom shielding layer, the bottom shielding layer covers the whole functional surface of the semiconductor chip, the peripheral edge of the bottom shielding layer is flush with the peripheral side walls of the semiconductor chip, the bonding pads penetrate through the bottom shielding layer, and the bonding pads are isolated from the bottom shielding layer through an isolation layer;
the underfill layer is positioned between the functional surface of the semiconductor chip and the front surface of the substrate;
the first shielding layer coats the non-functional surface and the side wall surface of the semiconductor chip and the side surface of the bottom filling layer, and the first shielding layer is connected with the peripheral edge of the bottom shielding layer;
a second shielding layer on the first shielding layer;
and an external contact structure located on the back surface of the substrate and connected to the output port.
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