CN110473489B - Pixel arrangement structure of double-gate panel - Google Patents
Pixel arrangement structure of double-gate panel Download PDFInfo
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- CN110473489B CN110473489B CN201910655278.5A CN201910655278A CN110473489B CN 110473489 B CN110473489 B CN 110473489B CN 201910655278 A CN201910655278 A CN 201910655278A CN 110473489 B CN110473489 B CN 110473489B
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- 230000009977 dual effect Effects 0.000 claims description 8
- 238000007599 discharging Methods 0.000 abstract description 4
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2074—Display of intermediate tones using sub-pixels
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
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- Condensed Matter Physics & Semiconductors (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
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Abstract
The invention relates to the technical field of display, in particular to a pixel arrangement structure of a double-gate panel, which is characterized in that the pixel arrangement driven by each data wire is changed, and sub-pixels of the same type are connected with the same data wire through a corresponding transistor, so that the same data wire drives the same pixel, and the aim of reducing the pure-color power consumption can be fulfilled. The pixel arrangement structure of the double-gate panel designed by the scheme can change the existing switching of each row into the switching of each frame, so that the frequency of charging and discharging of the driving IC on the data wiring is greatly reduced, and the power consumption is reduced.
Description
Technical Field
The invention relates to the technical field of display, in particular to a pixel arrangement structure of a double-gate panel.
Background
Along with the continuous development of panel display technology, various characteristic display panels are applied to ordinary life, especially popularization of smart phones, and panel technology is also greatly applied. Today's smartphones pursue higher screen ratios and higher resolutions, high screen ratios require display panels to achieve extremely narrow frames, while high resolutions mean that more pixel and signal routing designs are required, and more signal output channels are required for driving ICs, which can lead to increased IC cost and volume, which can affect the size of the lower frame, and panels of Dual Gate architecture have been developed in view of this. Compared with the common panel, the Dual Gate panel has double Gate wiring and half Data wiring, so that high resolution and narrowing of the lower frame are realized. However, in the pixel arrangement of the Dual Gate panel, when displaying a pure color picture, such as red, green and blue, the voltage on the Data line is not turned once every frame, but is turned once every row, which causes the problem of excessive display power consumption.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: a pixel arrangement structure of a dual gate panel is provided.
In order to solve the technical problems, the invention adopts the following scheme:
a pixel arrangement structure of a double-gate panel comprises a plurality of main pixel areas, a plurality of data wires and a plurality of gate wires;
each main pixel area comprises three sub-pixel areas which are sequentially arranged along the vertical direction, each sub-pixel area is positioned between two adjacent data wires, two transistors and two different types of sub-pixels are arranged in each sub-pixel area, the source electrode of each transistor in each sub-pixel area is correspondingly connected with one data wire, the grid electrode of each transistor in each sub-pixel area is correspondingly connected with one grid wire, the drain electrode of each transistor in each sub-pixel area is correspondingly connected with one sub-pixel, and the sub-pixels of the same type are connected with the same data wire through a corresponding transistor.
The invention has the beneficial effects that:
according to the scheme, the pixel arrangement driven by each data wiring is changed, the same type of sub-pixels are connected with the same data wiring through the corresponding transistor, the same data wiring is used for driving the same type of pixels, and the aim of reducing the pure-color power consumption can be fulfilled. The pixel arrangement structure of the double-gate panel designed by the scheme can change the existing switching of each row into the switching of each frame, so that the frequency of charging and discharging of the driving IC on the data wiring is greatly reduced, and the power consumption is reduced.
Drawings
Fig. 1 is a schematic structural view of a pixel arrangement structure of a dual gate panel according to the present invention;
description of the reference numerals:
1. a data trace; 2. a gate trace; 3. a sub-pixel.
Detailed Description
In order to describe the technical contents, the achieved objects and effects of the present invention in detail, the following description will be made with reference to the embodiments in conjunction with the accompanying drawings.
The most critical concept of the invention is as follows: the same type of sub-pixels are connected with the same data wiring through a corresponding transistor, so that the same data wiring drives the same pixel, and the aim of reducing the pure-color power consumption can be fulfilled.
Referring to fig. 1, the present invention provides the following technical solutions:
a pixel arrangement structure of a double-gate panel comprises a plurality of main pixel areas, a plurality of data wires and a plurality of gate wires;
each main pixel area comprises three sub-pixel areas which are sequentially arranged along the vertical direction, each sub-pixel area is positioned between two adjacent data wires, two transistors and two different types of sub-pixels are arranged in each sub-pixel area, the source electrode of each transistor in each sub-pixel area is correspondingly connected with one data wire, the grid electrode of each transistor in each sub-pixel area is correspondingly connected with one grid wire, the drain electrode of each transistor in each sub-pixel area is correspondingly connected with one sub-pixel, and the sub-pixels of the same type are connected with the same data wire through a corresponding transistor.
From the above description, the beneficial effects of the invention are as follows:
according to the scheme, the pixel arrangement driven by each data wiring is changed, the same type of sub-pixels are connected with the same data wiring through the corresponding transistor, the same data wiring is used for driving the same type of pixels, and the aim of reducing the pure-color power consumption can be fulfilled. The pixel arrangement structure of the double-gate panel designed by the scheme can change the existing switching of each row into the switching of each frame, so that the frequency of charging and discharging of the driving IC on the data wiring is greatly reduced, and the power consumption is reduced.
Further, the plurality of main pixel areas are arranged in an array.
As can be seen from the above description, the plurality of main pixel areas are arranged in an array, so that the limited display space of the panel can be reasonably utilized, and the display effect of the pixels of the sub-pixels in each main pixel area is better.
Further, two adjacent data wires are parallel to each other, two adjacent gate wires are parallel to each other, and the data wires are perpendicular to the gate wires.
Further, the sub-pixels of the sub-pixels in each sub-pixel region display different colors.
As can be seen from the above description, the color and brightness of each sub-pixel region can be ensured, and the display of red, green, or blue can be realized.
Further, the three sub-pixel areas sequentially arranged along the vertical direction comprise a first sub-pixel area, a second sub-pixel area and a third sub-pixel area, the colors of the sub-pixels in the first sub-pixel area are green and blue, the colors of the sub-pixels in the second sub-pixel area are red and green, and the colors of the sub-pixels in the third sub-pixel area are blue and red.
Further, the gates of the two transistors in the same sub-pixel region are respectively and correspondingly connected with different gate wirings, and the sources of the two transistors in the same sub-pixel region are respectively and correspondingly connected with different data wirings.
According to the description, the same-color sub-pixels can be connected in the same data wiring mode, so that the problem that the data wiring needs to be charged and discharged frequently can be solved, and the pure-color power consumption is greatly reduced.
Referring to fig. 1, a first embodiment of the present invention is as follows:
the pixel arrangement structure of the double-gate panel comprises a plurality of main pixel areas, a plurality of data wires 1 and a plurality of gate wires 2;
each main pixel area comprises three sub-pixel areas which are sequentially arranged along the vertical direction, each sub-pixel area is positioned between two adjacent data wires 1, two transistors and two different types of sub-pixels 3 are arranged in each sub-pixel area, the source electrode of each transistor in each sub-pixel area is correspondingly connected with one data wire 1, the grid electrode of each transistor in each sub-pixel area is correspondingly connected with one grid wire 2, the drain electrode of each transistor in each sub-pixel area is correspondingly connected with one sub-pixel 3, and the sub-pixels 3 of the same type are connected with the same data wire 1 through a corresponding transistor.
The main pixel areas are arranged in an array mode.
Two adjacent data wires 1 are parallel to each other, two adjacent gate wires 2 are parallel to each other, and the data wires 1 are perpendicular to the gate wires 2.
The grid electrodes of the two transistors in the same sub-pixel region are correspondingly connected with different grid wires 2 respectively, and the source electrodes of the two transistors in the same sub-pixel region are correspondingly connected with different data wires 1 respectively.
The sub-pixels of the sub-pixels 3 in each sub-pixel area display different colors.
The three sub-pixel areas sequentially arranged along the vertical direction comprise a first sub-pixel area, a second sub-pixel area and a third sub-pixel area, the colors of the sub-pixels 3 in the first sub-pixel area are green and blue, the colors of the sub-pixels 3 in the second sub-pixel area are red and green, and the colors of the sub-pixels 3 in the third sub-pixel area are blue and red.
The conventional pixel arrangement structure of the dual-gate panel can only be switched once per row during the pixel charging process, for example, if a green frame is displayed during the pixel charging process, the voltage written by the second data trace (denoted by D2 in fig. 1) is from-5 v→0→5v→0.. . The next frame is +5V→0→ +5V→0 for high frequency switching. . . As a result, the driving IC needs to charge and discharge D2 frequently, which consumes more power.
The pixel arrangement structure of the double-gate panel designed by the scheme can realize switching once every frame, for example, in the pixel charging process, if a green picture is displayed, the second data trace (denoted by D2 in fig. 1) always writes-5V voltage, and only when the next frame is performed, the voltage of the N frames of D2 is +5v: -5V, -5V. . . -5V, the voltage of the n+1 frame of D2 is switched to: +5v, +5v. . . +5v, thereby improving the problem of excessive power consumption of the existing double gate panel.
In summary, according to the pixel arrangement structure of the dual-gate panel provided by the invention, the pixel arrangement driven by each data trace is changed, and the same type of sub-pixels are connected with the same data trace through the corresponding transistor, so that the same data trace drives the same pixel, and the purpose of reducing the pure-color power consumption can be realized. The pixel arrangement structure of the double-gate panel designed by the scheme can change the existing switching of each row into the switching of each frame, so that the frequency of charging and discharging of the driving IC on the data wiring is greatly reduced, and the power consumption is reduced.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent changes made by the specification and drawings of the present invention, or direct or indirect application in the relevant art, are included in the scope of the present invention.
Claims (6)
1. The pixel arrangement structure of the double-gate panel is characterized by comprising a plurality of main pixel areas, a plurality of data wires and a plurality of gate wires;
each main pixel area comprises three sub-pixel areas which are sequentially arranged along the vertical direction, each sub-pixel area is positioned between two adjacent data wires, two transistors and two different types of sub-pixels are arranged in each sub-pixel area, the source electrode of each transistor in each sub-pixel area is correspondingly connected with one data wire, the grid electrode of each transistor in each sub-pixel area is correspondingly connected with one grid wire, the drain electrode of each transistor in each sub-pixel area is correspondingly connected with one sub-pixel, and the same type of sub-pixels are connected with the same data wire through a corresponding transistor, so that the same data wire can drive the same pixel.
2. The pixel arrangement structure of a dual gate panel according to claim 1, wherein a plurality of the main pixel regions are arranged in an array.
3. The pixel arrangement structure of claim 1, wherein two adjacent data wires are parallel to each other, two adjacent gate wires are parallel to each other, and the data wires are perpendicular to the gate wires.
4. The pixel arrangement structure of a dual gate panel according to claim 1, wherein the sub-pixels of the sub-pixels in each sub-pixel region display different colors.
5. The pixel arrangement structure of a dual gate panel according to claim 4, wherein the three sub-pixel regions sequentially arranged in the vertical direction include a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region, the sub-pixels in the first sub-pixel region being green and blue, the sub-pixels in the second sub-pixel region being red and green, and the sub-pixels in the third sub-pixel region being blue and red.
6. The pixel arrangement structure of claim 1, wherein gates of two transistors in the same sub-pixel region are respectively connected to different gate wirings, and sources of two transistors in the same sub-pixel region are respectively connected to different data wirings.
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| CN111028802B (en) * | 2019-12-12 | 2022-04-05 | 福建华佳彩有限公司 | Driving method of double-gate panel |
| CN113777839B (en) * | 2021-08-19 | 2022-08-05 | 深圳市华星光电半导体显示技术有限公司 | Display panel and mobile terminal |
| CN116246566B (en) * | 2023-01-30 | 2024-05-28 | 惠科股份有限公司 | Display panel and electronic equipment |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104090440A (en) * | 2014-06-30 | 2014-10-08 | 上海天马微电子有限公司 | Pixel structure, liquid crystal display array substrate and liquid crystal display panel |
| CN108628049A (en) * | 2018-05-31 | 2018-10-09 | 京东方科技集团股份有限公司 | array substrate, display panel and display device |
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| CN102930809B (en) * | 2011-08-12 | 2016-02-10 | 上海中航光电子有限公司 | The transversely arranged dot structure that bigrid drives and display panel |
| CN102881268A (en) * | 2012-09-07 | 2013-01-16 | 北京京东方光电科技有限公司 | Liquid crystal display driving method and liquid crystal display |
| CN105182638A (en) * | 2015-08-28 | 2015-12-23 | 重庆京东方光电科技有限公司 | Array substrate, display device and drive method thereof |
| CN105629606A (en) * | 2016-01-13 | 2016-06-01 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and driving method thereof |
| CN109830203B (en) * | 2019-03-05 | 2022-02-25 | 武汉天马微电子有限公司 | Display panel, driving method thereof and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104090440A (en) * | 2014-06-30 | 2014-10-08 | 上海天马微电子有限公司 | Pixel structure, liquid crystal display array substrate and liquid crystal display panel |
| CN108628049A (en) * | 2018-05-31 | 2018-10-09 | 京东方科技集团股份有限公司 | array substrate, display panel and display device |
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