CN110459676B - Preparation method of resistive random access memory - Google Patents
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- CN110459676B CN110459676B CN201910808942.5A CN201910808942A CN110459676B CN 110459676 B CN110459676 B CN 110459676B CN 201910808942 A CN201910808942 A CN 201910808942A CN 110459676 B CN110459676 B CN 110459676B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- 239000000463 material Substances 0.000 claims abstract description 67
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 58
- 239000007772 electrode material Substances 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 32
- 238000000151 deposition Methods 0.000 claims abstract description 31
- 239000010410 layer Substances 0.000 claims description 107
- 229910052751 metal Inorganic materials 0.000 claims description 31
- 239000002184 metal Substances 0.000 claims description 31
- 239000007789 gas Substances 0.000 claims description 23
- 230000004888 barrier function Effects 0.000 claims description 19
- 230000008021 deposition Effects 0.000 claims description 17
- 239000011229 interlayer Substances 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 11
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 8
- 238000005498 polishing Methods 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 8
- 239000001257 hydrogen Substances 0.000 claims description 5
- 229910052739 hydrogen Inorganic materials 0.000 claims description 5
- 229910052786 argon Inorganic materials 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 229910052756 noble gas Inorganic materials 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 18
- 239000011800 void material Substances 0.000 abstract description 5
- 230000008859 change Effects 0.000 description 10
- 238000005429 filling process Methods 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 230000015654 memory Effects 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000013078 crystal Substances 0.000 description 5
- 238000005137 deposition process Methods 0.000 description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000003792 electrolyte Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910000314 transition metal oxide Inorganic materials 0.000 description 1
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
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Abstract
The invention provides a preparation method of a resistive random access memory, which comprises the following steps of S1: providing a substrate, wherein a hole is formed in the top of the substrate; step S2: depositing electrode material in the holes for multiple times to form a lower electrode; step S3: forming a resistive material layer on the upper surface of the lower electrode and the substrate by depositing a resistive material; step S4: an upper electrode is formed over the resistive material layer. The invention adopts the method of depositing electrode material in holes for multiple times to form the lower electrode, solves the problems of insufficient filling and void filling existing in the titanium nitride electrode material filling method in the prior art, and improves the process uniformity.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a preparation method of a resistive random access memory.
Background
With the development of semiconductor technology, the market demand for nonvolatile memory is increasingly shifted to high capacity, low power consumption, high density, and low cost. Resistive random access memory (Resistive Random Access Memory, RRAM) has strong application potential as a research hot spot of next-generation memories, and is considered as the memory with the most commercial value. However, the existing manufacturing process of the resistive random access memory has a lot of defects, especially the improvement of the process uniformity of the resistive random access memory has a lot of problems.
The Resistive Random Access Memory (RRAM) generally comprises a substrate, a lower electrode (BE), a resistive material layer and an upper electrode (TE), wherein an electrode material filling process of the lower electrode and a resistive material deposition process of the resistive material layer are key points for improving the process uniformity of the resistive memory. In the prior art, the electrode material of the lower electrode is usually titanium nitride (TiN for short), the growth morphology of the titanium nitride is clustered crystal, the hole size for filling the titanium nitride is smaller, the oblique angle is larger, and the problems of insufficient filling and void filling exist in the traditional titanium nitride filling method are solved. The titanium nitride filling problem and the appearance of the lower electrode can influence the deposition process of the later resistance change material layer, and the titanium nitride exposed on the outer layer can be oxidized to a certain extent, so that the appearance is uneven when the resistance change material layer is deposited, and the traditional titanium nitride filling process and the resistance change material layer deposition process can cause poor process uniformity, so that the contact resistance between the resistance change material layer and the lower electrode can be increased.
Disclosure of Invention
The invention aims to provide a preparation method of a resistive random access memory, which is used for solving the problem of poor process uniformity of the resistive random access memory caused by an electrode material filling process and a resistive random access material layer deposition process, so as to reduce the contact resistance between the resistive random access material layer and a lower electrode.
In order to solve the technical problems, the preparation method of the resistive random access memory comprises the following steps:
step S1: providing a substrate, wherein a hole is formed in the top of the substrate;
step S2: depositing electrode material in the holes for multiple times to form a lower electrode;
step S3: forming a resistance change material layer on the upper surfaces of the lower electrode and the substrate;
step S4: an upper electrode is formed over the resistive material layer.
Optionally, in the resistive random access memory, the substrate includes a metal interconnection layer and a dielectric barrier layer located above the metal interconnection layer, wherein the metal interconnection layer includes an interlayer dielectric layer and a metal interconnection line formed in the interlayer dielectric layer, and the hole is disposed in the dielectric barrier layer and exposes a part of the metal interconnection line.
Optionally, in the resistive random access memory, the electrode material comprises titanium nitride.
Optionally, in the resistive random access memory, the step S2 further includes: the hole surfaces are bombarded with a noble gas before each deposition of electrode material.
Optionally, in the resistive random access memory, the rare gas includes argon.
Optionally, in the resistive random access memory, the deposition of the electrode material is stopped when the hole is filled with the electrode material.
Optionally, in the resistive random access memory, the step S3 further includes: and before the resistive material layer is formed, deoxidizing the surface of the lower electrode by adopting a reducing gas.
Optionally, in the resistive random access memory, the reducing gas includes hydrogen.
Optionally, in the resistive random access memory, the step S3 further includes: and before deoxidizing the surface of the lower electrode by adopting reducing gas, performing chemical mechanical polishing on the upper surfaces of the lower electrode and the substrate to remove redundant electrode materials.
Optionally, in the resistive random access memory, in the step S2, a thickness of the electrode material layer deposited each time is less than 1/6 of a diameter of the hole.
In summary, the present invention provides a method for manufacturing a resistive random access memory, which includes providing a substrate, forming a hole on top of the substrate, filling an electrode material in the hole to form a lower electrode, forming a resistive material layer on the upper surface of the lower electrode and the substrate, and forming an upper electrode on the resistive material layer. The method for forming the lower electrode by depositing the electrode material in the holes for multiple times solves the problems of insufficient filling of the titanium nitride and void filling caused by the fact that the growth morphology of the titanium nitride is cluster crystal, the size of the holes filled with the titanium nitride is smaller and the oblique angle is larger, thereby improving the process uniformity and reducing the contact resistance between the resistance change material layer and the lower electrode.
Drawings
FIG. 1 is a schematic diagram of a resistive random access memory;
FIG. 2 is a schematic diagram of the structure of the bottom electrode of FIG. 1 after titanium nitride filling;
FIG. 3 is a perspective view of the structure of the lower electrode of FIG. 2 after titanium nitride filling;
FIG. 4 is a schematic diagram of a resistive random access memory according to an embodiment of the invention;
FIGS. 5-7 are schematic diagrams illustrating a titanium nitride filling process of a bottom electrode according to an embodiment of the present invention;
FIG. 8 is a perspective view of a structure of a lower electrode filled with titanium nitride according to an embodiment of the present invention;
in fig. 1 to 3:
01-metal interconnection layer, 011-interlayer dielectric layer, 012-metal interconnection line, 02-dielectric barrier layer, 021-hole, 03-lower electrode, 031-titanium nitride layer, 04-resistance change material layer, 05-upper electrode;
in fig. 4 to 8:
10-metal interconnection layers, 101-interlayer dielectric layers, 102-metal interconnection lines, 20-dielectric barrier layers, 201-holes, 30-lower electrodes, 301-first electrode material layers, 302-second electrode material layers, 40-resistance change material layers and 50-upper electrodes.
Detailed Description
As a research hotspot of the next-generation memory, the Resistive Random Access Memory (RRAM) is mainly structured as shown in fig. 1, and comprises a substrate, a lower electrode 03, a resistive material layer 04 positioned on the upper surfaces of the lower electrode 03 and the substrate, and an upper electrode 05 positioned on the resistive material layer 04, wherein a hole (not shown in the figure) is arranged on the top of the substrate, and electrode materials are filled in the hole to form the lower electrode 03. The substrate comprises a metal interconnection layer 01 and a dielectric barrier layer 02 positioned above the metal interconnection layer 01, wherein the metal interconnection layer 01 comprises an interlayer dielectric layer 011 and a metal interconnection line 012, and the hole is arranged on the dielectric barrier layer 02, penetrates through the dielectric barrier layer 02 and exposes a part of the metal interconnection line 012. Wherein the material of the interlayer dielectric layer 011 comprises at least one of low dielectric constant material, silicon dioxide, silicon nitride and silicon oxynitride, preferably low dielectric constant material, the material of the metal interconnection 012 is preferably metallic copper, the material of the dielectric barrier layer 02 is preferably nitrogen doped silicon carbide (Nitride Doped Silicon Carbide abbreviated as NDC), the electrode materials of the lower electrode 03 and the upper electrode 05 are preferably titanium nitride (abbreviated as TiN), and the material of the resistive material layer 04 is preferably Ta and TaO x Is a mixture of (a) and (b).
The electrode material filling of the lower electrode 03 and the deposition of the resistive material layer 04 are key points for improving the process uniformity of the resistive memory. Because the growth morphology of the electrode material titanium nitride is cluster crystal, the hole size (diameter is 80-100 nm) for filling the titanium nitride is smaller, and the oblique angle is larger (the included angle between the oblique edge of the hole and the upper surface of the medium blocking layer 02 is 75-85 degrees), the traditional titanium nitride filling method has the problems of insufficient filling and void filling.
Referring to fig. 2, titanium nitride is deposited in the holes to form a titanium nitride layer 031, and then the titanium nitride layer 031 is subjected to chemical mechanical polishing to form a lower electrode 03. Since the titanium nitride as the electrode material of the lower electrode 03 grows in clusters and the angle of the bevel angle of the edge of the hole is large, if the titanium nitride deposited at one time exceeds 1/2 of the diameter of the hole, the titanium nitride with the side wall of the hole as the growth base point may touch each other and generate stress influence before the titanium nitride grows to a preset length, so that the titanium nitride cluster crystal is made into a bracket, and the problem of void is generated in the filling process. The filling problem and morphology of the electrode material of the lower electrode 03 also affect the deposition process of the resistive material layer, resulting in uneven morphology when the resistive material layer is deposited. Further, since the titanium nitride as an electrode material is exposed to the outer layer to be oxidized to some extent, the contact resistance between the resistive material layer 04 and the lower electrode 03 is increased.
A structural perspective view of the titanium nitride filled lower electrode 03 in fig. 2 is shown in fig. 3, wherein a white region in the middle of the titanium nitride layer 031 represents a region where voids exist, and thus the lower electrode 03 has a phenomenon of filling the voids. The thin titanium nitride filling on the resistive random access memory has the phenomenon of insufficient filling, the thicker titanium nitride filling can generate the phenomenon of filling holes in holes, and as titanium nitride grows in the shape of clustered crystals and is exposed in the air after chemical mechanical polishing, the titanium nitride on the surfaces of the holes can be oxidized, so that the phenomenon of uneven shape can also occur when a resistive material layer is deposited at the back.
Based on the findings, the invention provides a preparation method of a resistive random access memory, which forms a lower electrode by adopting a method of depositing electrode materials in holes for multiple times, avoids the phenomenon that the electrode materials generate holes or are not fully filled in the filling process, thereby improving the shape uniformity of the lower electrode and the resistive random access material layer, optimizing the contact between the lower electrode and the resistive random access material layer, and further reducing the contact resistance between the resistive random access material layer and the lower electrode.
In order to make the objects, advantages and features of the present invention more apparent, the following more particular description of the method for manufacturing a resistive random access memory according to an embodiment of the present invention will be presented with reference to fig. 4 to 8. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Referring to FIG. 4, the invention provides a method for manufacturing a resistive random access memory, which comprises
Step S1: providing a substrate, wherein a hole 201 is formed in the top of the substrate;
step S2: depositing electrode material in the holes 201 a plurality of times to form the lower electrode 30;
step S3: forming a resistive material layer 40 on the lower electrode 30 and the upper surface of the substrate;
step S4: an upper electrode 50 is formed over the resistive material layer 40.
In step S1, a substrate is first provided, and a hole 201 is provided on the top of the substrate. The substrate may be a conventional silicon substrate or other substrate comprising a layer of semiconductive material. For example, the substrate may include the metal interconnection layer 10 and the dielectric barrier layer 20 located above the metal interconnection layer 10, where the metal interconnection layer 10 includes the interlayer dielectric layer 101 and the metal interconnection line 102, the upper surface of the metal interconnection line 102 is flush with the upper surface of the interlayer dielectric layer 101, and the lower surface of the metal interconnection line 102 may be flush with the interlayer dielectric layer 101 (where the metal interconnection line 102 penetrates through the interlayer dielectric layer 101) or may be buried in the interlayer dielectric layer 101. The thickness of the interlayer dielectric layer 101 is 165 nm-180 nm, and the material includes at least one of Low dielectric constant material (Low-k), silicon dioxide, silicon nitride and silicon oxynitride, preferably Low dielectric constant material (Low-k), where the Low dielectric constant material (Low-k) includes SiOCH film, fluorosilicone glass (FSG), carbon doped silicon oxide (black diamond) or nitrogen doped silicon carbide (BLOK), etc. The thickness of the metal interconnection line 102 is 120 nm-150 nm, and the material is preferably metallic copper. The material of the dielectric barrier layer 20 is preferably nitrogen doped silicon carbide (Nitride Doped Silicon Carbide abbreviated as NDC) with a thickness of 25 nm-35 nm, and the purpose of the dielectric barrier layer is to prevent diffusion of metal into the dielectric. The hole 201 at the top of the substrate is disposed in the dielectric barrier layer 20, the diameter of the hole 201 is 80 nm-100 nm, and the hole penetrates through the dielectric barrier layer 20 in a truncated cone shape, and exposes a portion of the metal interconnection line 102. The number of the holes 201 may be one or more than two, and when the number of the holes 201 is at least two, the lateral distance between the holes is greater than 100nm, and each hole exposes a part of the metal interconnection line 102, preferably the holes have the same size and shape.
Referring to fig. 5 to 7, in step S2, electrode material is deposited in the holes 201 a plurality of times to form the lower electrode 30. The electrode material of the lower electrode 30 may be copper, platinum, titanium nitride, or the like, preferably titanium nitride, and in the following embodiments, titanium nitride is used as the electrode material. The method for depositing the holes 201 for multiple times comprises the following steps: depending on the size of the particular hole 201, titanium nitride is deposited multiple times, and each time titanium nitride is deposited to a thickness less than 1/6 the diameter of the hole 201, the deposition is stopped when the hole 201 is filled with electrode material, i.e., the deposition is stopped when the hole 201 is filled with titanium nitride. Because the thickness of titanium nitride deposited each time is reduced to less than 1/6 of the diameter of the hole, titanium nitride taking the hole wall as a growth base point does not affect each other during each deposition, so that a cavity is not generated.
In addition, the hole 201 may further add a rare gas bombardment process during the process of depositing titanium nitride multiple times, that is, the deposition surface (especially the surface of the hole) is subjected to rare gas bombardment before each time of depositing titanium nitride, where the rare gas may be argon or helium, preferably argon, and the time of each time of rare gas bombardment is preferably 15 s-25 s, and the pressure is preferably 100 mtorr-200 mtorr. In the cycle that the depth of titanium nitride filling does not exceed the depth of the holes 201 (i.e. the thickness of NDC), the surfaces of the holes 201 are bombarded with rare gas before each deposition of titanium nitride, so that oxides possibly generated on the surfaces of the holes 201 are eliminated, the filling effect of titanium nitride can be improved, the uniformity of the process is improved, and the morphology of the lower electrode is more uniform. For example, referring to fig. 5, first, the holes 201 are bombarded with a rare gas; then depositing titanium nitride in the holes 201 to form a first electrode material layer 301, wherein the thickness of the first electrode material layer 301 is less than 1/6 of the diameter of the holes 201, after the first electrode material layer 301 is formed, performing rare gas bombardment on the holes 201 again to remove oxides possibly generated on the surfaces of the holes 201, then depositing titanium nitride again to form a second electrode material layer 302, and performing rare gas bombardment again after the second electrode material layer 302 is deposited, and sequentially cycling until the holes are filled with the titanium nitride.
Referring to fig. 8, which is a perspective view of the structure of the titanium nitride filled in this embodiment, it can be seen that the hollow area of the lower electrode 30 with white middle is significantly reduced. Because the thickness of each deposition is thinned to less than 1/6 of the diameter of the hole, titanium nitride taking the hole wall as a growth base point cannot affect each other during each deposition, so that a cavity cannot be generated; meanwhile, in the cycle that the filling depth does not exceed the depth of the holes 201, the surfaces of the holes are bombarded by rare gas before titanium nitride is deposited each time, so that oxides possibly generated on the surfaces of the holes are eliminated, the filling effect of electrode materials can be improved, and the uniformity of the process is improved.
In step S4, a resistive material is deposited on the electrode 30 and the upper surface of the substrate to form a resistive material layer 40. The electrode material of the lower electrode 30 and the upper surface of the substrate need to be subjected to chemical mechanical polishing before the deposition of the resistive material, i.e., the dielectric barrier layer 20 and the upper surface of the lower electrode 30 are subjected to chemical mechanical polishing, so that the upper surface of the lower electrode 30 is flush with the upper surface of the dielectric barrier layer 20, and the surplus electrode material (i.e., titanium nitride) is removed.
A process of pre-treating the surface of the lower electrode with a reducing gas, preferably hydrogen, may be added after the chemical mechanical polishing of the upper surfaces of the dielectric barrier layer 20 and the lower electrode 30 and before the deposition of the resistive material layer, and the reducing gas is preferably hydrogen, and the pressure used in the process of pre-treating the reducing gas is preferably 50-150 mtorr, that is, the components possibly oxidized on the surface of the titanium nitride are reduced by hydrogen to remove the oxide, optimize the contact between the lower electrode and the resistive material layer, and improve the uniformity of the process.
After the electrode material of the lower electrode 30 is filled and processedAfter the chemical mechanical polishing and the reducing gas pretreatment, a resistive material layer is deposited on the upper surfaces of the lower electrode 30 and the dielectric barrier layer 20 to form a resistive material layer 40. The material of the resistive material layer 40 may be perovskite oxide, including PCMO, LCMO, LPCMO, PZT, SZO, STO; a molecular material; MIM structures based on electrolyte principles; transition metal oxides, for example: WOx, nixO, cuxO, taO x ZrO2, etc. In order to be compatible with the process as much as possible, it is preferable that the resistive material be Ta and TaO x The thickness of the resistive material layer 40 is 8nm to 10nm.
In step S5, the upper electrode 50 is formed above the resistive material layer 40, that is, the upper electrode 50 may be formed by depositing an electrode material above the resistive material layer 40, wherein the thickness of the upper electrode 50 is 38nm to 42nm, and the material may be copper, platinum, titanium nitride, or the like, preferably the same as the material of the lower electrode 30.
In the preparation process of the Resistive Random Access Memory (RRAM), the lower electrode is formed by adopting a method of multiple deposition, so that the lower electrode can not generate a cavity in the filling process. Meanwhile, the method of bombarding the surfaces of the holes by rare gas before each deposition can be adopted to eliminate oxides possibly generated on the surfaces of the holes, thereby improving the uniformity of the process. In addition, a reducing gas pretreatment process can be added before the deposition of the resistance change material layer, so that components possibly oxidized on the surface of the electrode material can be removed, the contact between the lower electrode and the resistance change material layer is optimized, and the process uniformity is improved.
Finally, it should be noted that the above-mentioned embodiments are merely preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. Equivalent changes and modifications are intended to be within the scope of the present invention as defined in the appended claims.
Claims (9)
1. The preparation method of the resistive random access memory is characterized by comprising the following steps of:
step S1: providing a substrate, wherein a hole is formed in the top of the substrate;
step S2: depositing electrode material in the holes for multiple times to form lower electrodes, and bombarding the surfaces of the holes with rare gas before each deposition of the electrode material;
step S3: forming a resistive material layer on the upper surfaces of the lower electrode and the substrate;
step S4: an upper electrode is formed over the resistive material layer.
2. The method of claim 1, wherein the substrate comprises a metal interconnect layer and a dielectric barrier layer over the metal interconnect layer, wherein the metal interconnect layer comprises an interlayer dielectric layer and a metal interconnect line formed in the interlayer dielectric layer, and the hole is formed in the dielectric barrier layer and exposes a portion of the metal interconnect line.
3. The method of manufacturing a resistive random access memory according to claim 1, wherein the electrode material comprises titanium nitride.
4. The method of manufacturing a resistive random access memory according to claim 1, wherein the noble gas comprises argon.
5. The method of manufacturing a resistive random access memory according to claim 1, wherein the deposition of the electrode material is stopped when the hole is filled with the electrode material.
6. The method for manufacturing a resistive random access memory according to claim 1, further comprising, in the step S3: and before the resistive material layer is formed, deoxidizing the surface of the lower electrode by adopting a reducing gas.
7. The method of manufacturing a resistive random access memory according to claim 6, wherein the reducing gas comprises hydrogen.
8. The method of manufacturing a resistive random access memory according to claim 6, further comprising, in the step S3: and before deoxidizing the surface of the lower electrode by adopting reducing gas, carrying out chemical mechanical polishing on the upper surfaces of the lower electrode and the substrate to remove the redundant electrode material.
9. The method of manufacturing a resistive random access memory according to claim 1, wherein in said step S2, a thickness of each deposited electrode material layer is less than 1/6 of a diameter of said hole.
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| CN105789439A (en) * | 2016-04-22 | 2016-07-20 | 中国科学院微电子研究所 | Preparation method of Cu-based resistive random access memory and memory |
| CN107887393A (en) * | 2016-09-30 | 2018-04-06 | 台湾积体电路制造股份有限公司 | Storage arrangement with single bottom electrode layer |
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| CN105789439A (en) * | 2016-04-22 | 2016-07-20 | 中国科学院微电子研究所 | Preparation method of Cu-based resistive random access memory and memory |
| CN107887393A (en) * | 2016-09-30 | 2018-04-06 | 台湾积体电路制造股份有限公司 | Storage arrangement with single bottom electrode layer |
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