CN110445139A - Control method and system of power electronic converter based on FPGA - Google Patents
Control method and system of power electronic converter based on FPGA Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J3/00—Circuit arrangements for ac mains or ac distribution networks
- H02J3/01—Arrangements for reducing harmonics or ripples
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
- Y02E40/20—Active power filtering [APF]
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Abstract
The disclosure relates to a control method and a system of a power electronic converter based on an FPGA. Wherein, the method comprises the following steps: setting the IP core based on the FPGA as a multi-level modular IP core according to the preset functional core construction complexity; converting a difference value of load harmonic current and compensation current output by an active power filter into a direct current quantity according to a synchronous rotating coordinate conversion strategy, and transmitting the value of the direct current quantity to a PI (proportional integral) controller as an error signal to obtain a current instruction value under a harmonic rotating coordinate system; and converting the current instruction value into a current instruction for current instruction synthesis in a fundamental wave dq rotation coordinate system, and transmitting the current instruction in the fundamental wave dq coordinate system to the modular IP core to realize PWM modulation. The method realizes complete harmonic current frequency division control in the single-chip FPGA, and effectively improves the execution speed of a control algorithm and the real-time compensation effect of the active power filter.
Description
Technical field
This disclosure relates to field of power electronics, in particular to a kind of control of converters based on FPGA
Method and system processed.
Background technique
Demand with society to electric power is growing day by day, and a large amount of idle and non-linear equipments access power grid, thus causes each
Kind power quality problem influences load and works normally.
Active Power Filter-APF (Active Power Filter, APF) has small in size, dynamic in converters
The advantages that static properties is good is a kind of ideal harmonics restraint and reactive-load compensation equipment.The control algolithm of APF is main
Including grid phase locking, Harmonic currents detection, harmonic current tracing control, DC bus-bar voltage control etc., operand compared with
Greatly, requirement of real-time is high.Current APF mostly uses digital signal processor (Digital Signal Porcessor, DSP)
As processor, but DSP intrinsic sequential instructions executive mode and program interrupt execution mechanism, constrain digital control system
The control algolithm of system executes speed, influences the real-time compensation effect of APF.
It should be noted that information is only used for reinforcing to the background of the disclosure disclosed in above-mentioned background technology part
Understand, therefore may include the information not constituted to the prior art known to persons of ordinary skill in the art.
Summary of the invention
The control method and system for being designed to provide a kind of converters based on FPGA of the disclosure,
And then one or more is overcome the problems, such as caused by the limitation and defect due to the relevant technologies at least to a certain extent.
According to one aspect of the disclosure, a kind of control method of converters based on FPGA is provided, is wrapped
It includes:
Modular i P core construction step sets the IP core based on FPGA to according to preset function core building complexity
Multi-stage module IP kernel；
Current instruction value generation step, according to synchronous rotating angle strategy by load harmonic current and active electric power
The compensation current differential of filter output is transformed to DC quantity, and the value of the DC quantity is delivered to PI as error signal
Controller obtains the current instruction value under harmonic wave rotating coordinate system；
Pre-control instructs generation step, and the current instruction value is converted to the electric current under fundamental wave dq rotating coordinate system and is referred to
Instruction synthesis is enabled and carried out, the current-order under fundamental wave dq coordinate system is delivered to the modular i P and verifies existing PWM modulation.
In a kind of exemplary embodiment of the disclosure, the modular i P core construction step includes:
Three-level parametrization IP kernel is set by IP kernel according to preset function core building complexity；Wherein:
First order module includes: at least one of basic operation module, trigonometric table module, counter, decoder
Module；
Second level module is built according to first order module, including PI controller, low-pass filter, coordinate transform mould
At least one of in block, PWM modulation module；
Third level module, by calling first order module and second level module to control closed loop control module, the closed loop control
Molding block include voltage and current double closed-loop, phaselocked loop, in harmonic current control module at least one of.
In a kind of exemplary embodiment of the disclosure, when the modular i P core construction step further includes arithmetic element
Sequence set-up procedure:
Timing is calculated according to finite states machine control, is adjusted by the time-sharing multiplex to basic processing unit to operation list
First timing.
In a kind of exemplary embodiment of the disclosure, the modular i P core construction step further includes control strategy tune
Synchronizing is rapid:
Control strategy execution sequence in the IP kernel based on FPGA includes:
AD sampling processing reads sampled data and controls sampled data calibration, phaselocked loop, DC bus-bar voltage harmonious
The comprehensive tactful parallel execution of tabling look-up of wave trigonometric function, odd harmonic current control is parallel, current-order is comprehensive, PWM modulation.
In a kind of exemplary embodiment of the disclosure, the modular i P core construction step further includes based on FPGA's
Multiplication of decimals operation set-up procedure:
It determines the smallest decimal quantization digit, binary quantization processing is carried out to decimal multiplier；
Binary product is arrived into decimal progress multiplying after quantization；
According to the rightmost side position the 0th of the binary product, using binary quantization times numerical digit as starting point, with IP kernel number
It is length according to interface digit, binary value is intercepted, as FPGA multiplication result.
In a kind of exemplary embodiment of the disclosure, the current instruction value generation step further include:
Control low-pass filter filters out load harmonic current and the compensation electric current of Active Power Filter-APF output makes the difference transformation
DC quantity in of ac；
It is delivered to PI controller using the value of DC quantity as error signal, the electric current obtained under harmonic wave rotating coordinate system refers to
Enable value.
In a kind of exemplary embodiment of the disclosure, the pre-control instructs generation step further include:
When the current instruction value is converted to progress current-order synthesis under fundamental wave dq rotating coordinate system, work as n
Subharmonic is positive sequence harmonic, by harmonic wave rotating coordinate system to the transformation matrix of fundamental wave dq rotating coordinate system
Are as follows:
When nth harmonic is Negative sequence harmonic, by harmonic wave rotating coordinate system to the transformation matrix of fundamental wave dq rotating coordinate system are as follows:
In one aspect of the present disclosure, a kind of control system of converters based on FPGA, feature are provided
It is, the system comprises:
Modular i P core constructs module, for setting the IP kernel based on FPGA according to preset function core building complexity
It is set to Multi-stage module IP kernel；
Current instruction value generation module, for according to synchronous rotating angle strategy by load harmonic current with it is active
The compensation current differential of electric-power filter output is transformed to DC quantity, and conveys the value of the DC quantity as error signal
To PI controller, the current instruction value under harmonic wave rotating coordinate system is obtained；
Pre-control directive generation module carries out under fundamental wave dq rotating coordinate system for being converted to the current instruction value
Current-order under fundamental wave dq coordinate system is delivered to the modular i P and verifies existing base by the comprehensive current-order of current-order
In the control of the converters of FPGA.
The control method for the converters based on FPGA that the disclosure provides is constructed according to preset function core
The IP kernel based on FPGA is set Multi-stage module IP kernel by complexity；It will be loaded according to synchronous rotating angle strategy humorous
Wave electric current and the compensation current differential of Active Power Filter-APF output are transformed to DC quantity, and using the value of the DC quantity as
Error signal is delivered to PI controller, obtains the current instruction value under harmonic wave rotating coordinate system；The current instruction value is converted
It is to carry out the comprehensive current-order of current-order under fundamental wave dq rotating coordinate system, the current-order under fundamental wave dq coordinate system is defeated
It send to the modular i P and verifies the control of the existing converters based on FPGA.On the one hand, the disclosure is in monolithic FPGA
In realize complete APF harmonic current frequency dividing control, on the other hand, also promotion control algolithm executes speed and active electricity
The real-time compensation effect of force filter.
It should be understood that above general description and following detailed description be only it is exemplary and explanatory, not
The disclosure can be limited.
Detailed description of the invention
It is described in detail its example embodiment by referring to accompanying drawing, the above and other feature and advantage of the disclosure will become
It obtains more obvious.
Fig. 1 shows the controlling party of the converters based on FPGA according to one exemplary embodiment of the disclosure
The flow chart of method；
Fig. 2 shows the harmonic currents based on harmonic synchronous rotating coordinate system according to the disclosure one exemplary embodiment
The schematic block diagram of frequency dividing control model；
Fig. 3 is diagrammatically illustrated to be locked according to single synchronous reference coordinate system three-phase digital of one exemplary embodiment of the disclosure
Phase ring control block diagram；
Fig. 4 diagrammatically illustrates the schematic diagram of the parametrization PI controller IP kernel according to one exemplary embodiment of the disclosure；
Fig. 5 diagrammatically illustrates the schematic diagram of the power electronics three-level IP kernel bank according to one exemplary embodiment of the disclosure；
Fig. 6 A-6B diagrammatically illustrates the data quantization digit and data precision according to one exemplary embodiment of the disclosure
And the relational graph of FPGA resource expense；
Fig. 7 diagrammatically illustrates Clark under the parallel schema according to one exemplary embodiment of the disclosure and converts IP core hardware
Structure chart；
Fig. 8, which is shown, converts IP kernel serial arithmetic optimization schematic diagram according to the Clark of one exemplary embodiment of the disclosure；
Fig. 9 diagrammatically illustrates the three-phase phase-locked loop hardware structure diagram according to one exemplary embodiment of the disclosure；
Figure 10 is diagrammatically illustrated to be controlled according to the basic processing unit time-sharing multiplex of one exemplary embodiment of the disclosure
Device；
Figure 11 diagrammatically illustrates the APF control strategy execution sequence and execution according to one exemplary embodiment of the disclosure
Time distribution map；
Figure 12 shows the control system of the converters based on FPGA according to one exemplary embodiment of the disclosure
System figure.
Specific embodiment
Example embodiment is described more fully with reference to the drawings.However, example embodiment can be real in a variety of forms
It applies, and is not understood as limited to embodiment set forth herein；On the contrary, these embodiments are provided so that the disclosure will comprehensively and
Completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.The identical appended drawing reference table in figure
Show same or similar part, thus repetition thereof will be omitted.
In addition, described feature, structure or characteristic can be incorporated in one or more implementations in any suitable manner
In example.In the following description, many details are provided to provide and fully understand to embodiment of the disclosure.However,
It will be appreciated by persons skilled in the art that can with technical solution of the disclosure without one in the specific detail or
It more, or can be using other methods, constituent element, material, device, step etc..In other cases, be not shown in detail or
Known features, method, apparatus, realization, material or operation are described to avoid fuzzy all aspects of this disclosure.
Block diagram shown in the drawings is only functional entity, not necessarily must be corresponding with physically separate entity.
I.e., it is possible to realize these functional entitys using software form, or these are realized in the module of one or more softwares hardening
A part of functional entity or functional entity, or in heterogeneous networks and/or processor device and/or microcontroller device in fact
These existing functional entitys.
In this exemplary embodiment, it provides firstly a kind of based on FPGA (Field-Programmable Gate
Array, field programmable gate array) converters control method, this method can be applied to FPGA, refer to
Shown in Fig. 1, the control method for being somebody's turn to do the converters based on FPGA be may comprise steps of:
Modular i P core construction step S110 constructs complexity for the IP kernel based on FPGA according to preset function core
(Intellectual Property Core, IP core) is set as Multi-stage module IP kernel；
Current instruction value generation step S120, according to synchronous rotating angle strategy by load harmonic current with it is active
The compensation current differential of electric-power filter output is transformed to DC quantity, and conveys the value of the DC quantity as error signal
To PI controller, the current instruction value under harmonic wave rotating coordinate system is obtained；
Pre-control instructs generation step S130, and the current instruction value is converted to and is carried out under fundamental wave dq rotating coordinate system
Current-order under fundamental wave dq coordinate system is delivered to the modular i P and verifies existing base by the comprehensive current-order of current-order
In the control of the converters of FPGA.
The control method for the converters based on FPGA that the disclosure provides is constructed according to preset function core
The IP kernel based on FPGA is set Multi-stage module IP kernel by complexity；It will be loaded according to synchronous rotating angle strategy humorous
Wave electric current and the compensation current differential of Active Power Filter-APF output are transformed to DC quantity, and using the value of the DC quantity as
Error signal is delivered to PI controller, obtains the current instruction value under harmonic wave rotating coordinate system；The current instruction value is converted
It is to carry out the comprehensive current-order of current-order under fundamental wave dq rotating coordinate system, the current-order under fundamental wave dq coordinate system is defeated
It send to the modular i P and verifies the control of the existing converters based on FPGA.On the one hand, the disclosure is in monolithic FPGA
In realize complete harmonic current frequency dividing control, on the other hand, also promotion control algolithm executes speed and active electric power
The real-time compensation effect of filter.
In modular i P core construction step S110, can construct complexity according to preset function core will be based on FPGA
IP kernel be set as Multi-stage module IP kernel.
In exemplary embodiment of the invention, the modular i P core construction step includes:
Three-level parametrization IP kernel is set by IP kernel according to preset function core building complexity；Wherein:
First order module includes: at least one of basic operation module, trigonometric table module, counter, decoder
Module；
Second level module is built according to first order module, including PI controller, low-pass filter, coordinate transform mould
At least one of in block, PWM modulation module；
Third level module, by calling first order module and second level module to control closed loop control module, the closed loop control
Molding block include voltage and current double closed-loop, phaselocked loop, in harmonic current control module at least one of.
In exemplary embodiment of the invention, by taking the control strategy of the converters such as APF as an example, use is whole
The design method of body theoretically can preferably be optimized hardware the utilization of resources by the global optimization of algorithm, but greatly
Increase design difficulty, and be unfavorable for debugging.Using modular design method, veritification is designed to single IP kernel
Card, then complete control strategy is realized in such a way that top layer calls, it can simplify design cycle, improve design efficiency.
The characteristics of according to converters, the division herein for module follow following basic principle: fully functional
Property and independence.The input and output of module will have specific meaning, and each intermodule at the same level avoids Function Coupling, to reduce mould
Block unnecessary wasting of resources when called.
According to control block diagram, three-phase phase-locked loop can be divided into four main modulars: Clarke converts IP kernel, Park becomes
Change IP kernel, PI controller IP kernel and integrator IP kernel.It is divided by module, the control task of control block diagram is decomposed multiple sons
Task.
The design of FPGA is substantially hardware design, the software design scheme compared to DSP, the specificity of hardware design
Stronger, the parameter changed in algorithm can be directly changed the hardware configuration that final design is presented.In order to have dedicated hardware units
There is versatility, to adapt to different control parameter and data bit width, the data bit width of variable element and IP core is designed as
GENERIC type, when IP kernel is called, setting parameter list can realize the reconstruct to its hardware configuration, in hardware design
The function that similar software function calls is realized under system.
The parametrization IP kernel of design is classified according to the complexity that its function core is constituted, establishes three-level parametrization
Shown in IP kernel bank.The first order is basic module, including basic operation module, trigonometric table module, counter, decoder etc.；
Second level module is built by first order module, including common PI controller, low-pass filtering in converters
Device, coordinate transformation module, PWM modulation module etc.；The third level is control loop, by calling the second level and first order module real
Now more complete closed loop control module such as voltage and current double closed-loop, phaselocked loop, harmonic current control module etc..Final design
The only parametrization IP kernel needed for top layer example, the high real-time power electronics based on FPGA is realized with the mode to play with building blocks
Converter numerical control system.
In exemplary embodiment of the invention, the modular i P core construction step further includes the decimal based on FPGA
Operation set-up procedure:
It determines the smallest decimal quantization digit, binary quantization processing is carried out to decimal multiplier；
Binary product is arrived into decimal progress multiplying after quantization；
According to the rightmost side position the 0th of the binary product, using binary quantization times numerical digit as starting point, with IP kernel number
It is length according to interface digit, binary value is intercepted, as FPGA multiplication result.
In exemplary embodiment of the invention, the modular i P core construction step further includes arithmetic element timing tune
Synchronizing is rapid:
Timing is calculated according to finite states machine control, is adjusted by the time-sharing multiplex to basic processing unit to operation list
First timing.
In exemplary embodiment of the invention, the modular i P core construction step further includes control strategy adjustment step
It is rapid:
Control strategy execution sequence in the IP kernel based on FPGA includes:
AD sampling processing reads sampled data and controls sampled data calibration, phaselocked loop, DC bus-bar voltage harmonious
The comprehensive tactful parallel execution of tabling look-up of wave trigonometric function, odd harmonic current control is parallel, current-order is comprehensive, PWM modulation.It is excellent
Selection of land, odd harmonic are ± 1 subharmonic of 6k.
In exemplary embodiment of the invention, control strategy carries out module division and is designed respectively, and table 1 is packet
All main IP kernels including A/D chip controlling of sampling are included, and its execute the time.The IP kernel execution time can pass through the shape of state machine
State number is calculated with working frequency.
Table 1APF controls the main IP kernel used
Figure 11 is the execution sequence and execution time distribution map of APF control strategy in FPGA, is from left to right control in figure
Strategy executes sequence, is sampled by AD to completion SVPWM modulation and needs 13.28 μ s altogether.When the overtone order increase of compensation, only
Harmonic current control IP kernel need to be increased parallel, and increase state of tabling look-up in harmonic wave trigonometric function look-up table IP kernel, according to increase
Compensation harmonic number increase additional calculation number in current-order integration module.Due to trigonometric function table lookup operation and directly
The parallel execution of bus piezoelectric voltage control is flowed, and the latter is far longer than table lookup operation at the execution time, therefore looks into a certain range increase
Tabular order number not will increase the additional calculating time.In the comprehensive IP kernel of current-order, additional calculation of every increase needs
Increase by two states to state machine, under 50MHz clock, increased computing relay is only 40ns.
The time point (time point for opening AD sampling) for calculating and starting is reasonably selected in carrier cycle, to greatest extent
Reduce system delay.Start time selection is calculated as shown in figure 4, the system frequency of FPGA used herein is 50MHz, system
Switching frequency is 20kHz, and the up-down counter that carrier wave counter is 0~1250 updates PWM in carrier wave zero point.By control strategy
Calculating time conversion be system clock cycle, then complete to calculate 664 clock cycle of total needs, for guarantee PWM update not
Can be delayed a carrier cycle, and the limit moment for calculating beginning is that carrier wave subtracts and counts up to 1250-664=586, due to each mould
The execution time of block calculates and only calculates sequence circuit part, and the time delay of pure combinational logic part is difficult to accurately estimate, together
When AD sampling section time not fully controlled by FPGA, therefore there are foots in the selection of zero-computing time for the disclosure
Enough allowances start control strategy when carrier wave counter subtracts count value to 800 and calculate, then the practical calculating frequency of system can be with
Reach 62.5kHz.
It, can be electric by load harmonic according to synchronous rotating angle strategy in current instruction value generation step S120
Stream and the compensation current differential of Active Power Filter-APF output are transformed to DC quantity, and using the value of the DC quantity as error
Signal is delivered to PI controller, obtains the current instruction value under harmonic wave rotating coordinate system.
In exemplary embodiment of the invention, it is assumed that load-side is six pulse wave rectifier circuits, is contained only in load current
± 1 subharmonic of 6k.Fundamental current can be expressed as
According to fundamental current expression formula, the mathematic(al) representation of ± 1 subharmonic of 6k can be obtained respectively, 6k+1 subharmonic
Mathematic(al) representation expression formula is
6k-1 subharmonic expression formula is
T3s/2rIt is fundamental wave by abc rest frame to the transformation matrix of dq rotating coordinate system
In formula
Transformation matrix of the harmonic wave by abc rest frame to dq rotating coordinate system can similarly be derived.
When nth harmonic be positive sequence harmonic, nth harmonic electric current by abc rest frame to dq rotating coordinate system transformation square
Battle array be
When nth harmonic be positive sequence harmonic, nth harmonic electric current by abc rest frame to dq rotating coordinate system transformation square
Battle array be
After the coordinate transform for carrying out step S110 after the compensation electric current of load current and APF output is made the difference, low pass is controlled
Filter filters out load harmonic current and the compensation electric current of Active Power Filter-APF output makes the difference and synchronized rotating coordinate transformation
Of ac in total current afterwards；It is delivered to PI controller using the value of DC quantity as error signal, obtains harmonic wave rotating coordinate system
Under current instruction value.
In pre-control instruction generation step S130, the current instruction value can be converted to fundamental wave dq rotational coordinates
System is lower to carry out the comprehensive current-order of current-order, and the current-order under fundamental wave dq coordinate system is delivered to SVPW modulation module
The control of converters of the IP kernel realization based on FPGA.
When the current instruction value is converted to progress current-order synthesis under fundamental wave dq rotating coordinate system, when n subharmonic
For positive sequence harmonic, by harmonic wave rotating coordinate system to the transformation matrix of fundamental wave dq rotating coordinate system are as follows:
When nth harmonic is positive sequence harmonic, the transformation matrix by harmonic wave rotating coordinate system to fundamental wave dq rotating coordinate system is
When nth harmonic is Negative sequence harmonic, the transformation matrix by harmonic wave rotating coordinate system to fundamental wave dq rotating coordinate system is
Based on above-mentioned derivation, the harmonic current frequency dividing control block diagram based on harmonic synchronous rotating coordinate system is as shown in Fig. 2.
Consist of two parts: a DC bus-bar voltage and fundamental current control ring and one group of harmonic current control.DC voltage control
Ring and fundamental current control ring are responsible for stable DC side voltage and fundamental current is stablized, and harmonic current control ring tracing control is each
Subharmonic current.
It is specifically described below in conjunction with attached drawing, and by taking the design of three-phase digital phaselocked loop as an example.
Fig. 3 is the control block diagram of single synchronous rotating frame phaselocked loop, and according to the control block diagram, three-phase phase-locked loop can be with
Be divided into four main modulars: Clarke converts IP kernel, Park transformation IP kernel, PI controller IP core and integrator IP kernel.By
Module divides, and the control task of Fig. 3 control block diagram is decomposed multiple subtasks.
In order to make dedicated hardware units that there is versatility, to adapt to different control parameter and data bit width, by variable ginseng
Several data bit widths with IP kernel are designed as GENERIC type, and when IP kernel is called, setting parameter list can be realized to it
The function that similar software function calls is realized in the reconstruct of hardware configuration under hardware design system.
Fig. 4 is the parametrization PI controller IP kernel designed herein.The parametrization IP kernel of design is constituted according to its function core
Complexity classify, establish three-level parametrization IP kernel bank it is as shown in Figure 5.The first order is basic module, including is transported substantially
Calculate module, trigonometric table module, counter, decoder etc.；Second level module is built by first order module, including electricity
Common PI controller, low-pass filter, coordinate transformation module, PWM modulation module etc. in power electronic converter；The third level is
Control loop is closed by calling the second level and first order module to realize that more complete closed loop control module such as voltage and current is double
Ring, phaselocked loop, harmonic current control module etc..Final design can the only parametrization IP kernel needed for top layer example, with taking
The mode of building blocks realizes the high real-time converters numerical control system based on FPGA.
In the control strategy of converters, often there is the multiplying containing decimal, citing is had below
Body illustrates to obtain operation to multiplication of decimals in FPGA.
If alternating voltage sample range is ± 500V, corresponding 16 bit AD sample value ranges -32767~32767, it is assumed that when
Preceding voltage 1V, by the value withMultiplication is done, as a result should be
It is right firstQuantification treatment is carried out, as shown in formula (9), Q isValue after quantization has symbol binary system with 16
Number is expressed as 0110111011011010.
Data after quantization are multiplied with AD sampled value.When actual voltage value be 1V, be according to above-mentioned relation AD sampled value
0000000001000010,65 are decimally expressed as,It is expressed as
R=Q × 65=1844570 (10)
For binary multiplication, it is the sum of number that the data bits of product, which is equal to two multipliers, therefore R is had symbol with 32
Number binary number representation is 00000000000111000010010101011010.In order to guarantee the data bits after calculating
Unanimously, it is therefore desirable to multiplication result is truncated, 16 in 32 results are taken.Due toQuantizing process amplified
214, cause product to be also exaggerated identical multiple, with binary number rightmost side position the 0th, take the 14th~30 data
00000000001110000 as a result, decimal representation is 112, corresponding actual value 1.709, error 1.3%.With quantization
The increase of digit, the i.e. increase of amplification factor calculate error and are gradually reduced, but the resource occupied is consequently increased.
Fig. 6 A-6B shows the relationship of data quantization digit and data precision and FPGA resource expense, such as Fig. 6 A-6B institute
Therefore data bits minimization principle will be followed in decimal quantization by showing: selecting most under the premise of data precision is met the requirements
Small quantization digit, to save FPGA resource expense.
It is substantially to exchange calculating speed for by hardware logic resource that FPGA efficient parallel, which executes algorithm,.
APF harmonic current frequency dividing control strategy is complex, to fully consider the distribution benefit of FPGA resource in the design
With.By rationally designing the serial parallel relationship of each section in control strategy, time-sharing multiplex is carried out to hardware resource, utilization is limited
Hardware logic Resource Design go out efficient nonshared control unit.Equilibrium considers FPGA hardware resource cost and calculating speed, herein
Following principle is followed in algorithm optimization: in the same module, as far as possible use serial executive mode, top layer call when according to
The executive mode of the demand selection serial or parallel of arithmetic speed.
Still by taking the whole design of Clarke conversion module and phaselocked loop in three-phase digital phaselocked loop as an example, illustrate algorithm
Optimization process carries out.Need to carry out 5 multiplication, 3 subtractions according to formula (11) Clark transformation.
It carries out needing to calculate 3 multiplication, 2 subtractions and 1 sub-addition such as formula (12) after abbreviation by merging similar terms.
For two's complement arithmetic, multiplyIt can be replaced, can directly be given up in practical operation minimum with right-shift operation
Sign bit simultaneously is mended in highest order in position.By algorithm optimization, Design of Hardware Architecture of the Clark module in FPGA is as shown in Figure 7
Clark converts IP kernel hardware structure diagram under parallel schema, needs 2 multipliers, 2 subtracters and 1 adder.
On the basis of Fig. 7 hardware configuration, is controlled and calculated using finite state machine (Finite-state machine, FSM)
Timing is further reduced resource occupation by the time-sharing multiplex to basic processing unit.The Clark as shown in Fig. 8 converts IP kernel
Serial arithmetic optimization, step1 and step2 share a subtracter, and step2 and step3 share a multiplier.After optimization
Clarke conversion module only needs to occupy the hardware resource of 1 multiplier, 1 adder and 1 subtracter.
Remaining IP kernel is designed based on above-mentioned algorithm optimization mode, and is adjusted in three-phase phase-locked loop IP kernel top layer
With it is as shown in Figure 9 to construct complete three-phase phase-locked loop IP kernel structure by the way of playing with building blocks.Each IP core, which has, to be had been calculated
It at flag bit flag, is controlled by FSM, is completed when calculating, state machine is set ' 1 ' and kept for two clock cycle, subsequent adjacent
IP kernel carries out uninterrupted scanning to the flag bit and reads, and receives and flag bit mark is set ' 1 ', and starting state after flag=' 1 '
The operation process of machine.
Basic processing unit time-sharing multiplex controller is a multiple selector in Fig. 9, and structure is as shown in Figure 10.It is logical
The position for crossing mark, which is selected, distributes to each IP kernel for the right to use of basic processing unit.By algorithm optimization, entire phase-locked loop module is only
Using 1 adder, 1 subtracter and 1 multiplier, under 50MHz system clock used herein, the time is calculated only
For 1100ns.
It should be noted that although describing each step of method in the disclosure in the accompanying drawings with particular order,
It is that this does not require that or implies must execute these steps in this particular order, or have to carry out shown in whole
Step is just able to achieve desired result.Additional or alternative, it is convenient to omit multiple steps are merged into one by certain steps
Step executes, and/or a step is decomposed into execution of multiple steps etc..
In addition, in this exemplary embodiment, additionally providing a kind of control system of converters based on FPGA
System.Referring to Fig.1 shown in 2, it is somebody's turn to do the control system of the converters based on FPGA, may include the building of modular i P core
Module 1201, current instruction value generation module 1202 and pre-control directive generation module 1203, in which:
Modular i P core constructs module 1201, for constructing complexity for the IP based on FPGA according to preset function core
Core is set as Multi-stage module IP kernel；
Current instruction value generation module 1202, for according to synchronous rotating angle strategy by load harmonic current with
The compensation current differential of Active Power Filter-APF output is transformed to DC quantity, and using the value of the DC quantity as error signal
It is delivered to PI controller, obtains the current instruction value under harmonic wave rotating coordinate system；
Pre-control directive generation module 1203, for being converted to the current instruction value under fundamental wave dq rotating coordinate system
The comprehensive current-order of current-order is carried out, the current-order under fundamental wave dq coordinate system is delivered to SVPWM modulation module.
Among the above respectively the detail of the control device module of the converters based on FPGA corresponding
It is described in detail in the control method of converters based on FPGA, therefore details are not described herein again.
It should be noted that although being referred to the control system of the converters based on FPGA in the above detailed description
Several modules or unit of system, but this division is not enforceable.In fact, according to embodiment of the present disclosure, on
Two or more modules of text description or the feature and function of unit can embody in a module or unit.Instead
It, the feature and function of an above-described module or unit can be by multiple modules or unit with further division
To embody.
Person of ordinary skill in the field it is understood that various aspects of the invention can be implemented as system, method or
Program product.Therefore, various aspects of the invention can be embodied in the following forms, it may be assumed that complete hardware embodiment, complete
The embodiment combined in terms of full software implementation (including firmware, microcode etc.) or hardware and software, can be referred to as here
For circuit, " module " or " system ".
By the description of above embodiment, those skilled in the art is it can be readily appreciated that example embodiment described herein
It can also be realized in such a way that software is in conjunction with necessary hardware by software realization.Therefore, according to disclosure reality
The technical solution for applying example can be embodied in the form of software products, which can store non-volatile at one
In storage medium (can be CD-ROM, USB flash disk, mobile hard disk etc.) or on network, including some instructions are so that a calculating is set
Standby (can be personal computer, server, terminal installation or network equipment etc.) executes the side according to the embodiment of the present disclosure
Method.
In addition, above-mentioned attached drawing is only the schematic theory of processing included by method according to an exemplary embodiment of the present invention
It is bright, rather than limit purpose.It can be readily appreciated that the time that above-mentioned processing shown in the drawings did not indicated or limited these processing is suitable
Sequence.In addition, be also easy to understand, these processing, which can be, for example either synchronously or asynchronously to be executed in multiple modules.
Those skilled in the art after considering the specification and implementing the invention disclosed here, will readily occur to the disclosure
Other embodiments.This application is intended to cover any variations, uses, or adaptations of the disclosure, these modifications, purposes or
Person's adaptive change follows the general principles of this disclosure and including the undocumented common knowledge in the art of the disclosure
Or conventional techniques.The description and examples are only to be considered as illustrative, and the true scope and spirit of the disclosure are wanted by right
It asks and points out.
It should be understood that the present disclosure is not limited to the precise structures that have been described above and shown in the drawings, and
And various modifications and changes may be made without departing from the scope thereof.The scope of the present disclosure is only limited by the attached claims.
Claims (8)
1. a kind of control method of the converters based on on-site programmable gate array FPGA, which is characterized in that described
Method is applied to FPGA, comprising:
The intellectual property IP kernel based on FPGA is arranged according to preset function core building complexity for modular i P core construction step
For Multi-stage module IP kernel；
Current instruction value generation step, according to synchronous rotating angle strategy by load harmonic current and Active Power Filter-APF
The compensation current differential of output is transformed to DC quantity, and is delivered to PI controller for the value of the DC quantity as error signal,
Obtain the current instruction value under harmonic wave rotating coordinate system；
Pre-control instructs generation step, and it is comprehensive that the current instruction value is converted to progress current-order under fundamental wave dq rotating coordinate system
Current-order under fundamental wave dq coordinate system is delivered to modular i P and verifies existing PWM modulation by the current-order of conjunction.
2. the method as described in claim 1, which is characterized in that the modular i P core construction step includes:
Three-level parametrization IP kernel is set by IP kernel according to preset function core building complexity；Wherein:
First order module includes: basic operation module, trigonometric table module, counter, at least one module in decoder；
Second level module is built according to first order module, including PI controller, low-pass filter, coordinate transformation module, PWM
At least one of in modulation module；
Third level module, by calling first order module and second level module to control closed loop control module, the closed-loop control mould
Block include voltage and current double closed-loop, phaselocked loop, in harmonic current control module at least one of.
3. the method as described in claim 1, which is characterized in that when the modular i P core construction step further includes arithmetic element
Sequence set-up procedure:
Timing is calculated according to finite states machine control, the operation of arithmetic element is adjusted by the time-sharing multiplex to basic processing unit
Timing.
4. the method as described in claim 1, which is characterized in that the modular i P core construction step further includes control strategy tune
Synchronizing is rapid:
Control strategy execution sequence in the IP kernel based on FPGA includes:
AD sampling processing reads sampled data and to sampled data calibration, phaselocked loop, DC bus-bar voltage control and harmonic wave triangle
Function Synthesis is tabled look-up, and strategy executes parallel, odd harmonic current control is parallel, current-order is comprehensive, pulsewidth PWM modulation.
5. the method as described in claim 1, which is characterized in that the modular i P core construction step further include:
It determines the smallest decimal quantization digit, binary quantization processing is carried out to decimal multiplier；
Binary product is arrived into decimal progress multiplying after quantization；
According to the rightmost side position the 0th of the binary product, using binary quantization times numerical digit as starting point, with IP kernel data-interface
Digit is length, binary value is intercepted, as FPGA multiplication result.
6. the method as described in claim 1, which is characterized in that the current instruction value generation step further include:
Control low-pass filter filters out load harmonic current and the compensation electric current of Active Power Filter-APF output makes the difference and passes through same
Walk the of ac in the DC quantity of rotating coordinate transformation；
It is delivered to PI controller using the value of DC quantity as error signal, obtains the current instruction value under harmonic wave rotating coordinate system.
7. the method as described in claim 1, which is characterized in that the pre-control instructs generation step further include:
When the current instruction value is converted to progress current-order synthesis under fundamental wave dq rotating coordinate system, work as n
Subharmonic is positive sequence harmonic, by harmonic wave rotating coordinate system to the transformation matrix of fundamental wave dq rotating coordinate system are as follows:
When nth harmonic is Negative sequence harmonic, by harmonic wave rotating coordinate system to the transformation matrix of fundamental wave dq rotating coordinate system are as follows:
8. a kind of control system of the converters based on FPGA, which is characterized in that the system comprises:
Modular i P core constructs module, for setting more for the IP kernel based on FPGA according to preset function core building complexity
Grade modular i P core；
Current instruction value generation module, for being filtered load harmonic current and active electric power according to synchronous rotating angle strategy
The compensation current differential of wave device output is transformed to DC quantity, and is delivered to PI control for the value of the DC quantity as error signal
Device obtains the current instruction value under harmonic wave rotating coordinate system；
Pre-control directive generation module refers to for the current instruction value to be converted to progress electric current under fundamental wave dq rotating coordinate system
Comprehensive current-order is enabled, the current-order under fundamental wave dq coordinate system is delivered to the modular i P and verifies existing PWM modulation.
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| CN113568339A (en) * | 2021-07-15 | 2021-10-29 | 许继电气股份有限公司 | Converter fixed time delay control method and device |
| CN113964848A (en) * | 2021-12-20 | 2022-01-21 | 昆山帝森华途工业物联网科技有限公司 | Reactive current extraction module of APF control system |
| CN114879564A (en) * | 2022-05-13 | 2022-08-09 | 西安交通大学 | FPGA-based distributed closed-loop control method for universal power electronic module |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111064537A (en) * | 2019-12-11 | 2020-04-24 | 中国电子科技集团公司第三十研究所 | High-speed interface communication method based on FPGA (field programmable Gate array) chips of different manufacturers |
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| CN113568339A (en) * | 2021-07-15 | 2021-10-29 | 许继电气股份有限公司 | Converter fixed time delay control method and device |
| CN113568339B (en) * | 2021-07-15 | 2023-03-21 | 许继电气股份有限公司 | Converter fixed time delay control method and device |
| CN113964848A (en) * | 2021-12-20 | 2022-01-21 | 昆山帝森华途工业物联网科技有限公司 | Reactive current extraction module of APF control system |
| CN113964848B (en) * | 2021-12-20 | 2022-05-31 | 昆山帝森华途工业物联网科技有限公司 | Reactive current extraction module of APF control system |
| CN114879564A (en) * | 2022-05-13 | 2022-08-09 | 西安交通大学 | FPGA-based distributed closed-loop control method for universal power electronic module |
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