CN110429129B - High-voltage groove type power semiconductor device and preparation method - Google Patents
High-voltage groove type power semiconductor device and preparation method Download PDFInfo
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- CN110429129B CN110429129B CN201910729781.0A CN201910729781A CN110429129B CN 110429129 B CN110429129 B CN 110429129B CN 201910729781 A CN201910729781 A CN 201910729781A CN 110429129 B CN110429129 B CN 110429129B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 10
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- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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Abstract
The invention relates to a power semiconductor and a preparation method thereof, in particular to a high-voltage groove type power semiconductor device and a preparation method thereof, belonging to the technical field of power semiconductor devices. The semiconductor substrate is etched to obtain a wider cell groove, after the substrate conductive polycrystalline silicon body filled in the cell groove is etched back, a positioning hole can be injected into the groove in the cell groove, the substrate conductive polycrystalline silicon body is arranged on the outer ring of the positioning hole injected into the groove, a substrate groove second conductive type doping region and a substrate second conductive type base region can be conveniently and simultaneously obtained by utilizing the positioning hole injected into the groove, the substrate groove second conductive type doping region is located under the groove bottom of the cell groove and is in contact with the groove bottom of the cell groove, and therefore the electric field of the cell groove bottom insulating gate oxide layer can be reduced, the reliability of the substrate insulating gate oxide layer is improved, the semiconductor substrate conductive type doping region is compatible with the existing process, and the controllability of the process flow is improved.
Description
Technical Field
The invention relates to a power semiconductor and a preparation method thereof, in particular to a high-voltage groove type power semiconductor device and a preparation method thereof, belonging to the technical field of power semiconductor devices.
Background
An Insulated Gate Bipolar Transistor (IGBT) combines the characteristics of a MOSFET and a BJT, and has the characteristics of gate control and low conduction voltage drop of bipolar conduction. A metal oxide field effect transistor (MOSFET), a gated unipolar conductive device.
The Trench gate (Trench gate) is formed by etching a Trench and then oxidizing and filling polycrystalline silicon, and the channel of the Trench is in the vertical direction, so that the JEFET effect can be eliminated, and the conduction voltage drop of a device is reduced; the problem that the trench gate has is that a high electric field is easy to appear at the bottom of the trench of the device, which affects the reliability of gate oxide, especially the gate oxide breakdown electric field of the silicon carbide SiC device is relatively low and the quality is not high.
As can be seen from the above description, the trench IGBT and MOSFET power devices have been widely used, however, the trench IGBT and MOSFET generally have a drawback that a high electric field occurs at the bottom of the trench, which affects the reliability of the gate oxide of the device. Particularly, in the silicon carbide trench IGBT and MOSFET, the critical breakdown electric field of the silicon carbide substrate is close to the breakdown electric field of the gate oxide, so that the gate oxide is easily disabled when the device reaches avalanche breakdown, and therefore the gate oxide must be protected to prevent the electric field from being too high.
In order to solve the problem, for an N-type IGBT device or an N-type MOSFET device, it is currently generally adopted to implant a layer of P-type doping at the bottom of a trench to reduce a high electric field at the bottom of the trench, however, the current method is a relatively narrow trench gate structure, taking a high-voltage 600V device as an example, the width of the trench is about 1.5 μm, and the depth generally has about 5 μm, which brings difficulty to the implantation at the bottom of the trench; therefore, new device structures and process methods are needed to reduce the process difficulty of forming P-type doping at the bottom of the trench and the influence on the gate oxide reliability.
As shown in fig. 1 to 6, a process flow diagram of a conventional trench type power semiconductor device, specifically,
as shown in fig. 1, an N-type semiconductor substrate 1 is provided, and a substrate trench 2 is etched in a front surface of the semiconductor substrate 1. As shown in fig. 2, implantation of P-type impurity ions and annealing are performed above the front surface of the semiconductor substrate 1 to obtain a substrate P-type base region 4 in the semiconductor substrate 1 and a substrate trench P-type doped region 3 below the bottom of the substrate trench 2.
As shown in fig. 3, an oxide layer is grown and polysilicon is filled to obtain a substrate oxide layer 5 and a substrate conductive polysilicon body 6, wherein the substrate conductive polysilicon body 6 is filled in the substrate trench 2, and the substrate conductive polysilicon body 6 is insulated and isolated from the sidewall and the bottom wall of the substrate trench 2 by the substrate oxide layer 5.
As shown in fig. 4, the substrate conductive polysilicon body 6 is etched to obtain the substrate conductive polysilicon body 6 located in the substrate trench 2. As shown in fig. 5, N-type impurity ion implantation and annealing are performed to obtain a substrate N + source region 7 located in the substrate P-type base region 4, where the substrate N + source region 7 contacts with the outer wall of the substrate trench 2. As shown in fig. 6, the steps of dielectric layer deposition, contact hole etching and front metal formation are performed to obtain a substrate metal layer 8 and a substrate insulating dielectric layer 9 covering the notch of the substrate trench 2, the substrate metal layer 8 is insulated and isolated from the substrate conductive polysilicon body 6 by the substrate insulating dielectric layer 9, and the substrate metal layer 8 is in ohmic contact with the substrate P-type base region 4 and the substrate N + source region 7.
In addition, a back structure is further disposed on the back surface of the semiconductor substrate 1, the specific form of the back structure can be rotated as required, and the required IGBT device or MOSFET device can be formed according to the difference of the back structure, which is known to those skilled in the art and will not be described herein again.
As can be seen from the above process steps, the current method for manufacturing a trench power semiconductor device has the following main defects: when the substrate trench P-type doped region 3 is prepared, since the substrate trench 2 has a relatively large aspect ratio, ion implantation must be strictly vertical, which has a very high requirement on the direction control of the ion implantation and a great process difficulty.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a high-voltage groove type power semiconductor device and a preparation method thereof, which can effectively reduce the electric field of a substrate insulating gate oxide layer at the bottom of a cellular groove, improve the reliability of the substrate insulating gate oxide layer, are compatible with the prior art, and improve the controllability of the process flow.
According to the technical scheme provided by the invention, the high-voltage groove type power semiconductor device comprises a semiconductor substrate with a first conduction type and a cellular area arranged in the central area of the semiconductor substrate, wherein cellular cells in the cellular area adopt a groove structure; the unit cell comprises a unit cell groove positioned in the semiconductor substrate;
on the cross section of the power semiconductor device, a substrate groove second conduction type doping region is arranged right below the bottom of a cell groove, and the substrate groove second conduction type doping region is in contact with the bottom of the cell groove; arranging substrate second conductive type base regions on two sides of the cellular trench, wherein the substrate second conductive type base regions are positioned above the bottom of the cellular trench and are in contact with the outer side wall of the cellular trench;
a substrate conductive polycrystalline silicon body and a substrate insulating medium layer are filled in the cell groove, the substrate insulating medium layer also covers the semiconductor substrate, and the substrate conductive polycrystalline silicon body is insulated and isolated from the side wall and the bottom wall of the cell groove through a substrate insulating gate oxide layer; and a substrate metal layer is also arranged above the semiconductor substrate, the substrate metal layer is supported on the substrate insulating medium layer, the substrate metal layer is insulated and isolated from the substrate conductive polycrystalline silicon body through the substrate insulating medium layer, and the substrate metal layer is in ohmic contact with the substrate first conductive type source region and the substrate second conductive type base region.
The substrate second conduction type base region and the substrate second conduction type doping region are the same process step layer.
The substrate insulating gate oxide layer and the substrate insulating dielectric layer are both silicon dioxide layers.
The semiconductor substrate is made of silicon or silicon carbide.
A preparation method of a high-voltage trench type power semiconductor device comprises the following steps:
step 7, selectively masking and etching the substrate insulating medium layer to obtain a medium layer contact hole penetrating through the substrate insulating medium layer;
step 8, depositing a metal layer above the front surface of the semiconductor substrate to obtain a substrate metal layer supported on a substrate insulating medium layer, wherein the substrate metal layer can be in ohmic contact with a substrate second conductive type base region and a substrate first conductive type source region through a medium layer contact hole, and the substrate metal layer is isolated from a substrate conductive polycrystalline silicon body in a cellular trench through the substrate insulating medium layer in an insulating way;
and 9, manufacturing a required device back structure on the back of the semiconductor substrate.
The substrate insulating gate oxide layer and the substrate insulating dielectric layer are both silicon dioxide layers.
The semiconductor substrate is made of silicon or silicon carbide.
In both the "first conductivity type" and the "second conductivity type", for an N-type power semiconductor device, the first conductivity type refers to an N-type, and the second conductivity type is a P-type; for a P-type power semiconductor device, the first conductivity type and the second conductivity type are opposite to the N-type power semiconductor device.
The invention has the advantages that: the semiconductor substrate is etched to obtain a wider cell groove, after the substrate conductive polycrystalline silicon body filled in the cell groove is etched back, a positioning hole can be injected into the groove in the cell groove, the substrate conductive polycrystalline silicon body is arranged on the outer ring of the positioning hole injected into the groove, a substrate groove second conductive type doping region and a substrate second conductive type base region can be conveniently and simultaneously obtained by utilizing the positioning hole injected into the groove, the substrate groove second conductive type doping region is located under the groove bottom of the cell groove and is in contact with the groove bottom of the cell groove, and therefore the electric field of the cell groove bottom insulating gate oxide layer can be reduced, the reliability of the substrate insulating gate oxide layer is improved, the semiconductor substrate conductive type doping region is compatible with the existing process, and the controllability of the process flow is improved.
Drawings
FIGS. 1 to 6 are flow charts of the detailed manufacturing process of the cell of the conventional trench type power semiconductor device, wherein
Fig. 1 is a cross-sectional view of a semiconductor substrate having a substrate trench formed therein.
Fig. 2 is a cross-sectional view of a substrate trench P-type doped region and a substrate P-type base region in a semiconductor substrate.
Fig. 3 is a cross-sectional view after filling the substrate conductive polysilicon body.
Fig. 4 is a cross-sectional view of a substrate after etching of a conductive polysilicon body.
Fig. 5 is a cross-sectional view of the resulting N + source region of the substrate.
Fig. 6 is a cross-sectional view of the substrate metal layer.
FIGS. 7-12 are flow charts of specific processes of the present invention, wherein
Fig. 7 is a cross-sectional view of the semiconductor substrate after etching a cell trench in the front side of the semiconductor substrate.
Fig. 8 is a cross-sectional view of the invention after filling the substrate conductive polysilicon body.
FIG. 9 is a cross-sectional view of the present invention after a locating hole is injected into the trench.
FIG. 10 is a cross-sectional view of a substrate trench P-type doped region and a substrate P-type base region according to the present invention.
Fig. 11 is a cross-sectional view of the present invention after obtaining a substrate N + source region.
FIG. 12 is a cross-sectional view of a metal layer of a substrate according to the present invention.
Description of the reference numerals: 1-semiconductor substrate, 2-substrate groove, 3-substrate groove P-type doping region, 4-substrate P-type base region, 5-substrate oxidation layer, 6-substrate conductive polycrystalline silicon body, 7-substrate N + source region, 8-substrate metal layer, 9-substrate insulating medium layer, 10-semiconductor substrate, 11-cell groove, 12-substrate insulating gate oxidation layer, 13-substrate conductive polycrystalline silicon body, 14-in-groove injection positioning hole, 15-substrate P-type base region, 16-substrate groove P-type doping region, 17-substrate N + source region, 18-substrate metal layer and 19-substrate insulating medium layer.
Detailed Description
The invention is further illustrated by the following specific figures and examples.
As shown in fig. 12: in order to effectively reduce the electric field of the substrate insulating gate oxide layer at the bottom of the cellular trench and improve the reliability of the substrate insulating gate oxide layer, taking an N-type trench power semiconductor device as an example, the invention comprises a semiconductor substrate 10 with an N conductive type and a cellular region arranged in the central region of the semiconductor substrate 10, wherein the cellular in the cellular region adopts a trench structure; the cell includes a cell trench 11 in a semiconductor substrate 10;
on the cross section of the power semiconductor device, a substrate groove P-type doped region 16 is arranged right below the groove bottom of the cell groove 11, and the substrate groove P-type doped region 16 is in contact with the groove bottom of the cell groove 11; substrate P-type base regions 15 are arranged on two sides of the cell groove 11, the substrate P-type base regions 15 are positioned above the groove bottom of the cell groove 11, the substrate P-type base regions 15 are in contact with the outer side wall of the cell groove 11, a substrate N + source region 17 is arranged in the substrate P-type base regions 15, and the substrate N + source region 17 is in contact with the outer side wall of the cell groove 11;
a substrate conductive polycrystalline silicon body 13 and a substrate insulating medium layer 19 are filled in the cellular trench 11, the substrate insulating medium layer 19 also covers the semiconductor substrate 10, and the substrate conductive polycrystalline silicon body 13 is insulated and isolated from the side wall and the bottom wall of the cellular trench 11 through a substrate insulating gate oxide layer 12; a substrate metal layer 18 is further arranged above the semiconductor substrate 11, the substrate metal layer 18 is supported on a substrate insulating medium layer 19, the substrate metal layer 18 is insulated and isolated from the substrate conductive polycrystalline silicon body 13 through the substrate insulating medium layer 19, and the substrate metal layer 18 is in ohmic contact with the substrate N + source region 17 and the substrate P-type base region 15.
Specifically, the semiconductor substrate 10 is made of silicon or silicon carbide, the conductivity type of the semiconductor substrate 10 is N-type for an N-type trench power semiconductor device, the conductivity type of the semiconductor substrate 10 is P-type for a P-type trench power semiconductor device, and the material type of the semiconductor substrate 10 may be selected as needed, which is well known to those skilled in the art and is not described herein again. A cell area is disposed in a central area of the semiconductor substrate 10, generally, a terminal protection area is disposed at an outer ring of the cell area, and the terminal protection area can be used to implement voltage-withstanding protection of the cell area, and a specific matching relationship between the terminal protection area and the cell area is well known to those skilled in the art and will not be described herein again. In the embodiment of the present invention, the cells in the cell area adopt a trench structure, that is, the cells include cell trenches 11, the cell trenches 11 are located in the semiconductor substrate 10, the cell trenches 11 extend vertically downward from the front surface of the semiconductor substrate 10, and the depth of the cell trenches 11 is less than the thickness of the semiconductor substrate 50.
On the cross section of the power semiconductor device, a substrate groove P-type doped region 16 is located right below the groove bottom of a cell groove 11, the width of the substrate groove P-type doped region 16 is smaller than that of the cell groove 11, the substrate groove P-type doped region 16 is in contact with the groove bottom of the cell groove 11, a substrate P-type base region 15 is located on two sides of the cell groove 11, and the substrate P-type base region 15 and the substrate P-type doped region 16 are in the same process step layer. The substrate N + source region 17 is located in the substrate P-type base region 15, the depth of the substrate N + source region 17 is smaller than that of the substrate P-type base region 15, and the substrate N + source region 17 is also in contact with the outer side wall of the cellular groove 11.
The cell trench 11 is filled with a substrate conductive polysilicon body 13 and a substrate insulating medium layer 19, the substrate insulating medium layer 19 also covers the front surface of the semiconductor substrate 10, the substrate insulating gate oxide layer 12 in the cell trench 11 corresponds to the substrate conductive polysilicon body 13, so that the substrate conductive polysilicon body 13 can be insulated and isolated from the side wall and the bottom wall of the cell trench 11 by the substrate insulating gate oxide layer 12, the substrate insulating medium layer 19 filled in the cell trench 11 is positioned in the central area of the cell trench 11, and the substrate insulating gate oxide layer 12 and the substrate insulating medium layer 19 are both silicon dioxide layers. The substrate metal layer 18 is supported on the substrate insulating medium layer 19, the substrate metal layer 18 is in ohmic contact with the substrate P-type base region 15 and the substrate N + source region 17, a source terminal of the power semiconductor device can be formed through the substrate metal layer 18, and the substrate metal layer 18 can be isolated from the substrate conductive polycrystalline silicon body 13 in the cell trench 11 through the substrate insulating medium layer 19.
As shown in fig. 7 to 12, the trench type power semiconductor device with the above structure can be prepared by the following process steps, and specifically, the preparation method of the power semiconductor device of the present invention comprises the following steps:
specifically, the material of the semiconductor substrate 10 may be silicon or silicon carbide, and after the front surface of the semiconductor substrate 10 is etched by a common technical means in the technical field, a cell trench 11 can be obtained, as shown in fig. 7; the process of preparing the cell trench 11 is well known in the art and will not be described herein.
specifically, the substrate insulating gate oxide layer 12 is a silicon dioxide layer, the substrate insulating gate oxide layer 12 can be obtained by thermal oxidation, the substrate insulating gate oxide layer 12 obtained by thermal oxidation growth covers the front surface of the semiconductor substrate 10, and the substrate insulating gate oxide layer 12 can also be obtained on the side wall and the bottom wall of the cell trench 11. By means of a conventional technical means in the technical field, the cell trench 11 in which the substrate insulating gate oxide layer 12 is grown is filled with a substrate conductive polysilicon body 13, and the substrate conductive polysilicon body 13 is further covered on the front surface of the semiconductor substrate 10, as shown in fig. 8.
specifically, the conductive polysilicon body 13 of the substrate is etched by a conventional technical means in the technical field, that is, the insulating gate oxide layer 12 of the substrate on the front surface of the semiconductor substrate 10 and the conductive polysilicon body 13 of the substrate on the front surface of the semiconductor substrate 10 are removed, and in addition, the conductive polysilicon body 13 of the substrate and the insulating gate oxide layer 12 of the substrate in the central area of the cell trench 11 are also removed, so that the intra-trench injection positioning hole 14 can be obtained in the cell trench 11, the outer ring of the intra-trench injection positioning hole 14 is the conductive polysilicon body 13 of the substrate, the bottom of the central area in the cell trench 11 can be exposed by the intra-trench injection positioning hole 14, and for the conductive polysilicon body 13 of the substrate remaining in the cell trench 11, the conductive polysilicon body 13 of the substrate in the cell trench 11 can be insulated and isolated from the side wall and the bottom wall of the cell trench 11 by the insulating gate oxide layer 12 of the substrate, that the relationship between the conductive polysilicon body 13 of the substrate in the cell trench 11 and the semiconductor substrate 10 is not affected after the positioning hole 14 is injected in the trench, as shown in fig. 9.
specifically, the implantation and annealing process of the P-type impurity ions can be performed by using the technical means and process conditions commonly used in the art, and the process of performing the implantation and annealing process of the P-type impurity ions is well known to those skilled in the art and is not described herein again. When P-type impurity ion implantation and annealing are carried out, substrate P-type base regions 15 can be obtained on two sides of the cell groove 11, meanwhile, a substrate groove P-type doped region 16 can be obtained right below the bottom of the cell groove 11 by utilizing the in-groove injection positioning hole 14, and the bottom of the cell groove 11 is contacted with the substrate groove P-type doped region 16, as shown in fig. 10. As can be seen from the above description, the cell trench 11 may have a wider width, so that the substrate trench P-type doped region 16 may be conveniently formed below the bottom of the cell trench 11 during the P-type impurity ion implantation and annealing, thereby improving the process controllability, not requiring strict control of the vertical implantation angle, and reducing the process difficulty.
specifically, the implantation and annealing of N-type impurity ions are performed by using the technical means and process conditions commonly used in the art, so that the substrate N + source region 17 can be obtained in the substrate P-type base region 15, and the substrate N + source region 17 is in contact with the outer sidewall of the cell trench 11, as shown in fig. 11.
specifically, the substrate insulating dielectric layer 19 is made of silicon dioxide, the substrate insulating dielectric layer 19 can be obtained after deposition by a common technical means in the technical field, the substrate insulating dielectric layer 19 can cover the front surface of the semiconductor substrate 10 and is filled in the positioning hole 14 in the groove of the cell groove 11, and the substrate insulating dielectric layer 19 filled in the positioning hole 14 in the groove can cover the bottom of the cell groove 11 and is connected with the substrate insulating gate oxide layer 12 in the cell groove 11 into a whole, so that the P-type doped region 16 of the substrate groove and the substrate conductive polysilicon body 13 are not affected, namely the function of the cell is not affected.
Step 7, selectively masking and etching the substrate insulating medium layer 19 to obtain a medium layer contact hole penetrating through the substrate insulating medium layer 19;
specifically, the substrate insulating dielectric layer 19 is subjected to contact hole etching by adopting a commonly used technical means in the technical field to obtain a dielectric layer contact hole positioned on the outer side of the cell trench 11, and the dielectric layer contact hole penetrates through the substrate insulating dielectric layer 19.
Step 8, depositing a metal layer above the front surface of the semiconductor substrate 10 to obtain a substrate metal layer 18 supported on a substrate insulating medium layer 19, wherein the substrate metal layer 19 can be in ohmic contact with a substrate P-type base region 15 and a substrate N + source region 17 through a medium layer contact hole, and the substrate metal layer 18 is insulated and isolated from a substrate conductive polysilicon body 13 in the cellular trench 11 through the substrate insulating medium layer 19;
specifically, a metal layer is deposited by adopting a commonly used technical means and process conditions in the technical field to obtain a substrate metal layer 18 located above the front surface of the semiconductor substrate 10, the substrate metal layer 18 is supported on a substrate insulating dielectric layer 19 and can be filled in a dielectric layer contact hole, the substrate metal layer 18 can be in ohmic contact with the substrate P-type base region 15 and the substrate N + source region 17 after being filled in the dielectric layer contact hole, the substrate metal layer 18 is insulated and isolated from the substrate conductive polysilicon body 13 through the substrate insulating dielectric layer 19, and the leading-out of the substrate conductive polysilicon body 13 is not affected, as shown in fig. 12.
And 9, manufacturing a required device back structure on the back surface of the semiconductor substrate 10.
In the embodiment of the present invention, a device back structure may be fabricated on the back of the semiconductor substrate 10 according to actual needs, and different power semiconductor devices may be obtained according to different device back structures, for example, MOSFET devices or IGBT devices may be obtained, and the specific structural form and the fabrication process of the device back structure may be the same as those in the prior art, which are well known to those skilled in the art and will not be described herein again.
Claims (2)
1. A high-voltage trench type power semiconductor device comprises a semiconductor substrate with a first conduction type and a cellular area arranged in the central area of the semiconductor substrate, wherein cellular cells in the cellular area adopt a trench structure; the cell comprises a cell groove positioned in the semiconductor substrate; the method is characterized in that:
on the cross section of the power semiconductor device, a substrate groove second conduction type doping region is arranged right below the bottom of a cell groove, and the substrate groove second conduction type doping region is in contact with the bottom of the cell groove; substrate second conduction type base regions are arranged on two sides of the cell groove, the substrate second conduction type base regions are located above the bottom of the cell groove and are in contact with the outer side wall of the cell groove, a substrate first conduction type source region is arranged in the substrate second conduction type base regions and is in contact with the outer side wall of the cell groove;
a substrate conductive polycrystalline silicon body and a substrate insulating medium layer are filled in the cell groove, the substrate insulating medium layer also covers the semiconductor substrate, and the substrate conductive polycrystalline silicon body is insulated and isolated from the side wall and the bottom wall of the cell groove through a substrate insulating gate oxide layer; a substrate metal layer is further arranged above the semiconductor substrate, the substrate metal layer is supported on a substrate insulating medium layer, the substrate metal layer is insulated and isolated from the substrate conductive polycrystalline silicon body through the substrate insulating medium layer, and the substrate metal layer is in ohmic contact with the substrate first conductive type source region and the substrate second conductive type base region;
on the cross section of the power semiconductor device, the width of the second conductive type doped region of the substrate groove is smaller than that of the cell groove;
the substrate second conductive type base region and the substrate second conductive type doping region are the same process step layer;
the substrate insulating gate oxide layer and the substrate insulating dielectric layer are both silicon dioxide layers;
the semiconductor substrate is made of silicon or silicon carbide.
2. A preparation method of a high-voltage groove type power semiconductor device is characterized by comprising the following steps:
step 1, providing a semiconductor substrate with a first conductive type, and selectively masking and etching the semiconductor substrate to obtain a cell groove on the front surface of the semiconductor substrate;
step 2, growing a substrate insulating gate oxide layer on the front surface of the semiconductor substrate, wherein the substrate insulating gate oxide layer also covers the side wall and the bottom wall of the cellular groove, and filling a substrate conductive polycrystalline silicon body in the cellular groove with the substrate insulating gate oxide layer;
step 3, etching the substrate conductive polycrystalline silicon body to obtain a substrate conductive polycrystalline silicon body positioned in the cell groove, and injecting a positioning hole into the groove in the cell groove, wherein the positioning hole in the groove penetrates through the substrate conductive polycrystalline silicon body and the substrate insulating gate oxide layer on the bottom wall of the cell groove; the substrate conductive polycrystalline silicon body in the cellular groove is insulated and isolated from the side wall and the bottom wall of the cellular groove through the substrate insulating gate oxide layer;
step 4, injecting and annealing process of second conductive type impurity ions is carried out on the front surface of the semiconductor substrate, so that a second conductive type doping region of a substrate groove and a substrate second conductive type base region are obtained in the semiconductor substrate; the substrate groove second conductive type doping region is positioned right below the cell groove bottom, the substrate groove second conductive type doping region is contacted with the cell groove bottom, the substrate second conductive type base region is positioned above the cell groove bottom, and the substrate second conductive type base region is contacted with the outer side wall of the cell groove;
on the cross section of the power semiconductor device, the width of the second conductive type doped region of the substrate groove is smaller than that of the cell groove;
step 5, injecting and annealing impurity ions of a first conduction type into the front surface of the semiconductor substrate to obtain a substrate first conduction type source region positioned in the substrate second conduction type base region, wherein the substrate first conduction type source region is contacted with the outer side wall of the cellular trench;
step 6, performing dielectric layer deposition on the front surface of the semiconductor substrate to obtain a substrate insulating dielectric layer covering the front surface of the semiconductor substrate, wherein the substrate insulating dielectric layer is also filled in the grooves of the cellular grooves and is injected into the positioning holes;
step 7, selectively masking and etching the substrate insulating medium layer to obtain a medium layer contact hole penetrating through the substrate insulating medium layer;
step 8, depositing a metal layer above the front surface of the semiconductor substrate to obtain a substrate metal layer supported on a substrate insulating medium layer, wherein the substrate metal layer can be in ohmic contact with a substrate second conductive type base region and a substrate first conductive type source region through a medium layer contact hole, and the substrate metal layer is isolated from a substrate conductive polycrystalline silicon body in a cellular trench through the substrate insulating medium layer in an insulating way;
step 9, manufacturing a required device back structure on the back of the semiconductor substrate;
the substrate insulating gate oxide layer and the substrate insulating dielectric layer are both silicon dioxide layers;
the semiconductor substrate is made of silicon or silicon carbide.
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