CN110428050B - Synapse bionic circuit for realizing diversified STDP learning rules based on memristor - Google Patents

Synapse bionic circuit for realizing diversified STDP learning rules based on memristor Download PDF

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CN110428050B
CN110428050B CN201910787215.5A CN201910787215A CN110428050B CN 110428050 B CN110428050 B CN 110428050B CN 201910787215 A CN201910787215 A CN 201910787215A CN 110428050 B CN110428050 B CN 110428050B
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analog switch
memristor
channel
module
synaptic
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CN110428050A (en
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叶葱
张鑫
夏天
刘昕怡
刘炎欣
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Hubei University
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Hubei University
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention relates to a memristor-based synaptic bionic circuit for realizing diversified STDP learning rules, which comprises an enhancement module, a suppression module and a memristor synaptic module, wherein the enhancement module and the suppression module respectively comprise two input ends and an output end, the two input ends are used for receiving a pre-neuron signal pre and a post-neuron signal post, and the output ends are connected with the memristor synaptic module; when the front neuron signal pre arrives before the rear neuron signal post, the enhancement module works, the inhibition module stops running, and the enhancement module outputs direct current levels with different widths according to the input time difference of the two signals; when the post of the rear neuron signal arrives before the pre of the front neuron signal, the suppression module works, the enhancement module stops running, and the suppression module outputs direct current levels with different widths according to the input time difference of the two signals; the memristor synapse module correspondingly inhibits the memristor conductance weight according to the direct current levels with different widths, so that corresponding parameters for realizing the STDP learning function through simulation are changed, and the application range is wide.

Description

Synapse bionic circuit for realizing diversified STDP learning rules based on memristor
Technical Field
The invention relates to the field of neural network integrated circuits, in particular to a synaptic bionic circuit for realizing diversified STDP learning rules based on memristors.
Background
With the advent of the artificial intelligence era, the data information processing amount and the computation complexity have increased dramatically, and the architecture system of the traditional computer is subject to serious challenges, so that it is urgent to realize a novel computer architecture integrating computation and storage. The human brain has an interactive complex neural network, and the highly developed parallel computing capability and learning and memory functions bring a heuristic for the development of people on brain-like chips. In the brain, neurons are the fundamental building blocks of neural networks, and synapses are the basis for connections between neurons. The change of the morphology, the function and the working efficiency of the nerve synapse, namely the synapse plasticity, plays a crucial role in information transmission, processing and storage among neurons in a nerve network, and is also an important basis of the human brain learning ability. Therefore, in order to realize a bionic chip for information transmission and storage using a neural network like the brain, it is a primary task to construct an artificial synapse circuit.
In 2008, the hewlett packard laboratory developed the first titanium oxide-based thin film memristor mock-up, confirming the inference that the professor Cai Shaotang proposed in 1971 about the existence of a fourth basic circuit element, the memristor, in addition to resistance, capacitance, inductance. Memristors have unique properties such as non-linearity, passivity, non-volatility in power down, etc. Memristors are considered ideal devices for developing artificial synapses when both ends of the memristor are subjected to the same pulse stimulus as the synapse, and the conductance change is quite similar to the change of the synaptic weight. In recent years, in order to better explain the learning and memory functions of biological brains, a pulse time dependent plasticity (STDP) learning rule is proposed, which is a mechanism for regulating the synaptic strength in the brains through presynaptic and postsynaptic pulse relative time, and is a theoretical basis for learning and self-adapting to external interference by biological neural networks. Thus, one typically utilizes memristors to build artificial synapse circuits and implement STDP learning rules. In order to explore the research of brain-like bionic chips, the predecessor realizes STDP learning rules by building a COMS integrated circuit to simulate synapses, but most synapse circuits have the problems of overlarge power consumption and severe input signal waveforms and difficult regulation. To solve these problems, researchers began to construct synaptic circuits built based on memristors and implement STDP learning functions. However, when the time difference between the pre-neuron signal and the post-neuron signal is taken as the abscissa and the conductance weight of the synapse module is taken as the ordinate, different biological neurons may work in different quadrants, for example, biological vision nerves work in the 1 st quadrant and the 3 rd quadrant, and muscle nerves work in the 1 st quadrant and the 2 nd quadrant, an artificial synapse circuit built based on the memristor is the same as a traditional COMS synapse circuit, and the problems of single simulation type and unsatisfactory fitting effect exist.
Disclosure of Invention
Aiming at the technical problems existing in the prior art, the invention provides a synaptic bionic circuit for realizing diversified STDP learning rules based on memristors. Compared with a synapse bionic circuit which can only simulate one STDP learning rule by a former person, the synapse bionic circuit provided by the invention can simulate various STDP learning functions of synapses at different parts such as a visual nerve and a muscle nerve of an organism. Meanwhile, the input signal of the circuit discards the traditional complex double spike pulse waveform which is difficult to adjust, and adopts the simple direct current pulse waveform which is easy to adjust, so that the input condition is not harsh. The circuit also has the capability of adjusting the STDP learning rule, changes the variation of the synaptic weight under the same excitation by changing the set regulation voltage, further changes the corresponding parameters for realizing the STDP learning function by simulation, can be used for simulating the STDP learning rule of the synapse under different environments, has wider application range and has larger development potential in the aspect of artificial intelligence bionic.
The technical scheme for solving the technical problems is as follows:
a synapse bionic circuit for realizing diversified STDP learning rules based on memristors, which comprises an enhancement module, a suppression module and a memristor synapse module,
The enhancement module comprises two input ends and an output end, wherein the two input ends of the enhancement module are respectively used for receiving a front neuron signal pre and a rear neuron signal post, and the output end of the enhancement module is connected with the memristive synaptic module;
the suppression module comprises two input ends and an output end, the two input ends of the suppression module are respectively used for receiving a front neuron signal pre and a rear neuron signal post, and the output end of the suppression module is connected with the memristive synaptic module;
when the pre-neuron signal pre reaches the synapse bionic circuit before the post-neuron signal post, the enhancement module works, the suppression module stops running, and the enhancement module outputs direct current levels with different widths to the memristive synapse module according to the input time difference of the pre-neuron signal pre and the post-neuron signal post;
when the post neuron signal post reaches the synapse bionic circuit before the pre neuron signal pre, the suppression module works, the enhancement module stops running, and the suppression module outputs direct current levels with different widths to the memristive synapse module according to the input time difference of the post neuron signal post and the pre neuron signal pre;
And the memristor synaptic module correspondingly inhibits the conductive weight of the memristor Rm according to the direct current levels with different widths.
On the basis of the technical scheme, the invention can be improved as follows.
Preferably, the enhancement module includes an inverter U1, a nand gate U2, an electronic switch tube P1, a resistor R1, a capacitor C1, a first analog switch, a resistor R2, a capacitor C2, a voltage comparator U5, and a resistor R3, wherein an output end of the inverter U1 is connected to one of input ends of the nand gate U2, another input end of the nand gate U2 receives the front neuron signal pre, an output end of the nand gate U2 is connected to a control electrode of the electronic switch tube P1, an input end of the electronic switch tube P1 is connected to a supply voltage, an output end of the electronic switch tube P1 is connected to one end of the first analog switch, a control end of the first analog switch receives the rear neuron signal post, another end of the first analog switch is connected to a homodromous input end of the voltage comparator U5, and an inverting input end of the voltage comparator U5 is connected to a regulation voltage V th The output end of the voltage comparator U5 is connected with the memristive synaptic module, one end of the resistor R3 is connected with the power input end of the voltage comparator U5 in parallel and connected with a power supply, and the other end of the resistor R3 is connected with the output end of the voltage comparator U5; the resistor R1 and the capacitor C1 are connected in parallel between the output end of the electronic switch tube P1 and the ground, and the resistor R2 and the capacitor C2 are connected in parallel between the same-direction input end of the voltage comparator U5 and the ground.
Preferably, the suppression module comprises an inverter U3, a NAND gate U4, and an electronic switchThe electronic switch comprises a switch tube P2, a resistor R4, a capacitor C3, a second analog switch, a resistor R5, a capacitor C4, a voltage comparator U6 and a resistor R6, wherein the input end of the inverter U3 is connected with the output end of the electronic switch tube P1, the output end of the inverter U3 is connected with one input end of a NAND gate U4, the other input end of the NAND gate U4 receives a post neuron signal, the output end of the NAND gate U4 is connected with a control electrode of the electronic switch tube P2, the input end of the electronic switch tube P2 is connected with a power supply voltage, the output end of the electronic switch tube P2 is respectively connected with the input end of the inverter U1 and one end of the second analog switch, the control end of the second analog switch receives a pre neuron signal, the other end of the second analog switch is connected with the same-direction input end of the voltage comparator U6, and the reverse input end of the voltage comparator U6 is connected with a voltage V th The output end of the voltage comparator U6 is connected with the memristive synaptic module, one end of the resistor R6 is connected with the power input end of the voltage comparator U6 in parallel and connected with a power supply, and the other end of the resistor R6 is connected with the output end of the voltage comparator U6; the resistor R4 and the capacitor C3 are connected in parallel between the output end of the electronic switch tube P2 and the ground, and the resistor R5 and the capacitor C4 are connected in parallel between the same-direction input end of the voltage comparator U6 and the ground.
Preferably, the memristive synapse module comprises a first memristive synapse sub-module, a second memristive synapse sub-module, a third memristive synapse sub-module, and a fourth memristive synapse sub-module; when the time difference deltat between the input of the pre-neuron signal pre and the post-neuron signal post to the memristive synaptic block is taken as the abscissa and the conductance weight of the memristor Rm is taken as the ordinate,
the first memristive synaptic submodule works in quadrants 1 and 3 and is used for simulating neural activity working in quadrants 1 and 3;
the second memristive synaptic submodule works in the 2 nd quadrant and the 4 th quadrant and is used for simulating the neural activity working in the 2 nd quadrant and the 4 th quadrant;
the third memristive synaptic submodule works in quadrants 1 and 2 and is used for simulating neural activity working in quadrants 1 and 2;
the fourth memristive synaptic submodule works in quadrants 3 and 4 and is used for simulating neural activity working in quadrants 3 and 4.
Preferably, the first memristive synaptic submodule comprises a memristor Rm and a third analog switch, the third analog switch comprises at least four channels, the output end of the enhancement module is connected with the control end of a first channel of the third analog switch and the control end of a fourth channel of the third analog switch, one end of the first channel of the third analog switch is connected with an external power supply, the other end of the first channel of the third analog switch is connected with the positive electrode of the memristor Rm, the negative electrode of the memristor Rm is connected with one end of the fourth channel of the third analog switch, and the other end of the fourth channel of the third analog switch is grounded; the output end of the suppression module is connected with the control end of the second channel of the third analog switch and the control end of the third channel of the third analog switch, one end of the second channel of the third analog switch is connected with an external power supply, the other end of the second channel of the third analog switch is connected with the negative electrode of the memristor Rm, the positive electrode of the memristor Rm is connected with one end of the third channel of the third analog switch, and the other end of the third channel of the third analog switch is grounded.
Preferably, the second memristive synaptic submodule includes a memristor Rm and a fourth analog switch, the fourth analog switch includes at least four channels, an output end of the enhancement module is connected with a control end of a first channel of the fourth analog switch and a control end of a fourth channel of the fourth analog switch, one end of the first channel of the fourth analog switch is connected with an external power supply, the other end of the first channel of the fourth analog switch is connected with a negative electrode of the memristor Rm, a positive electrode of the memristor Rm is connected with one end of the fourth channel of the fourth analog switch, and the other end of the fourth channel of the fourth analog switch is grounded; the output end of the suppression module is connected with the control end of the second channel of the fourth analog switch and the control end of the third channel of the fourth analog switch, one end of the second channel of the fourth analog switch is connected with an external power supply, the other end of the second channel of the fourth analog switch is connected with the positive electrode of the memristor Rm, the negative electrode of the memristor Rm is connected with one end of the third channel of the fourth analog switch, and the other end of the third channel of the fourth analog switch is grounded.
Preferably, the third memristive synaptic submodule includes a memristor Rm and a fifth analog switch, the fifth analog switch includes at least two channels, an output end of the enhancement module is connected with a control end of a first channel of the fifth analog switch, one end of the first channel of the fifth analog switch is connected with an external power supply, the other end of the first channel of the fifth analog switch is connected with an anode of the memristor Rm, and a cathode of the memristor Rm is grounded; the output end of the suppression module is connected with the control end of the second channel of the fifth analog switch, one end of the second channel of the fifth analog switch is connected with an external power supply, and the other end of the second channel of the fifth analog switch is connected with the anode of the memristor Rm.
Preferably, the fourth memristive synaptic submodule includes a memristor Rm and a sixth analog switch, the sixth analog switch includes at least two channels, an output end of the enhancement module is connected to a control end of a first channel of the sixth analog switch, one end of the first channel of the sixth analog switch is connected to an external power supply, the other end of the first channel of the sixth analog switch is connected to a negative electrode of the memristor Rm, and an positive electrode of the memristor Rm is grounded; the output end of the suppression module is connected with the control end of the second channel of the sixth analog switch, one end of the second channel of the sixth analog switch is connected with an external power supply, and the other end of the second channel of the sixth analog switch is connected with the negative electrode of the memristor Rm.
The beneficial effects of the invention are as follows: compared with a synapse bionic circuit which can only simulate one STDP learning rule by a former person, the synapse bionic circuit provided by the invention can simulate various STDP learning functions of synapses at different parts such as a visual nerve and a muscle nerve of an organism. Meanwhile, the input signal of the circuit discards the traditional complex double spike pulse waveform which is difficult to adjust, and adopts the simple direct current pulse waveform which is easy to adjust, so that the input condition is not harsh. The circuit also has the capability of adjusting the STDP learning rule, changes the variation of the synaptic weight under the same excitation by changing the set regulation voltage, further changes the corresponding parameters for realizing the STDP learning function by simulation, can be used for simulating the STDP learning rule of the synapse under different environments, has wider application range and has larger development potential in the aspect of artificial intelligence bionic.
Drawings
FIG. 1 is a schematic diagram of the overall structure of the present invention;
FIG. 2a is a block diagram of a memristive synaptic module according to a first embodiment of the present disclosure;
FIG. 2b is a block diagram of a third embodiment of a memristive synaptic module of the present disclosure;
FIG. 2c is a block diagram of a memristive synaptic module according to a second embodiment of the present disclosure;
FIG. 2d is a block diagram of a memristive synaptic module of the present disclosure;
FIG. 3 is a simulated time domain waveform diagram when four different input signals are respectively input in the first embodiment of the present invention;
FIG. 4 is a plot of the percentage change in conductance of the memristor when the input pulse time difference ΔT is changed in steps of 1 millisecond in accordance with the first embodiment of the present disclosure;
FIG. 5 is a plot of the percent change in memristor conductance when the input pulse time difference ΔT is varied in steps of 1 millisecond in a third embodiment of the present disclosure;
FIG. 6 is a plot of the percentage change in conductance of the memristor when the input pulse time difference ΔT is changed in steps of 1 millisecond in a second embodiment of the present disclosure;
FIG. 7 is a plot of the percent change in memristor conductance when the input pulse time difference ΔT is varied in steps of 1 millisecond in a fourth embodiment of the present disclosure;
FIG. 8 shows the memristor at different modulation voltages V when the input pulse time difference ΔT is changed in steps of 1 millisecond in the first embodiment of the present invention th The percentage change in conductance below.
Detailed Description
The principles and features of the present invention are described below with reference to the drawings, the examples are illustrated for the purpose of illustrating the invention and are not to be construed as limiting the scope of the invention.
The synapse bionic circuit for realizing diversified STDP learning rules based on memristors shown in fig. 1 comprises an enhancement module, a suppression module and a memristive synapse module,
the enhancement module comprises two input ends and an output end, wherein the two input ends of the enhancement module are respectively used for receiving a front neuron signal pre and a rear neuron signal post, and the output end of the enhancement module is connected with the memristive synaptic module;
the suppression module comprises two input ends and an output end, the two input ends of the suppression module are respectively used for receiving a front neuron signal pre and a rear neuron signal post, and the output end of the suppression module is connected with the memristive synaptic module;
when the pre-neuron signal pre reaches the synapse bionic circuit before the post-neuron signal post, the enhancement module works, the suppression module stops running, and the enhancement module outputs direct current levels with different widths to the memristive synapse module according to the input time difference of the pre-neuron signal pre and the post-neuron signal post;
When the post neuron signal post reaches the synapse bionic circuit before the pre neuron signal pre, the suppression module works, the enhancement module stops running, and the suppression module outputs direct current levels with different widths to the memristive synapse module according to the input time difference of the post neuron signal post and the pre neuron signal pre;
and the memristor synaptic module correspondingly inhibits the conductive weight of the memristor Rm according to the direct current levels with different widths.
As shown in FIG. 1, the enhancement module and the suppression module are mutually independent and alternately operate, and each of the enhancement module and the suppression module has two input ends and one output end, and the output ends of the two input ends are connected with the two input ends of the memristive synaptic module, so that a complete memristive synaptic bionic circuit is formed.
In this embodiment, the enhancement module includes an inverter U1, a nand gate U2, an electronic switch tube P1, a resistor R1, a capacitor C1, a first analog switch, a resistor R2, a capacitor C2, a voltage comparator U5, and a resistor R3, an input end of the inverter U1 is denoted as a point b, and an output of the inverter U1One input end of the NAND gate U2 is connected with one end of the NAND gate U2, the other input end of the NAND gate U2 receives the front neuron signal pre, the output end of the NAND gate U2 is connected with the control electrode of the electronic switching tube P1, the input end of the electronic switching tube P1 is connected with a power supply voltage, the output end of the electronic switching tube P1 is connected with one end of the first analog switch, the control end of the first analog switch receives the rear neuron signal post, the other end of the first analog switch is connected with the homodromous input end of the voltage comparator U5, and the reverse input end of the voltage comparator U5 is connected with a regulating voltage V th The output end of the voltage comparator U5 is connected with the memristive synaptic module, one end of the resistor R3 is connected with the power input end of the voltage comparator U5 in parallel and connected with a power supply, and the other end of the resistor R3 is connected with the output end of the voltage comparator U5; the resistor R1 and the capacitor C1 are connected in parallel between the output end of the electronic switch tube P1 and the ground, a node, where the resistor R1, the capacitor C1 and the output end of the electronic switch tube P1 are connected, is denoted as a point a, the resistor R2 and the capacitor C2 are connected in parallel between the same-direction input end of the voltage comparator U5 and the ground, and are used for receiving charges transmitted by the capacitor C1, wherein the capacitance C2 is far smaller than C1, the capacitance C2 is 1uF, the resistance R2 is 15k, the resistance R1 is 1k, and the capacitance C1 is 10uF.
The first analog switch is implemented by an analog switch chip ADG442, and includes four-channel single-pole single-throw switches, where each single-pole single-throw switch is controlled to be turned on or off by a control end. The electronic switch tube P1 adopts a PMOS tube, the grid electrode of the electronic switch tube P1 is connected with the output end of the NAND gate U2, the source electrode of the electronic switch tube P1 is connected with a +5V power supply, and the drain electrode of the electronic switch tube P1 is connected with the S1 pin of the analog switch chip ADG442, the resistor R1 and the capacitor C1; the D1 pin of ADG442 is connected to the positive input of voltage comparator U5, the IN1 pin of ADG442 is connected to the post-neuron signal post, the VSS pin of ADG442 is connected to + V, VDD and +15V, and the GND, S4, D4 and IN4 pins are all grounded. The voltage comparator U5 is implemented with LM 393. The power input terminal of LM393 is connected with +5V power supply, and its GND pin is grounded.
In this embodiment, the suppression module includes an inverter U3, a nand gate U4, an electronic switching tube P2, and an electric circuitThe voltage regulator comprises a resistor R4, a capacitor C3, a second analog switch, a resistor R5, a capacitor C4, a voltage comparator U6 and a resistor R6, wherein the input end of an inverter U3 is marked as a point a, the input end of the inverter U3 is connected with the point a in the enhancement module, the output end of the inverter U3 is connected with one input end of a NAND gate U4, the other input end of the NAND gate U4 receives a post neuron signal post, the output end of the NAND gate U4 is connected with a control electrode of an electronic switch tube P2, the input end of the electronic switch tube P2 is connected with a power supply voltage, the output end of the electronic switch tube P2 is connected with one end of the second analog switch, the control end of the second analog switch receives a pre neuron signal pre, the other end of the second analog switch is connected with a homodromous input end of the voltage comparator U6, and the reverse input end of the voltage comparator U6 is connected with a voltage V regulation and control voltage V th The output end of the voltage comparator U6 is connected with the memristive synaptic module, one end of the resistor R6 is connected with the power input end of the voltage comparator U6 in parallel and connected with a power supply, and the other end of the resistor R6 is connected with the output end of the voltage comparator U6; the resistor R4 and the capacitor C3 are connected in parallel between the output end of the electronic switching tube P2 and the ground, a connection node of the resistor R4, the capacitor C3 and the output end of the electronic switching tube P2 is denoted as a point b, the point b of the suppression module is connected with the point b of the enhancement module, namely, the point b of the suppression module is connected with the input end of the inverter U1. The resistor R5 and the capacitor C4 are connected in parallel between the same-direction input end of the voltage comparator U6 and the ground, and are used for receiving charges transmitted by the capacitor C3, wherein the capacitance value of C4 is far smaller than C3, the capacitance of C4 is 1uF, the resistance value of R5 is 15k, and the resistance value of R4 is 1k and the capacitance value of C3 is 10uF.
The second analog switch is implemented by multiplexing an analog switch chip ADG442 used by the first analog switch, and includes four-way single-pole single-throw switches, where each single-pole single-throw switch is controlled to be turned on or off by a control end. The first analog switch uses the first channel (S1, D1) and the fourth channel (S4, D4) of the ADG442 chip, the second analog switch uses the third channel (S3, D3) and the second channel (S2, D2) of the ADG442 chip, the IN3 pin controls the on-off of the third channel (S3, D3), and the IN2 pin controls the on-off of the second channel (S2, D2).
The electronic switch tube P2 adopts a PMOS tube, the grid electrode of the electronic switch tube P2 is connected with the output end of the NAND gate U4, the source electrode of the electronic switch tube P2 is connected with a +5V power supply, and the drain electrode of the electronic switch tube P2 is connected with the D3 pin of the analog switch chip ADG442, the resistor R4 and the capacitor C3; the S3 pin of ADG442 is connected to the positive input of voltage comparator U6, the IN3 pin of ADG442 is connected to the pre-neuron signal pre, the VSS of ADG442 is connected to-15V, VDD to +15V, and the GND, S2, D2 and IN2 pins are all grounded. The voltage comparator U6 is implemented with LM 393. The power input terminal of LM393 is connected to +5V power supply, its GND pin is grounded, and resistor R6 is connected between Vcc and the output terminal of voltage comparator U6.
The current neuron signal pre reaches the synapse-like circuit of the embodiment before the post-neuron signal post, and the enhancement module outputs pulse levels with different widths at the output end of the enhancement module according to the time difference of the input pre-neuron signal pre before the post-neuron signal post, wherein the larger the time difference is, the wider the pulse width is. When the front neuron signal pre reaches the synapse-like circuit before the rear neuron signal post, the front neuron signal pre is at a high level, the rear neuron signal post is at a low level, the low level of the rear neuron signal post locks the NAND gate U4 in the inhibition module, the NAND gate U4 outputs a high level, and the gate-source voltage U of the PMOS tube P2 at the moment GS Greater than the turn-on voltage U GS（th） The PMOS tube P2 enters a cut-off region, a +5V power supply cannot charge C3, the point b in the suppression module keeps low potential, and the suppression module does not work at the moment. When the current neuron signal pre reaches the input high level, the point b in the enhancement module outputs the high level through the inverter U1, the two input ends of the NAND gate U2 are both high level, and the output end of the NAND gate U2 outputs the low level. Grid source voltage U of PMOS tube P1 GS Less than the turn-on voltage U GS（th） The PMOS tube P1 is conducted, the +5V direct current power supply charges the capacitor C1, the conduction time of the PMOS tube P1 is the pulse width of the neuron signal pre before the input signal, when the signal of the neuron signal pre ends to return to the low level, the capacitor C1 ends to be charged, and then the capacitor C1 begins to discharge through the resistor R1. Up to post-neuronal signal pos When the t signal arrives, the 1 pin IN1 of the ADG422 becomes high level, the single-pole single-throw analog switch (S1 pin, D1 pin) between the 2 pin and the 3 pin is turned on, the capacitor C1 with larger capacitance starts to charge the capacitor C2 with smaller capacitance, and the capacitor C2 is full of charge before the post neuron signal post returns to low potential and the first analog switch is turned off because the capacitance of the capacitor C2 is far smaller than that of the capacitor C1. And the maximum voltage reached by the capacitor C2 is the same as the voltage of the capacitor C1 at the moment when the first analog switch is turned on, and since the capacitor C1 is continuously discharged before that, the voltage of the capacitor C1 is continuously reduced, the earlier the time when the post neuron signal post arrives, that is, the smaller the time difference between the pre neuron signal pre and the post neuron signal post, the larger the voltage maximum value reached by the capacitor C2. After the post neuron signal post returns to the low potential, the capacitor C2 starts to discharge through the resistor R2, and the discharging time of the capacitor C2 is proportional to the maximum voltage value reached by charging the capacitor C2 due to the fixed resistance value of the resistor R2 and the fixed capacitance value of the capacitor C2. Resistor R2 and capacitor C2 are connected in parallel to the same-directional input terminal of voltage comparator U5, and the reverse input terminal thereof is connected to regulated voltage V th When the capacitor C2 is fully charged, the output end of the voltage comparator U5 outputs a high level, and when the voltage of the capacitor C2 is discharged to V th In the following case, the voltage comparator U5 outputs a low level; the smaller the time difference between the front neuron signal pre and the rear neuron signal post of the input signal is, the higher the initial discharge voltage of the capacitor C2 is, and the wider the output DC level width of the output end of the voltage comparator U5 is; can also be controlled by changing the voltage V th Adjusting the comparison threshold of the voltage comparator U5 to change the output level width, V under the condition that the time difference between the two input signals is unchanged th The smaller the dc pulse width output from the voltage comparator U5 is, the larger the dc pulse width is. Resistor R3 is connected between Vcc and the output of voltage comparator U5 as a pull-up resistor to allow voltage comparator U5 (i.e., LM 393) to function properly.
The circuit structure and the working principle of the suppression module are basically the same as those of the enhancement module, the current neuron signal pre and the post neuron signal post arrive at the synapse bionic circuit, and the suppression module outputs at the output end according to the time difference of the pre neuron signal pre before the post neuron signal post is inputPulse levels of different widths, the greater the time difference the wider the pulse width. When the post neuron signal post reaches the synapse-like circuit before the pre neuron signal pre, the post neuron signal post is at a high level, the pre neuron signal pre is at a low level, the low level of the pre neuron signal pre locks the NAND gate U2 in the enhancement module, the NAND gate U2 outputs a high level, and the U of the PMOS tube P1 at the moment GS Greater than U GS（th） The PMOS tube P1 enters a cut-off region, a +5V power supply cannot charge the capacitor C1, and the point a of the enhancement module keeps low potential. When the post neuron signal post reaches a high level, the point a in the enhancement module is connected with the input end of the inverter U3, the high level is output through the inverter U3, the two input ends of the NAND gate U4 are both high level, and the NAND gate U4 outputs a low level. Grid source voltage U of PMOS tube P2 GS Less than the turn-on voltage U GS（th） The PMOS transistor P2 is turned on, the +5v dc power supply charges the capacitor C3, the on duration of the PMOS transistor P2 is the pulse width of the post neuron signal after inputting the signal, when the post neuron signal ends to return to the low level, the capacitor C3 ends to charge, and then the capacitor C3 begins to discharge through the resistor R4. Until the pre-neuron signal pre arrives, the 9 pin (i.e., IN3 pin) of the ADG422 becomes high level, the single-pole single-throw analog switch between the 10 pin and the 11 pin (i.e., D3 pin and S3 pin) is turned on, the capacitor C3 with larger capacitance starts to charge the capacitor C4 with smaller capacitance, and the capacitor C3 fills the charge before the pre-neuron signal pre returns to low potential and the second analog switch (i.e., D3 pin and S3 pin) is turned off because the capacitance C4 is far smaller than the capacitor C3. And the maximum voltage reached by the capacitor C4 is the same as the voltage of the capacitor C3 at the moment when the second analog switch is turned on, and since the capacitor C3 is continuously discharged before that, the voltage of the capacitor C3 is continuously reduced, the earlier the moment when the front neuron signal pre arrives, that is, the smaller the time difference between the rear neuron signal post and the front neuron signal pre, the larger the voltage maximum value reached by the capacitor C4 is charged. After the pre-neuron signal pre returns to the low potential, the capacitor C4 starts to discharge through the resistor R5, and the discharging time of the capacitor C4 is proportional to the maximum voltage value reached by charging the capacitor C4 due to the fixed resistance value of the resistor R5 and the capacitance value of the capacitor C4. Resistor R5 and Capacitor C4 is connected in parallel to the same-direction input end of voltage comparator U6 (LM 393), and the opposite-direction input end is connected to regulated voltage V th When the capacitor C4 is fully charged, the output end of the voltage comparator U6 outputs a high level, and when the voltage of the capacitor C4 is discharged to the regulated voltage V th When the voltage comparator U6 outputs low level, and the smaller the time difference between the neuron signal post after inputting the signal and the pre-neuron signal pre is, the higher the initial discharging voltage of the capacitor C4 is, and the wider the output direct current level width of the output end of the voltage comparator U6 is; can also be controlled by changing the voltage V th The comparison threshold value of the voltage comparator U6 is regulated so as to change the width of the output level, and the voltage V is regulated under the condition that the time difference between two input signals is unchanged th The smaller the dc pulse width output from the voltage comparator U6 is, the larger the dc pulse width is. Resistor R6 is connected between Vcc and the two ends of the output terminal of voltage comparator U6, and acts as a pull-up resistor to make voltage comparator U6 (LM 393) work normally.
In this embodiment, the memristive synapse module includes a first memristive synapse submodule, a second memristive synapse submodule, a third memristive synapse submodule, and a fourth memristive synapse submodule; when the time difference deltat between the input of the pre-neuron signal pre and the post-neuron signal post to the memristive synaptic block is taken as the abscissa and the conductance weight of the memristor Rm is taken as the ordinate,
The first memristive synaptic submodule operates in quadrants 1 and 3 and is used for simulating neural activity operating in quadrants 1 and 3, such as simulating the activity of visual nerves of an organism;
the second memristive synaptic submodule works in the 2 nd quadrant and the 4 th quadrant and is used for simulating the neural activity working in the 2 nd quadrant and the 4 th quadrant;
the third memristive synaptic submodule operates in quadrants 1 and 2 and is used for simulating the neural activity operating in quadrants 1 and 2, such as simulating the activity of muscle nerves of an organism;
the fourth memristive synaptic submodule works in quadrants 3 and 4 and is used for simulating neural activity working in quadrants 3 and 4.
The memristive synaptic module is connected with the enhancement module and the suppression module through a selection switch and is used for respectively controlling the first memristive synaptic submodule, the second memristive synaptic submodule, the third memristive synaptic submodule and the fourth memristive synaptic submodule to be connected.
Embodiment one:
the present embodiment uses a selection switch to switch on the connection between the enhancement module, the suppression module, and the first memristive synaptic submodule on the basis of the main scheme. The first memristive synaptic submodule circuit of the embodiment is used for realizing the STDP learning rule that the learning function is located in the 1,3 quadrants when the time difference Δt between the pre-neuron signal pre and the post-neuron signal post is taken as the abscissa and the conductance weight of the memristor Rm is taken as the ordinate.
In this embodiment, the first memristive synaptic submodule includes a memristor Rm and a third analog switch, the third analog switch includes at least four channels, an output end of the enhancement module is connected to a control end of a first channel of the third analog switch and a control end of a fourth channel of the third analog switch, one end of the first channel of the third analog switch is connected to a power supply, the other end of the first channel of the third analog switch is connected to an anode of the memristor Rm, a cathode of the memristor Rm is connected to one end of the fourth channel of the third analog switch, and the other end of the fourth channel of the third analog switch is grounded; the output end of the suppression module is connected with the control end of the second channel of the third analog switch and the control end of the third channel of the third analog switch, one end of the second channel of the third analog switch is connected with a power supply, the other end of the second channel of the third analog switch is connected with the negative electrode of the memristor Rm, the positive electrode of the memristor Rm is connected with one end of the third channel of the third analog switch, and the other end of the third channel of the third analog switch is grounded.
Specifically, as shown in fig. 2a, the third analog switch is implemented using an analog switch chip ADG442 that includes four controllable single pole single throw switching channels. The GND pin of ADG442 is grounded, VSS is connected to-15V, and VDD is connected to +15V. IN the first memristive synaptic submodule, the output end of a voltage comparator U5 of the enhancement module is respectively connected with an IN1 pin and an IN4 pin of an ADG442, and the voltage comparator U5 is used for controlling a single-pole single-throw switch formed by the D1 pin and the S1 pin, and a single-pole single-throw switch formed by the D4 pin and the S4 pin, wherein the D1 pin of the ADG442 is connected with an external power supply, and the external power supply adopts +2V voltage for considering that the voltage is closer to an STDP learning function of a living being; the S1 pin of the ADG442 is connected with the anode of the memristor Rm; the S4 pin is grounded, and the D4 pin is connected with the negative electrode of the memristor Rm. IN the first memristor synaptic submodule, the output end of a voltage comparator U6 of the suppression module is respectively connected with an IN2 pin and an IN3 pin of an ADG442, and is used for controlling a single-pole single-throw switch formed by a D2 pin and an S2 pin, and a single-pole single-throw switch formed by a D3 pin and an S3 pin, wherein the D2 pin is connected with an external power supply, and the external power supply adopts +2V voltage for considering that the STDP learning function of living beings is closer; the S2 pin is connected with the negative electrode of the memristor Rm; the S3 pin is grounded, and the D3 pin is connected with the anode of the memristor Rm.
When the time difference Δt between the pre-neuron signal pre and the post-neuron signal post is taken as the abscissa and the conductance weight of the memristor Rm is taken as the ordinate, the first memristor synapse submodule circuit of the embodiment is used for realizing the STDP learning rule that the learning function is located in the 1,3 quadrants, the current neuron signal pre reaches the input end of the synapse bionic circuit before the post-neuron signal post, and the enhancement module outputs direct current levels with different widths to the memristor synapse module according to the time difference Δt reached by the pre-neuron signal pre and the post-neuron signal post. When the memristive synaptic module circuit of this embodiment is adopted, the direct current level transmitted by the enhancement module is input to pins 1 and 8 (i.e., pins IN1 and IN 4) of the ADG442 of the memristive synaptic module, the single-pole single-throw analog switch (composed of pins D1 and S1) of the first channel and the single-pole single-throw analog switch (composed of pins D4 and S4) of the fourth channel are turned on, and as the suppression module stops working, pins 9 and 16 (i.e., pins IN3 and IN 2) connected with the suppression module are at low potential, the single-pole single-throw analog switch (composed of pins D2 and S2) of the second channel on the right side and the single-pole single-throw analog switch (composed of pins D3 and S3) of the third channel are IN an off state. The current generated by the +2V direct current power supply can be transmitted to the positive electrode of the memristor Rm through a single-pole single-throw analog switch (composed of a D1 pin and an S1 pin) of the first channel, and then flows to a zero potential point from the negative electrode of the memristor Rm through a single-pole single-throw analog switch (composed of a D4 pin and an S4 pin) of the fourth channel, so that a closed loop is formed, and the conductance of the memristor Rm is increased. The wider the direct current level generated by the enhancement module, namely the larger the time difference between the front neuron signal pre and the rear neuron signal post of the input signal is, the larger the conductivity of the memristor Rm is increased; when the post neuron signal post reaches the input end of the synapse bionic circuit before the pre neuron signal pre, the suppression module outputs direct current levels with different widths to the memristive synapse module according to the arrival time difference delta T, the direct current levels transmitted by the suppression module are input to pins 9 and 16 (namely pins IN3 and IN 2) of the ADG442, the single-pole single-throw analog switch (composed of pins D2 and S2) of the second channel on the right side and the single-pole single-throw analog switch (composed of pins D3 and S3) of the third channel are conducted, and the 1 pin and 8 pin (namely pins IN1 and IN 4) connected with the enhancement module are IN a low potential state due to the stop of the enhancement module, and the single-pole single-throw analog switch (composed of pins D1 and S1) of the first channel on the left side and the single-pole single-throw analog switch (composed of pins D4 and S4) of the fourth channel are IN an off state. The current generated by the +2V direct current power supply can be transmitted to the negative electrode of the memristor Rm through a single-pole single-throw analog switch (composed of a D2 pin and an S2 pin) of the second channel, and then flows to a zero potential point from the positive electrode of the memristor Rm through a single-pole single-throw analog switch (composed of a D3 pin and an S3 pin) of the third channel, so that a closed loop is formed, and the electric conduction of the memristor Rm is reduced. The wider the DC level generated by the suppression module, namely the larger the time difference delta T between the post neuron signal post and the pre neuron signal pre of the input signal, the larger the decrease of the conductance of the memristor Rm.
FIG. 3 is a PSPICE simulation time domain waveform diagram of the memristive synapse module in the present embodiment after being connected to the enhancement module and the suppression module, when four different input signals are input respectively. As shown in fig. 3, four output pulses are respectively input in four cases of 1 ms after the leading neuron signal pre, 8 ms after the leading neuron signal pre, 1 ms after the lagging neuron signal post of the leading neuron signal pre, and 8 ms after the lagging neuron signal post of the leading neuron signal pre, so as to simulate four different situations that the leading neuron signal and the trailing neuron signal reach synapse successively. When the input pre-neuron signal pre arrives before the post-neuron signal post for 1 millisecond, the resistance value of the memristor Rm is observed to be reduced from 11K to 10.3K; until the second pair of pre-pulse neuron signals pre arrives 8 milliseconds before the post-pulse neuron signal post, the memristor Rm resistance drops from 10.3K to 9.9K; when the third pair of pre-pulse neuron signals pre arrives 1 millisecond later than the post-neuron signals post, the memristor Rm resistance rises to 10.6K; finally, when the fourth pair of pre-pulse neuron signals pre arrives after 8 milliseconds of post-pulse neuron signals post, the resistance value of the memristor Rm rises to 11K again. The method is the same as the STDP learning rule of biological synapses, when a front neuron signal pre reaches a synapse bionic circuit before a rear neuron signal post, the conduction weight of a memristor Rm rises, and the smaller the time difference delta T between the front neuron signal pre and the rear neuron signal post is, the more obvious the conduction of the memristor Rm rises; when the post-neuron signal post reaches the synapse-like circuit after the pre-neuron signal pre, the memristor Rm conductivity weight decreases, and the smaller the time difference delta T between the post-neuron signal post and the pre-neuron signal pre is, the more obvious the memristor Rm conductivity decreases.
In order to further simulate the bionic characteristic of the STDP learning rule of the biological synapse, as shown in fig. 4, in this embodiment, the pre-neuron signal pre and the post-neuron signal post, in which the time difference DeltaT changes in 1 millisecond steps, are respectively input, and the percentage of the change of the Rm conductance of the memristor under the corresponding condition is recorded and connected in parallel to form a line, as shown in fig. 4, the measured waveform is similar to the waveform of the 1, 3-quadrant STDP learning function of the biological synapse, the simulation effect is better, and the bionic characteristic is good.
To further expand the application range of the first memristive synaptic submodule circuit, FIG. 8 shows the voltage V at different modulation voltages th In the following, taking this embodiment as an example, when the input pulse time difference Δt changes in steps of 1 ms, the memristor Rm is a plot of the percentage change in conductance. Regulating voltage V th For the comparison threshold voltages of the voltage comparators U5 and U6, the lower the threshold voltage, the longer the capacitor C2 and C4 discharge voltages will be to threshold, the wider the output level width of the enhancement and/or suppression modules will be, therefore, under the same input pulse time difference DeltaT, V th The smaller its memristor Rm conductance change the greater the percentage.Thus, according to the actual situation, by adjusting different V th The memristive protruding electric circuit is used.
Embodiment two:
the present embodiment uses a selection switch to switch on the connection between the enhancement module, the suppression module, and the second memristive synaptic submodule on the basis of the master scheme. The second memristive synaptic submodule circuit of the embodiment is used for realizing the STDP learning rule that the learning function is located in the 2,4 quadrants when the time difference Δt between the pre-neuron signal pre and the post-neuron signal post is taken as the abscissa and the conductance weight of the memristor Rm is taken as the ordinate.
In this embodiment, the second memristive synaptic submodule includes a memristor Rm and a fourth analog switch, the fourth analog switch includes at least four channels, an output end of the enhancement module is connected to a control end of a first channel of the fourth analog switch and a control end of a fourth channel of the fourth analog switch, one end of the first channel of the fourth analog switch is connected to a power supply, the other end of the first channel of the fourth analog switch is connected to a negative electrode of the memristor Rm, a positive electrode of the memristor Rm is connected to one end of the fourth channel of the fourth analog switch, and the other end of the fourth channel of the fourth analog switch is grounded; the output end of the suppression module is connected with the control end of the second channel of the fourth analog switch and the control end of the third channel of the fourth analog switch, one end of the second channel of the fourth analog switch is connected with a power supply, the other end of the second channel of the fourth analog switch is connected with the positive electrode of the memristor Rm, the negative electrode of the memristor Rm is connected with one end of the third channel of the fourth analog switch, and the other end of the third channel of the fourth analog switch is grounded.
As shown in fig. 2c, the fourth analog switch is implemented using an analog switch chip ADG442 that includes four controllable single pole single throw switching channels. The GND pin of ADG442 is grounded, VSS is connected to-15V, and VDD is connected to +15V. IN the memristor synaptic module, the output end of a voltage comparator U5 of the enhancement module is respectively connected with an IN1 pin and an IN4 pin of the ADG442, and is used for controlling a single-pole single-throw switch formed by a D1 pin and an S1 pin, and a single-pole single-throw switch formed by a D4 pin and an S4 pin, wherein the D1 pin of the ADG442 is connected with an external power supply, and the external power supply adopts +2V voltage for considering that the external power supply is closer to an STDP learning function of living beings; the S1 pin of the ADG442 is connected with the negative electrode of the memristor Rm; the S4 pin is grounded, and the D4 pin is connected with the anode of the memristor Rm. IN the second memristor synaptic submodule, the output end of a voltage comparator U6 of the suppression module is respectively connected with an IN2 pin and an IN3 pin of the ADG442 and used for controlling a single-pole single-throw switch formed by a D2 pin and an S2 pin and a single-pole single-throw switch formed by a D3 pin and an S3 pin, the D2 pin is connected with an external power supply, and the external power supply adopts +2V voltage for considering that the external power supply is closer to an STDP learning function of living beings; the S2 pin is connected with the anode of the memristor Rm; the S3 pin is grounded, and the D3 pin is connected with the negative electrode of the memristor Rm.
The second memristive synaptic submodule of the present embodiment is basically identical to the circuit structure and the working principle of the first memristive synaptic submodule of the first embodiment, and the second memristive synaptic submodule of the present embodiment is obtained by placing the polarities of the memristors Rm in the first memristive synaptic submodule in the first embodiment in reverse, so that the synaptic function simulated by the second memristive synaptic submodule of the present embodiment is opposite to that of the first memristive synaptic submodule of the first embodiment. In this embodiment, the pre-neuron signal pre and the post-neuron signal post, in which the time difference Δt changes in 1 millisecond steps, are respectively input, and the percentage of the change of the memristor Rm conductance is recorded and connected in parallel to form a line, as shown in fig. 6, the measured waveform is similar to the waveform of the 2, 4-quadrant STDP learning function of the biological synapse, the simulation effect is better, and the bionic characteristic is good.
Embodiment III:
the present embodiment uses a selection switch to switch on the connection between the enhancement module, the suppression module, and the third memristive synaptic submodule on the basis of the master scheme. The third memristive synaptic submodule circuit of the embodiment is used for realizing the STDP learning rule that the learning function is located in the 1,2 quadrants when the time difference Δt between the pre-neuron signal pre and the post-neuron signal post is taken as the abscissa and the conductance weight of the memristor Rm is taken as the ordinate.
In this embodiment, the third memristive synaptic submodule includes a memristor Rm and a fifth analog switch, the fifth analog switch includes at least two channels, an output end of the enhancement module is connected to a control end of a first channel of the fifth analog switch, one end of the first channel of the fifth analog switch is connected to a power supply, another end of the first channel of the fifth analog switch is connected to an anode of the memristor Rm, and a cathode of the memristor Rm is grounded; the output end of the suppression module is connected with the control end of the second channel of the fifth analog switch, one end of the second channel of the fifth analog switch is connected with a power supply, and the other end of the second channel of the fifth analog switch is connected with the anode of the memristor Rm.
As shown IN fig. 2b, the fifth analog switch is implemented by using an analog switch chip ADG442, which includes four controllable single pole single throw switch channels, and only two controllable single pole single throw switch channels are used IN this embodiment, and all the pins (i.e., IN2 pin, S2 pin, D2 pin, IN3 pin, S3 pin, D3 pin) of the other two controllable single pole single throw switch channels are grounded. The GND pin of ADG442 is grounded, VSS is connected to-15V, and VDD is connected to +15V. IN the third memristive synaptic submodule, the output end of a voltage comparator U5 of the enhancement module is connected with an IN1 pin of the ADG442, and is used for controlling a single-pole single-throw switch composed of a D1 pin and an S1 pin, the D1 pin of the ADG442 is connected with an external power supply, the external power supply is closer to an STDP learning function of living beings IN consideration, the external power supply adopts +2V voltage, and the S1 pin of the ADG442 is connected with the positive electrode of a memristor Rm; IN the third memristor synaptic submodule, the output end of a voltage comparator U6 of the inhibition module is connected with an IN4 pin of the ADG442 and is used for controlling a single-pole single-throw switch consisting of a D4 pin and an S4 pin, the S4 pin is connected with an external power supply, the external power supply is closer to an STDP learning function of living beings IN consideration, the external power supply adopts +2V voltage, and the D4 pin is connected with the positive electrode of a memristor Rm; the negative pole of memristor Rm is grounded.
The embodiment is used for realizing the STDP learning rule that the learning function is located in the 1 quadrant and the 2 quadrant, the current neuron signal pre reaches the input end of the synapse bionic circuit before the post neuron signal post, and the enhancement module outputs direct current levels with different widths to the third memristive synapse sub-module according to the time difference delta T between the current neuron signal pre and the post neuron signal post. IN this embodiment, the dc level transmitted from the enhancement module is input to the 1 pin (i.e., IN1 pin) of the ADG442, the single-pole single-throw analog switch (composed of the D1 pin and the S1 pin) of the first channel of the fifth analog switch is turned on, and the current generated by the +2v dc power supply is transmitted to the positive electrode of the memristor Rm through the single-pole single-throw analog switch (composed of the D1 pin and the S1 pin) of the first channel of the fifth analog switch, and then flows from the negative electrode of the memristor Rm to the zero potential point to form a closed loop, so that the conductance of the memristor Rm is increased. The wider the direct current level generated by the enhancement module is, namely the larger the time difference delta T between the pre-neuron signal pre and the post-neuron signal post of the input signal is, the larger the conductivity of the memristor Rm is increased; when the post neuron signal post reaches the input end of the synapse bionic circuit before the pre neuron signal pre, the suppression module outputs direct current levels with different widths to the memristor synapse module according to the arrival time difference delta T, the direct current level transmitted by the suppression module is input to the 8 pins (namely the IN4 pins) of the ADG442, the single-pole single-throw analog switch (composed of the D4 pins and the S4 pins) of the second channel of the fifth analog switch is conducted, and the current generated by the +2V direct current power supply is transmitted to the positive electrode of the memristor Rm through the single-pole single-throw analog switch (composed of the D4 pins and the S4 pins) of the second channel of the fifth analog switch, and flows to a zero potential point from the negative electrode of the memristor Rm, so that the conductance of the memristor Rm rises. The wider the DC level generated by the suppression module, namely the larger the time difference between the post neuron signal post and the pre neuron signal pre of the input signal, the larger the conductance increase of the memristor Rm. In order to further simulate the bionic characteristic of the STDP learning rule of the biological synapse, in this embodiment, a pre-neuron signal pre and a post-neuron signal post with time difference Δt changing in steps of 1 millisecond are respectively input, and the percentage of change of the conductance of the memristor Rm under the corresponding condition is recorded and connected in parallel to form a line, as shown in FIG. 5, the measured waveform is similar to the waveform of the 1, 2-quadrant STDP learning function of the biological synapse, the simulation effect is better, and the bionic characteristic is good.
Embodiment four:
the present embodiment uses a selection switch to turn on the connections between the enhancement module, the suppression module, and the fourth memristive synaptic submodule on the basis of the main scheme. The fourth memristive synaptic submodule circuit of the embodiment is configured to implement the STDP learning rule that the learning function is located in the 3,4 quadrants when the time difference Δt between the pre-neuron signal pre and the post-neuron signal post is taken as the abscissa and the conductance weight of the memristor Rm is taken as the ordinate.
In this embodiment, the fourth memristive synaptic submodule includes a memristor Rm and a sixth analog switch, the sixth analog switch includes at least two channels, an output end of the enhancement module is connected to a control end of a first channel of the sixth analog switch, one end of the first channel of the sixth analog switch is connected to a power supply, another end of the first channel of the sixth analog switch is connected to a negative electrode of the memristor Rm, and an positive electrode of the memristor Rm is grounded; the output end of the suppression module is connected with the control end of the second channel of the sixth analog switch, one end of the second channel of the sixth analog switch is connected with a power supply, and the other end of the second channel of the sixth analog switch is connected with the negative electrode of the memristor Rm.
As shown IN fig. 2D, the sixth analog switch is implemented by using an analog switch chip ADG442, which includes four controllable single pole single throw switch channels, and only two controllable single pole single throw switch channels are used IN this embodiment, and all the pins (i.e., IN2 pin, S2 pin, D2 pin, IN3 pin, S3 pin, D3 pin) of the other two controllable single pole single throw switch channels are grounded. The GND pin of ADG442 is grounded, VSS is connected to-15V, and VDD is connected to +15V. IN the fourth memristive synaptic submodule, the output end of a voltage comparator U5 of the enhancement module is connected with an IN1 pin of the ADG442, and is used for controlling a single-pole single-throw switch composed of a D1 pin and an S1 pin, the D1 pin of the ADG442 is connected with an external power supply, the external power supply is closer to an STDP learning function of living beings IN consideration, the external power supply adopts +2V voltage, and the S1 pin of the ADG442 is connected with the negative electrode of the memristor Rm; IN the fourth memristive synaptic submodule, the output end of a voltage comparator U6 of the suppression module is connected with an IN4 pin of the ADG442 and used for controlling a single-pole single-throw switch composed of a D4 pin and an S4 pin, the S4 pin is connected with an external power supply, the external power supply is closer to an STDP learning function of living beings IN consideration, the external power supply adopts +2V voltage, and the D4 pin is connected with the negative electrode of a memristor Rm; the positive pole of memristor Rm is grounded.
The fourth memristive synaptic sub-module of the present embodiment is basically identical to the circuit structure and the working principle of the third memristive synaptic sub-module of the third embodiment, and the memristor Rm in the third memristive synaptic sub-module of the third embodiment is placed in a reverse direction to obtain the fourth memristive synaptic sub-module of the present embodiment, so that the synaptic function simulated by the fourth memristive synaptic sub-module of the present embodiment is opposite to that of the third memristive synaptic sub-module of the third embodiment. In this embodiment, the pre-neuron signal pre and the post-neuron signal post, in which the time difference Δt changes in 1 millisecond steps, are respectively input, and the parallel connection points of the percentages of the memristor Rm conductivity changes under the corresponding conditions are recorded to form a line, as shown in fig. 7, the measured waveform is similar to the waveform of the 3, 4-quadrant STDP learning function of the biological synapse, the simulation effect is better, and the bionic characteristic is good.
Compared with the synapse bionic circuit which can simulate only one STDP learning rule by the former, the synapse bionic circuit provided by the invention can select various STDP learning functions simulating synapses of different parts such as organism vision nerves and muscle nerves through the selection switch. Meanwhile, the input signal of the circuit discards the traditional complex double spike pulse waveform which is difficult to adjust, and adopts the simple direct current pulse waveform which is easy to adjust, so that the input condition is not harsh. The circuit also has the capability of adjusting the STDP learning rule, changes the variation of the synaptic weight under the same excitation by changing the set regulation voltage, further changes the corresponding parameters for realizing the STDP learning function by simulation, can be used for simulating the STDP learning rule of the synapse under different environments, has wider application range and has larger development potential in the aspect of artificial intelligence bionic.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.

Claims (5)

1. A synapse bionic circuit for realizing diversified STDP learning rules based on memristors is characterized by comprising an enhancement module, a suppression module and a memristor synapse module,
the enhancement module comprises two input ends and an output end, wherein the two input ends of the enhancement module are respectively used for receiving a front neuron signal pre and a rear neuron signal post, and the output end of the enhancement module is connected with the memristive synaptic module;
the suppression module comprises two input ends and an output end, the two input ends of the suppression module are respectively used for receiving a front neuron signal pre and a rear neuron signal post, and the output end of the suppression module is connected with the memristive synaptic module;
when the pre-neuron signal pre arrives before the post-neuron signal post, the enhancement module works, the suppression module stops running, and the enhancement module outputs direct current levels with different widths according to the input time difference of the pre-neuron signal pre and the post-neuron signal post;
When the post neuron signal post arrives before the pre neuron signal pre, the suppression module works, the enhancement module stops running, and the suppression module outputs direct current levels with different widths according to the input time difference of the post neuron signal post and the pre neuron signal pre;
the memristor synaptic module correspondingly inhibits the memristor conductance weight according to the direct current levels with different widths; specifically, the memristive synaptic module comprises a first memristive synaptic submodule, a second memristive synaptic submodule, a third memristive synaptic submodule and a fourth memristive synaptic submodule; when the time difference deltat between the input of the pre-neuron signal pre and the post-neuron signal post to the memristive synaptic block is taken as the abscissa and the conductance weight of the memristor Rm is taken as the ordinate,
the first memristive synaptic submodule works in quadrants 1 and 3 and is used for simulating neural activity working in quadrants 1 and 3;
the second memristive synaptic submodule works in the 2 nd quadrant and the 4 th quadrant and is used for simulating the neural activity working in the 2 nd quadrant and the 4 th quadrant;
the third memristive synaptic submodule works in quadrants 1 and 2 and is used for simulating neural activity working in quadrants 1 and 2;
The fourth memristive synaptic submodule works in the 3 rd quadrant and the 4 th quadrant and is used for simulating the neural activity working in the 3 rd quadrant and the 4 th quadrant;
more specifically:
the first memristor synaptic submodule comprises a memristor Rm and a third analog switch, the third analog switch comprises at least four channels, the output end of the enhancement module is connected with the control end of a first channel of the third analog switch and the control end of a fourth channel of the third analog switch, one end of the first channel of the third analog switch is connected with an external power supply, the other end of the first channel of the third analog switch is connected with the positive electrode of the memristor Rm, the negative electrode of the memristor Rm is connected with one end of the fourth channel of the third analog switch, and the other end of the fourth channel of the third analog switch is grounded; the output end of the suppression module is connected with the control end of the second channel of the third analog switch and the control end of the third channel of the third analog switch, one end of the second channel of the third analog switch is connected with an external power supply, the other end of the second channel of the third analog switch is connected with the negative electrode of the memristor Rm, the positive electrode of the memristor Rm is connected with one end of the third channel of the third analog switch, and the other end of the third channel of the third analog switch is grounded;
The second memristor synaptic submodule comprises a memristor Rm and a fourth analog switch, the fourth analog switch comprises at least four channels, the output end of the enhancement module is connected with the control end of a first channel of the fourth analog switch and the control end of a fourth channel of the fourth analog switch, one end of the first channel of the fourth analog switch is connected with an external power supply, the other end of the first channel of the fourth analog switch is connected with the negative electrode of the memristor Rm, the positive electrode of the memristor Rm is connected with one end of the fourth channel of the fourth analog switch, and the other end of the fourth channel of the fourth analog switch is grounded; the output end of the suppression module is connected with the control end of the second channel of the fourth analog switch and the control end of the third channel of the fourth analog switch, one end of the second channel of the fourth analog switch is connected with an external power supply, the other end of the second channel of the fourth analog switch is connected with the positive electrode of the memristor Rm, the negative electrode of the memristor Rm is connected with one end of the third channel of the fourth analog switch, and the other end of the third channel of the fourth analog switch is grounded.
2. The synaptic bionic circuit for realizing diversified STDP learning rules based on memristors according to claim 1, wherein the enhancement module comprises an inverter U1, a NAND gate U2, an electronic switching tube P1, a resistor R1, a capacitor C1, a first analog switch, a resistor R2, a capacitor C2, a voltage comparator U5 and a resistor R3, wherein the output end of the inverter U1 is connected with one input end of the NAND gate U2, the other input end of the NAND gate U2 receives the pre-neuron signal pre, the output end of the NAND gate U2 is connected with a control electrode of the electronic switching tube P1, the input end of the electronic switching tube P1 is connected with a supply voltage, the output end of the electronic switching tube P1 is connected with one end of the first analog switch, the control end of the first analog switch receives the post-neuron signal post, the other end of the first analog switch is connected with a homodromous input end of the voltage comparator U5, the other input end of the voltage comparator U5 is connected with the voltage comparator U5, the output end of the voltage comparator U3 is connected with the voltage comparator U3 in parallel; the resistor R1 and the capacitor C1 are connected in parallel between the output end of the electronic switch tube P1 and the ground, and the resistor R2 and the capacitor C2 are connected in parallel between the same-direction input end of the voltage comparator U5 and the ground.
3. The synaptic bionic circuit for realizing diversified STDP learning rules based on memristors according to claim 2, wherein the suppression module comprises an inverter U3, a NAND gate U4, an electronic switching tube P2, a resistor R4, a capacitor C3, a second analog switch, a resistor R5, a capacitor C4, a voltage comparator U6 and a resistor R6, wherein the input end of the inverter U3 is connected with the output end of the electronic switching tube P1, the output end of the inverter U3 is connected with one input end of the NAND gate U4, the other input end of the NAND gate U4 receives the back neuron signal post, the output end of the NAND gate U4 is connected with a control electrode of the electronic switching tube P2, the input end of the electronic switching tube P2 is connected with a power supply voltage, the output end of the electronic switching tube P2 is respectively connected with the input end of the inverter U1 and one end of the second analog switch, the control end of the second analog switch is connected with the voltage comparator U6, the other end of the comparator U6 is connected with the voltage comparator U6, and the voltage comparator U6 is connected with the other end of the voltage comparator U6 is connected with the output end of the voltage comparator U6; the resistor R4 and the capacitor C3 are connected in parallel between the output end of the electronic switch tube P2 and the ground, and the resistor R5 and the capacitor C4 are connected in parallel between the same-direction input end of the voltage comparator U6 and the ground.
4. The synaptic bionic circuit for realizing diversified STDP learning rules based on memristors according to claim 1 is characterized in that the third memristor synaptic submodule comprises a memristor Rm and a fifth analog switch, the fifth analog switch comprises at least two channels, the output end of the enhancement module is connected with the control end of the first channel of the fifth analog switch, one end of the first channel of the fifth analog switch is connected with an external power supply, the other end of the first channel of the fifth analog switch is connected with the positive electrode of the memristor Rm, and the negative electrode of the memristor Rm is grounded; the output end of the suppression module is connected with the control end of the second channel of the fifth analog switch, one end of the second channel of the fifth analog switch is connected with an external power supply, and the other end of the second channel of the fifth analog switch is connected with the anode of the memristor Rm.
5. The synaptic bionic circuit for realizing diversified STDP learning rules based on memristors according to claim 1 is characterized in that the fourth memristor synaptic submodule comprises a memristor Rm and a sixth analog switch, the sixth analog switch comprises at least two channels, the output end of the enhancement module is connected with the control end of the first channel of the sixth analog switch, one end of the first channel of the sixth analog switch is connected with an external power supply, the other end of the first channel of the sixth analog switch is connected with the negative electrode of the memristor Rm, and the positive electrode of the memristor Rm is grounded; the output end of the suppression module is connected with the control end of the second channel of the sixth analog switch, one end of the second channel of the sixth analog switch is connected with an external power supply, and the other end of the second channel of the sixth analog switch is connected with the negative electrode of the memristor Rm.
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