CN110427065A - A kind of two-way line loss compensation circuit based on DC-DC converter - Google Patents
A kind of two-way line loss compensation circuit based on DC-DC converter Download PDFInfo
- Publication number
- CN110427065A CN110427065A CN201910588475.XA CN201910588475A CN110427065A CN 110427065 A CN110427065 A CN 110427065A CN 201910588475 A CN201910588475 A CN 201910588475A CN 110427065 A CN110427065 A CN 110427065A
- Authority
- CN
- China
- Prior art keywords
- resistance
- nmos tube
- line loss
- tube
- pmos tube
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005070 sampling Methods 0.000 claims abstract description 56
- 239000000284 extract Substances 0.000 claims abstract description 7
- 230000005611 electricity Effects 0.000 claims description 9
- 239000003990 capacitor Substances 0.000 claims description 7
- 101150096622 Smr2 gene Proteins 0.000 description 9
- 238000000034 method Methods 0.000 description 4
- 238000001514 detection method Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 102220007331 rs111033633 Human genes 0.000 description 2
- 102220264750 rs1305455942 Human genes 0.000 description 2
- 102220095236 rs876658436 Human genes 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- HEZMWWAKWCSUCB-PHDIDXHHSA-N (3R,4R)-3,4-dihydroxycyclohexa-1,5-diene-1-carboxylic acid Chemical compound O[C@@H]1C=CC(C(O)=O)=C[C@H]1O HEZMWWAKWCSUCB-PHDIDXHHSA-N 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000013016 damping Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000001172 regenerating effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The present invention relates to DC-DC converter technical fields, specifically disclose a kind of two-way line loss compensation circuit based on DC-DC converter, applied to DC-DC converter, including two-way line loss compensation module, the input terminal of two-way line loss compensation module is connected separately with sampling resistor Rs1 and sampling resistor Rs2, the output end of two-way line loss compensation module is connected with feedback pin VFB, the feedback pin VFB is connected with feedback resistance R1 and feedback resistance R2, the other end of feedback resistance R1 is connected with equivalent line loss resistance Rcable, the other end of equivalent line loss resistance Rcable connects sampling resistor Rs1 and sampling resistor Rs2, sampling resistor Rs1, one end of sampling resistor Rs2 and feedback resistance R2 are grounded respectively；DC-DC converter output voltage Vout obtains load voltage Vload by equivalent line loss resistance Rcable, two-way line loss compensation module receives the pressure drop on sampling resistor Rs1 and sampling resistor Rs2, be converted to the electric current that electric current Ic extracts feedback resistance R1, to correct output voltage Vout, the configuration of the present invention is simple is suitable for single and double line linear load application.
Description
Technical field
The present invention relates to DC-DC converter technical field more particularly to a kind of two-way line loss compensations based on DC-DC converter
Circuit.
Background technique
In the prior art, the patent of invention of Publication No. CN2018116169855 disclose a kind of line loss compensation circuit and
Implementation method, including control IC, resistance RU, resistance RD and the sampling resistor RSENSE being connected on voltage input end VBUS, institute
It states control IC and is internally connected with CL Compare Logic circuit, two input terminals of the CL Compare Logic circuit pass through control IC's respectively
The port SNSN and the port SNSP connect at the both ends of the sampling resistor RSENSE, compare for sampled voltage to be transferred to be connected to
Ground resistance RC on logic circuit obtains sampling current I C, is also connected with current source ICMP on the CL Compare Logic circuit,
Smaller in electric current ILIM and sampling current is mended for exporting preset max line inside control IC, finally the shape on resistance RU
At the offset voltage being superimposed on voltage input end VBUS；Although the invention can control maximum voltage offset and compensation model
It encloses, and voltage compensation is not limited by external potential-divider network fixed resistance value demand, but compensation can only be provided for single channel load,
It is not suitable for two-way line loss compensation.
A kind of DCDC conversion with line loss compensation is disclosed in the patent of invention of another Publication No. CN2014107659908
Device, including control circuit and filter circuit, feed circuit, line loss compensation circuit；Input voltage passes through control circuit and filtered electrical
Die terminals output voltage is generated behind road, generates load end output voltage after line loss resistance as load end power supply；Die terminals are defeated
Voltage is by feedback resistance and compensation resistance feedback to control circuit out；Line loss compensation circuit passes through the mistake in detection control circuit
The voltage of poor amplifier out obtains load current, extracts the benefit proportional with load current from the feedback port of compensation resistance
Electric current is repaid, the line loss pressure drop of load end output voltage is compensated；Although the invention can make offset voltage and loss voltage
It is completely the same, change output voltage with load current, keep constant, and offset can flexibly be set by outer connecting resistance, but
It is loaded only for single channel and compensation is provided, if being applied to two-way line loss compensation, all circuits need to repeat to increase, in addition, compensation
Circuit reflects that load current is poor for wide input voltage and output loading range accuracy by detection EA output end, especially exists
In two-way line loss compensation application.
Summary of the invention
In view of the above technical problems, the present invention provides a kind of two-way line loss compensation circuit based on DC-DC converter, knot
Structure is simple, is suitable for single and double line linear load application, is not necessarily to external resistance, and compensation precision is high.
In order to solve the above technical problem, the present invention provides concrete scheme it is as follows:
A kind of two-way line loss compensation circuit based on DC-DC converter is applied to DC-DC converter, including two-way line loss compensation mould
Block, the input terminal of the two-way line loss compensation module are connected separately with sampling resistor Rs1 and sampling resistor Rs2, and two-way line loss is mended
The output end for repaying module is connected with feedback pin VFB, and the feedback pin VFB is connected with feedback resistance R1 and feedback resistance R2,
The other end of the feedback resistance R1 is connected with equivalent line loss resistance Rcable, the other end of the equivalent line loss resistance Rcable
Connect one end point of sampling resistor Rs1 and sampling resistor Rs2, the sampling resistor Rs1, sampling resistor Rs2 and feedback resistance R2
It is not grounded；
The DC-DC converter output voltage Vout obtains load voltage Vload, two-way line by equivalent line loss resistance Rcable
The pressure drop on compensating module reception sampling resistor Rs1 and sampling resistor Rs2 is damaged, the electricity that electric current Ic extracts feedback resistance R1 is converted to
Stream, to correct output voltage Vout.
Optionally, the two-way line loss compensation module includes start-up circuit, trims circuit, the first current mirror, low-pass filtering
Device and addition trsanscondutance amplifier；
The start-up circuit trims circuit and the first current mirror is separately connected addition trsanscondutance amplifier, and the low-pass filter connects
Connect the first current mirror.
Optionally, the addition trsanscondutance amplifier includes the first PMOS tube MP1, the second PMOS tube MP2, the first NMOS tube
MN1, the second NMOS tube MN2 and resistance R3 to resistance R12；
Described resistance R3, R5, R7, R9 connect the source of the first NMOS tube MN1 with the one end for being sequentially connected in series rear resistance R3 R11
Pole, one end of resistance R11 connect the drain electrode of the first PMOS tube MP1；The drain electrode of first NMOS tube MN1 is with the second NMOS tube MN2's
Drain electrode, which connects together, to be followed by the first current mirror；
Described resistance R4, R6, R8, R10 connect the source of the second NMOS tube MN2 with the one end for being sequentially connected in series rear resistance R4 R12
Pole, one end of resistance R12 connect the drain electrode of the second PMOS tube MP2；
The grid of the first NMOS tube MN1 and the source electrode of the first PMOS tube MP1 are separately connected node VN, second NMOS tube
The source electrode of the grid of MN2 and the second PMOS tube MP2 are separately connected node VP；
The grid of the first PMOS tube MP1 connects sampling resistor Rs1, the grid connection sampling electricity of the second PMOS tube MP2
Hinder Rs2.
Optionally, the circuit that trims includes the 5th NMOS tube MN5 to the 12nd NMOS tube MN12, resistance R3 to resistance
R12；
The drain electrode of the 5th NMOS tube MN5 and source electrode are connected to the both ends of resistance R5；The leakage of the 6th NMOS tube MN6
Pole and source electrode are connected to the both ends of resistance R6；The grid of the 5th NMOS tube MN5 connects the grid of the 6th NMOS tube MN6
Pole；
The drain electrode of the 7th NMOS tube MN7 and source electrode are connected to the both ends of resistance R7；The leakage of the 8th NMOS tube MN8
Pole and source electrode are connected to the both ends of resistance R8；The grid of the 7th NMOS tube MN7 connects the grid of the 8th NMOS tube MN8
Pole；
The drain electrode of the 9th NMOS tube MN9 and source electrode are connected to the both ends of resistance R9；The tenth NMOS tube MN10's
Drain electrode and source electrode are connected to the both ends of resistance R10；The grid of the 9th NMOS tube MN9 connects the tenth NMOS tube MN10's
Grid；
The drain electrode of the 11st NMOS tube MN11 and source electrode are connected to the both ends of resistance R11；12nd NMOS tube
The drain electrode of MN12 and source electrode are connected to the both ends of resistance R12；The grid connection the 12nd of the 11st NMOS tube MN11
The grid of NMOS tube MN12.
Optionally, first current mirror include third PMOS tube MP3 to the 6th PMOS tube MP6, third NMOS tube MN3 and
4th NMOS tube MN4；
The 4th PMOS tube MP4 of third PMOS tube MP3 connection, the 5th PMOS tube MP5 of the 4th PMOS tube MP4 connection, institute
State the 6th PMOS tube MP6 of the 5th PMOS tube MP5 connection, the 6th PMOS tube MP6 connection third NMOS tube MN3, the third
NMOS tube MN3 connection low-pass filter, the other end of the 4th NMOS tube MN4 connection low-pass filter.
Optionally, the start-up circuit includes the second current mirror, electric current leakage and delay circuit；
The second current mirror connection electric current leakage, the electric current leak connection delay circuit.
Optionally, second current mirror includes the 7th PMOS tube MP7 to the tenth PMOS tube MP10；7th PMOS tube
MP7 connection the 8th PMOS tube MP8, the 9th PMOS tube MP9 of the 8th PMOS tube MP8 connection, the 9th PMOS tube MP9 connection
Tenth PMOS tube MP10；
The electric current bottom pour ladle includes the 13rd NMOS tube MN13 to the 15th NMOS tube MN15, the delay circuit include resistance R2 and
Capacitor C2.
Optionally, the low-pass filter includes resistance R1 and capacitor C1.
Compared with prior art, the beneficial effects of the present invention are: the present invention applies the DC-DC converter in doubleway output
On chip, by detecting the sampling resistor pressure drop being connected in load, extraction feedback is converted to by two-way line loss compensation module
Ohmically electric current, to correct output voltage Vout, structure is simple, is suitable for single and double line linear load application, without outer
Resistance is set, compensation precision is high.
Detailed description of the invention
Fig. 1 is a kind of two-way line loss compensation circuit block diagram based on DC-DC converter provided in the embodiment of the present invention.
Fig. 2 is the physical circuit figure of the two-way line loss compensation module provided in the embodiment of the present invention.
Specific embodiment
For the technical solution that the present invention will be described in detail, below in conjunction with the attached drawing of the embodiment of the present invention, to of the invention real
The technical solution for applying example carries out clear, complete description.Obviously, described embodiment is a part of the embodiments of the present invention,
Instead of all the embodiments.Based on described the embodiment of the present invention, those of ordinary skill in the art are without creativeness
Every other embodiment obtained, shall fall within the protection scope of the present invention under the premise of labour.
Unless otherwise defined, all technical and scientific terms used herein and belong to technical field of the invention
The normally understood meaning of technical staff it is identical.Term used herein is intended merely to description specific embodiment
Purpose, it is not intended that in the limitation present invention.Term " and or " used herein includes one or more relevant listed items
Any and all combinations.
For example, a kind of two-way line loss compensation circuit based on DC-DC converter, is applied to DC-DC converter, including two-way line
Compensating module is damaged, the input terminal of the two-way line loss compensation module is connected separately with sampling resistor Rs1 and sampling resistor Rs2, double
The output end of damage compensating module is connected with feedback pin VFB, and the feedback pin VFB is connected with feedback resistance R1 and feedback
Resistance R2, the other end of the feedback resistance R1 are connected with equivalent line loss resistance Rcable, the equivalent line loss resistance Rcable
Other end connection sampling resistor Rs1 and sampling resistor Rs2, the sampling resistor Rs1, sampling resistor Rs2 and feedback resistance R2
One end be grounded respectively；The DC-DC converter output voltage Vout obtains load voltage by equivalent line loss resistance Rcable
Vload, two-way line loss compensation module receive the pressure drop on sampling resistor Rs1 and sampling resistor Rs2, are converted to electric current Ic and extract instead
The electric current of feed resistance R1, to correct output voltage Vout.
The present embodiment is applied on the DC-DC converter chip of doubleway output, by detecting the sampling being connected in load electricity
Damping drop is converted to the electric current extracted on feedback resistance by two-way line loss compensation module, to correct output voltage Vout, ties
Structure is simple, is suitable for single and double line linear load application, is not necessarily to external resistance, and compensation precision is high.
In some embodiments, as shown in Figure 1, a kind of two-way line loss compensation circuit based on DC-DC converter, is applied to
DC-DC converter, including two-way line loss compensation module, the input terminal of the two-way line loss compensation module are connected separately with sampling electricity
Rs1 and sampling resistor Rs2 is hindered, the output end of two-way line loss compensation module is connected with feedback pin VFB, the feedback pin VFB
It is connected with feedback resistance R1 and feedback resistance R2, the other end of the feedback resistance R1 is connected with equivalent line loss resistance Rcable,
The other end of the equivalent line loss resistance Rcable connects sampling resistor Rs1 and sampling resistor Rs2, the sampling resistor Rs1, adopts
One end of sample resistance Rs2 and feedback resistance R2 are grounded respectively；The DC-DC converter output voltage Vout is by equivalent line loss electricity
Resistance Rcable obtains load voltage Vload, and two-way line loss compensation module receives the pressure on sampling resistor Rs1 and sampling resistor Rs2
Drop is converted to the electric current that electric current Ic extracts feedback resistance R1, to correct output voltage Vout.
Specifically, after being converted to the electric current that electric current Ic extracts feedback resistance R1, by formula: Vout=(R1+R2)/R2 × VFB
+ R1 × Ic realizes line loss compensation, steady load voltage Vload to promote output voltage Vout.
In some embodiments, as shown in Fig. 2, the two-way line loss compensation module includes start-up circuit, trims circuit,
One current mirror, low-pass filter and addition trsanscondutance amplifier；The start-up circuit trims circuit and the first current mirror is separately connected
Addition trsanscondutance amplifier, the low-pass filter connect the first current mirror.
Specifically, start-up circuit gives addition trsanscondutance amplifier node VN and VP Injection Current, addition trsanscondutance amplifier is activated；
Circuit is trimmed for correcting line loss penalty coefficient；Low-pass filter introduces low-frequency pole, reduces line loss compensation loop bandwidth, avoids
Loop oscillation；Addition trsanscondutance amplifier samples the pressure drop for being connected on resistance on two loads, is done add operation, is converted to benefit
The electric current Ic on feedback resistance is repaid, is had by KCL, Vout=(R1+R2)/R2 × VFB+R1 × Ic, therefore output voltage Vout compensation rate
For R1 × Ic.
In some embodiments, the addition trsanscondutance amplifier includes the first PMOS tube MP1, the second PMOS tube MP2, first
NMOS tube MN1, the second NMOS tube MN2 and resistance R3 to resistance R12；Described resistance R3, R5, R7, R9 and R11 are sequentially connected in series company
The one end for meeting rear resistance R3 connects the source electrode of the first NMOS tube MN1, and one end of resistance R11 connects the drain electrode of the first PMOS tube MP1；
The drain electrode of first NMOS tube MN1 is connected together with the drain electrode of the second NMOS tube MN2 to be followed by the first current mirror；The resistance
R4, R6, R8, R10 connect the source electrode of the second NMOS tube MN2 with the one end for being sequentially connected in series rear resistance R4 R12, resistance R12's
One end connects the drain electrode of the second PMOS tube MP2；The grid of the first NMOS tube MN1 and the source electrode difference of the first PMOS tube MP1
Connecting node VN, the grid of the second NMOS tube MN2 and the source electrode of the second PMOS tube MP2 are separately connected node VP；Described
The grid of one PMOS tube MP1 connects sampling resistor Rs1, and the grid of the second PMOS tube MP2 connects sampling resistor Rs2.
It trims circuit and includes the 5th NMOS tube MN5 to the 12nd NMOS tube MN12, resistance R3 to resistance R12；Described 5th
The drain electrode of NMOS tube MN5 and source electrode are connected to the both ends of resistance R5；The drain electrode of the 6th NMOS tube MN6 and source electrode difference
It is connected to the both ends of resistance R6；The grid of the 5th NMOS tube MN5 connects the grid of the 6th NMOS tube MN6；Described 7th
The drain electrode of NMOS tube MN7 and source electrode are connected to the both ends of resistance R7；The drain electrode of the 8th NMOS tube MN8 and source electrode difference
It is connected to the both ends of resistance R8；The grid of the 7th NMOS tube MN7 connects the grid of the 8th NMOS tube MN8；Described 9th
The drain electrode of NMOS tube MN9 and source electrode are connected to the both ends of resistance R9；The drain electrode of the tenth NMOS tube MN10 and source electrode point
It is not connected to the both ends of resistance R10；The grid of the 9th NMOS tube MN9 connects the grid of the tenth NMOS tube MN10；Described
The drain electrode of 11 NMOS tube MN11 and source electrode are connected to the both ends of resistance R11；The drain electrode of the 12nd NMOS tube MN12
The both ends of resistance R12 are connected to source electrode；The grid of the 11st NMOS tube MN11 connects the 12nd NMOS tube MN12
Grid.
First current mirror includes third PMOS tube MP3 to the 6th PMOS tube MP6, third NMOS tube MN3 and the 4th NMOS tube
MN4；The 4th PMOS tube MP4 of third PMOS tube MP3 connection, the 5th PMOS tube MP5 of the 4th PMOS tube MP4 connection, institute
State the 6th PMOS tube MP6 of the 5th PMOS tube MP5 connection, the 6th PMOS tube MP6 connection third NMOS tube MN3, the third
NMOS tube MN3 connection low-pass filter, the other end of the grid connection low-pass filter of the 4th NMOS tube MN4, the 4th
The drain electrode of NMOS tube MN4 connects feedback pin VFB.
Start-up circuit includes the second current mirror, electric current leakage and delay circuit；The second current mirror connection electric current leakage, it is described
Electric current leaks connection delay circuit.Second current mirror includes the 7th PMOS tube MP7 to the tenth PMOS tube MP10；7th PMOS tube
MP7 connection the 8th PMOS tube MP8, the 9th PMOS tube MP9 of the 8th PMOS tube MP8 connection, the 9th PMOS tube MP9 connection
Tenth PMOS tube MP10；The electric current bottom pour ladle includes the 13rd NMOS tube MN13 to the 15th NMOS tube MN15, the delay circuit
Including resistance R2 and capacitor C2.The low-pass filter includes resistance R1 and capacitor C1.
Wherein, the drain electrode of the 9th PMOS tube MP9 and the drain electrode of the 14th NMOS tube MN14 are separately connected node VN, and the tenth
The drain electrode of PMOS tube MP10 and the drain electrode of the 15th NMOS tube MN15 are separately connected node VP；The drain electrode of 13rd NMOS tube MN13
One end of resistance R2 is connected with grid, the grid of the 14th NMOS tube MN14 and the grid of the 15th NMOS tube MN15 connect resistance
The other end of R2, the source electrode of the 13rd NMOS tube MN13, the source electrode of the 14th NMOS tube MN14 and the 15th NMOS tube MN15
Source electrode connects capacitor C2；The drain electrode connecting node VP of drain electrode the connecting node VN, the 5th PMOS tube MP5 of third PMOS tube MP3.
In this example, when system starts power up, addition trsanscondutance amplifier node VN and VP are 0V, the first NMOS tube
MN1 and the second NMOS tube MN2 pipe are turned off, and the electric current for flowing through third PMOS tube MP3 to the 6th PMOS tube MP6 pipe is 0uA, the
The mirror currents of three NMOS tube MN3 and the 4th NMOS tube MN4 composition are 0uA, and compensation electric current Ic is 0uA, at this time line loss compensation
Circuit be in failure merger dotted state, start-up circuit by give node VN and VP Injection Current, open the first NMOS tube MN1 and
Second NMOS tube MN2 pipe gets rid of it and annexs point.Addition trsanscondutance amplifier samples the pressure drop of resistance in series load, that is, has, VCS1
=Rs1×Iload1, VCS2=Rs2×Iload2;Guarantee the first PMOS tube MP1 and the second PMOS tube by rationally designing W/L
The threshold V T HP of MP2 pipe is equal with the threshold V T HN of the first NMOS tube MN1 and the second NMOS tube, therefore has VP=VCS2+
VTHP, can similarly obtain VN=VCS1+VTHN；Since resistance R4 upper end voltage is VP-VTHN, resistance R3 upper end voltage is VN-VTHN,
By above-mentioned formula simultaneous, can obtain, resistance R4 upper end voltage is VCS2, and resistance R3 upper end voltage is VCS1, in this example, default
Condition trims circuit as D3-D0=0111, R3=R4=8R, R5=R6=2R, R7=R8=R, R9=R10=R/2, R11=R12=R/4, therefore,
Flow through MP4 pipe electric current be VCS1/ (R3+R5)+VCS2/ (R4+R6)=(VCS1+VCS2)/10R=(Rs1 × Iload1+Rs2 ×
Iload2)/10R, so as to which electric current I must be compensatedC=M × (Rs1 × Iload1+Rs2 × Iload2)/10R, seeks node VFB
KCL has Vout=(R1+R2)/R2 × VFB+R1 × Ic, and the above-mentioned formula of simultaneous can obtain, load compensation amount R1 × Ic=R1 × M
×(Rs1×Iload1+Rs2×Iload2)/10R.Among the above, VTHPFor the threshold voltage of P-type transistor, VTHNFor N-type pipe
Threshold voltage, M are current mirror enlargement ratio, and R is square resistance, when D3-D0=0111, effective series resistance R3-R6,
Iload is load current, and Rs is load current sampling resistor.
Specific implementation process is that start-up circuit is addition by current mirror the 9th PMOS tube MP9 and the tenth PMOS tube MP10
Trsanscondutance amplifier provides Injection Current, so that it is got rid of failure merger state, in order to improve VTHPAnd VTHNMatching precision introduces warp
The electric current leakage for crossing the same current centainly postponed guarantees that start-up circuit is 0uA for node VN and VP net inflow electric current.Trim electricity
Road receives D3-D0 control signal and changes effective series resistance number, corrects line loss penalty coefficient, guarantees the consistent of batch production
Property, implied terms D3-D0=0111, effective series resistance is R5 and R6 at this time, and expanding control signal digit can be improved correction factor
Range and precision.Low-pass filter is made of R1 and C1, in order to avoid the regenerative feedback loop that line loss compensation introduces vibrates,
It needs the bandwidth of line loss compensation being made low, generally taking line loss compensation bandwidth is the 1/10-1/100 of system control bandwidth.Add
Resistance drop in method trsanscondutance amplifier detection series load is converted to the compensation electric current Ic of feedback pin VFB, to realize line
Damage compensation.When load current Iload1 flows through sampling resistor Rs1, sampled voltage VCS1=Iload1 × Rs1 is generated, similarly may be used
, 2 sampled voltage VCS1=Iload2 × Rs2 is loaded, W/L is rationally designed and guarantees the first PMOS tube MP1 and the second PMOS tube
The threshold V T HP of MP2 pipe is equal with the threshold V T HN of the first NMOS tube MN1 and the second NMOS tube MN2 pipe, thus have VP=
VCS2+VTHP, can similarly obtain, VN=VCS1+VTHN；Since resistance R4 upper end voltage is VP-VTHN, the upper end resistance R3 voltage is
VN-VTHN, by above-mentioned formula simultaneous, can obtain, resistance R4 upper end voltage is VCS2, and resistance R3 upper end voltage is VCS1, this example
Middle implied terms trim circuit be D3-D0=0111, R3=R4=8R, R5=R6=2R, R7=R8=R, R9=R10=R/2, R11=R12=
R/4, therefore, flow through the 4th PMOS tube MP4 pipe electric current be VCS1/ (R3+R5)+VCS2/ (R4+R6)=(VCS1+VCS2)/10R=
(Rs1 × Iload1+Rs2 × Iload2)/10R, so as to which electric current I must be compensatedC=M×(Rs1×Iload1+Rs2×
Iload2)/10R seeks KCL to node VFB, there is Vout=(R1+R2)/R2 × VFB+R1 × Ic, and the above-mentioned formula of simultaneous can obtain,
Load compensation amount R1 × Ic=R1 × M × (Rs1 × Iload1+Rs2 × Iload2)/10R.
It can be obtained from above, line loss compensation coefficient and sampling resistor Rs1, Rs2, the first current mirror amplification factor M, feedback resistance R1
It is related with resistance is trimmed, wherein sampling resistor and system are using related, and in order to reduce loss, sampling resistor generally uses 10m Ω
Or 20m Ω；First current mirror amplification factor M is completed in circuit design stage, is a fixed constant；Feedback resistance R1 and system
Using related, general value range 50K Ω -200K Ω, in fast charge application field, feedback resistance value is 100K Ω；Trim electricity
Hindering parameter designing flexibly can adjust compensation system range and precision.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
Therefore it cannot understand limitations on the scope of the patent of the present invention.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention
Range, therefore, protection scope of the present invention should be determined by the appended claims.
Claims (8)
1. a kind of two-way line loss compensation circuit based on DC-DC converter is applied to DC-DC converter, which is characterized in that including double
The input terminal of damage compensating module, the two-way line loss compensation module is connected separately with sampling resistor Rs1 and sampling resistor
Rs2, the output end of two-way line loss compensation module are connected with feedback pin VFB, and the feedback pin VFB is connected with feedback resistance R1
With feedback resistance R2, the other end of the feedback resistance R1 is connected with equivalent line loss resistance Rcable, the equivalent line loss resistance
The other end of Rcable connects sampling resistor Rs1 and sampling resistor Rs2, the sampling resistor Rs1, sampling resistor Rs2 and feedback
One end of resistance R2 is grounded respectively；
The DC-DC converter output voltage Vout obtains load voltage Vload, two-way line by equivalent line loss resistance Rcable
The pressure drop on compensating module reception sampling resistor Rs1 and sampling resistor Rs2 is damaged, the electricity that electric current Ic extracts feedback resistance R1 is converted to
Stream, to correct output voltage Vout.
2. the two-way line loss compensation circuit according to claim 1 based on DC-DC converter, which is characterized in that the two-way
Line loss compensation module includes start-up circuit, trims circuit, the first current mirror, low-pass filter and addition trsanscondutance amplifier；
The start-up circuit trims circuit and the first current mirror is separately connected addition trsanscondutance amplifier, and the low-pass filter connects
Connect the first current mirror.
3. the two-way line loss compensation circuit according to claim 2 based on DC-DC converter, which is characterized in that the addition
Trsanscondutance amplifier includes the first PMOS tube MP1, the second PMOS tube MP2, the first NMOS tube MN1, the second NMOS tube MN2 and resistance
R3 to resistance R12；
Described resistance R3, R5, R7, R9 connect the source of the first NMOS tube MN1 with the one end for being sequentially connected in series rear resistance R3 R11
Pole, one end of resistance R11 connect the drain electrode of the first PMOS tube MP1；The drain electrode of first NMOS tube MN1 is with the second NMOS tube MN2's
Drain electrode, which connects together, to be followed by the first current mirror；
Described resistance R4, R6, R8, R10 connect the source of the second NMOS tube MN2 with the one end for being sequentially connected in series rear resistance R4 R12
Pole, one end of resistance R12 connect the drain electrode of the second PMOS tube MP2；
The grid of the first NMOS tube MN1 and the source electrode of the first PMOS tube MP1 are separately connected node VN, second NMOS tube
The source electrode of the grid of MN2 and the second PMOS tube MP2 are separately connected node VP；
The grid of the first PMOS tube MP1 connects sampling resistor Rs1, the grid connection sampling electricity of the second PMOS tube MP2
Hinder Rs2.
4. the two-way line loss compensation circuit according to claim 3 based on DC-DC converter, which is characterized in that described to trim
Circuit includes the 5th NMOS tube MN5 to the 12nd NMOS tube MN12, resistance R3 to resistance R12；
The drain electrode of the 5th NMOS tube MN5 and source electrode are connected to the both ends of resistance R5；The leakage of the 6th NMOS tube MN6
Pole and source electrode are connected to the both ends of resistance R6；The grid of the 5th NMOS tube MN5 connects the grid of the 6th NMOS tube MN6
Pole；
The drain electrode of the 7th NMOS tube MN7 and source electrode are connected to the both ends of resistance R7；The leakage of the 8th NMOS tube MN8
Pole and source electrode are connected to the both ends of resistance R8；The grid of the 7th NMOS tube MN7 connects the grid of the 8th NMOS tube MN8
Pole；
The drain electrode of the 9th NMOS tube MN9 and source electrode are connected to the both ends of resistance R9；The tenth NMOS tube MN10's
Drain electrode and source electrode are connected to the both ends of resistance R10；The grid of the 9th NMOS tube MN9 connects the tenth NMOS tube MN10's
Grid；
The drain electrode of the 11st NMOS tube MN11 and source electrode are connected to the both ends of resistance R11；12nd NMOS tube
The drain electrode of MN12 and source electrode are connected to the both ends of resistance R12；The grid connection the 12nd of the 11st NMOS tube MN11
The grid of NMOS tube MN12.
5. the two-way line loss compensation circuit according to claim 2 based on DC-DC converter, which is characterized in that described first
Current mirror includes third PMOS tube MP3 to the 6th PMOS tube MP6, third NMOS tube MN3 and the 4th NMOS tube MN4；
The 4th PMOS tube MP4 of third PMOS tube MP3 connection, the 5th PMOS tube MP5 of the 4th PMOS tube MP4 connection, institute
State the 6th PMOS tube MP6 of the 5th PMOS tube MP5 connection, the 6th PMOS tube MP6 connection third NMOS tube MN3, the third
NMOS tube MN3 connection low-pass filter, the other end of the 4th NMOS tube MN4 connection low-pass filter.
6. the two-way line loss compensation circuit according to claim 1 based on DC-DC converter, which is characterized in that the starting
Circuit includes the second current mirror, electric current leakage and delay circuit；
The second current mirror connection electric current leakage, the electric current leak connection delay circuit.
7. the two-way line loss compensation circuit according to claim 6 based on DC-DC converter, which is characterized in that described second
Current mirror includes the 7th PMOS tube MP7 to the tenth PMOS tube MP10；The 8th PMOS tube MP8 of 7th PMOS tube MP7 connection, institute
State the 9th PMOS tube MP9 of the 8th PMOS tube MP8 connection, the tenth PMOS tube MP10 of the 9th PMOS tube MP9 connection；
The electric current bottom pour ladle includes the 13rd NMOS tube MN13 to the 15th NMOS tube MN15, the delay circuit include resistance R2 and
Capacitor C2.
8. the two-way line loss compensation circuit according to claim 2 based on DC-DC converter, which is characterized in that the low pass
Filter includes resistance R1 and capacitor C1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910588475.XA CN110427065B (en) | 2019-07-02 | 2019-07-02 | Double-circuit line loss compensation circuit based on DCDC converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910588475.XA CN110427065B (en) | 2019-07-02 | 2019-07-02 | Double-circuit line loss compensation circuit based on DCDC converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110427065A true CN110427065A (en) | 2019-11-08 |
| CN110427065B CN110427065B (en) | 2021-04-06 |
Family
ID=68409998
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910588475.XA Active CN110427065B (en) | 2019-07-02 | 2019-07-02 | Double-circuit line loss compensation circuit based on DCDC converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110427065B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090160258A1 (en) * | 2007-12-21 | 2009-06-25 | James Allen | Advanced Renewable Energy Harvesting |
| CN102801300A (en) * | 2012-08-30 | 2012-11-28 | 佛山市南海赛威科技技术有限公司 | Primary-side feedback controlled switching power line loss compensating system and method |
| US20130328532A1 (en) * | 2012-06-06 | 2013-12-12 | Analog Vision Technology Inc. | Mult-channel constant voltage and constant current converting controler and apparatus |
| CN106160472A (en) * | 2016-08-11 | 2016-11-23 | 深圳欧创芯半导体有限公司 | Line loss compensation method and device for electric pressure converter |
| CN109491435A (en) * | 2018-12-28 | 2019-03-19 | 上海南芯半导体科技有限公司 | A kind of line loss compensation circuit and implementation method |
-
2019
- 2019-07-02 CN CN201910588475.XA patent/CN110427065B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090160258A1 (en) * | 2007-12-21 | 2009-06-25 | James Allen | Advanced Renewable Energy Harvesting |
| US20130328532A1 (en) * | 2012-06-06 | 2013-12-12 | Analog Vision Technology Inc. | Mult-channel constant voltage and constant current converting controler and apparatus |
| CN102801300A (en) * | 2012-08-30 | 2012-11-28 | 佛山市南海赛威科技技术有限公司 | Primary-side feedback controlled switching power line loss compensating system and method |
| CN106160472A (en) * | 2016-08-11 | 2016-11-23 | 深圳欧创芯半导体有限公司 | Line loss compensation method and device for electric pressure converter |
| CN109491435A (en) * | 2018-12-28 | 2019-03-19 | 上海南芯半导体科技有限公司 | A kind of line loss compensation circuit and implementation method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110427065B (en) | 2021-04-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106168828B (en) | A kind of power supply circuit with overcurrent protection function | |
| CN101388605B (en) | switching regulator | |
| CN106253671A (en) | A kind of internal ripple being applicable to COT control compensates circuit | |
| CN106405197B (en) | Flouride-resistani acid phesphatase 100V high precision electro current detection circuit | |
| CN109004911A (en) | The difference amplifier of common mode inhibition with adjusting and circuit with improved common mode rejection ratio | |
| US9709603B2 (en) | Current sensing system and method | |
| CN104779793B (en) | Breakover time generation circuit for BUCK converter | |
| CN107942787A (en) | Analog signal multiplex circuit and analogue signal acquisition circuit | |
| CN106787726B (en) | The dynamic removing method of adaptive turn-on time control converter output voltage imbalance | |
| CN214150858U (en) | Unbalanced bridge insulation resistance detection circuit for rail transit | |
| CN110289820A (en) | A kind of operation amplifier circuit | |
| CN105099159B (en) | A kind of fast start circuit for DC DC converters | |
| CN109101067A (en) | A kind of low pressure difference linear voltage regulator of dual power rail | |
| CN106787626A (en) | Slope compensation circuit and power conversion unit | |
| CN101257282B (en) | Frequency mixer | |
| CN103458586B (en) | Trsanscondutance amplifier and constant current driver circuit for LED | |
| CN113078817A (en) | Interphase current balance control system suitable for hysteresis control high-frequency two-phase Buck converter | |
| CN109742946A (en) | A kind of DCR sample circuit applied to wide output voltage range Buck converter | |
| CN110427065A (en) | A kind of two-way line loss compensation circuit based on DC-DC converter | |
| CN206313477U (en) | It is a kind of to support that the multichannel of QC2.0 functions is vehicle-mounted and fill chip soon | |
| CN106059516B (en) | Track to track operational amplification circuit and ADC converter, dcdc converter and power amplifier | |
| CN104953658B (en) | Cell voltage conversion circuit and battery management system | |
| CN108462388A (en) | The realization circuit of bootstrap power supply | |
| CN106643925B (en) | Low differential voltage linear voltage stabilizer circuit | |
| CN108762360A (en) | A kind of power transfer circuitry |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220701 Address after: 516003 23rd floor, Desai building, No. 12 Yunshan West Road, Huizhou City, Guangdong Province Patentee after: Guangdong Desai Group Co.,Ltd. Address before: Room 2303, 23 / F, Desai technology building, 9789 Shennan Avenue, Nanshan District, Shenzhen, Guangdong 518067 Patentee before: SHENZHEN DESAY MICROELECTRONIC TECHNOLOGY CO.,LTD. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20231020 Address after: 516006 No.101, hechangwu Road West, Zhongkai high tech Zone, Huizhou City, Guangdong Province Patentee after: HUIZHOU BLUEWAY ELECTRONICS Co.,Ltd. Address before: 516003 23rd floor, Desai building, No. 12 Yunshan West Road, Huizhou City, Guangdong Province Patentee before: Guangdong Desai Group Co.,Ltd. |
|
| TR01 | Transfer of patent right |