CN110416986A - For quick discharging circuit after the shutdown of mainboard - Google Patents
For quick discharging circuit after the shutdown of mainboard Download PDFInfo
- Publication number
- CN110416986A CN110416986A CN201910589303.4A CN201910589303A CN110416986A CN 110416986 A CN110416986 A CN 110416986A CN 201910589303 A CN201910589303 A CN 201910589303A CN 110416986 A CN110416986 A CN 110416986A
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- China
- Prior art keywords
- channel mos
- mos pipe
- power supply
- mainboard
- discharging circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000007599 discharging Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims description 8
- 230000005611 electricity Effects 0.000 claims description 7
- 239000003990 capacitor Substances 0.000 description 5
- 230000000739 chaotic effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000002269 spontaneous effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/047—Free-wheeling circuits
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- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses quick discharging circuits after a kind of shutdown for mainboard, including the first N-channel MOS pipe, second N-channel MOS pipe, third N-channel MOS pipe, 4th N-channel MOS pipe, 5th N-channel MOS pipe and the 6th N-channel MOS pipe, the first N-channel MOS tube grid is electrically connected to SUS_S3# signal, drain electrode is parallel with backup power source respectively, second N-channel MOS tube grid, third N-channel MOS tube grid, 4th N-channel MOS tube grid, 5th N-channel MOS tube grid and the 6th N-channel MOS tube grid, the second N-channel MOS pipe, third N-channel MOS pipe, 4th N-channel MOS pipe, the drain electrode of 5th N-channel MOS pipe and the 6th N-channel MOS pipe has been electrically connected the first power supply, second source, third Power supply, the 4th power supply, the 5th power supply are successively reduced by first power supply to the 5th supply voltage.The present invention can quick release charge, effectively shorten interval time of secondary booting, avoid being switched on again the timing confusion problem powered on.
Description
Technical field
The present invention relates to circuit fields, in particular to quick discharging circuit after a kind of shutdown for mainboard.
Background technique
Industrial equipment motherboard design is extremely complex at present, and capacitor usage quantity is very more, causes after shutting down every time, capacitor is released
Electric discharge is slow not in time.
Capacitor release electricity is very slow after prior art shutdown, and the design of the power supply of board has electrifying timing sequence requirement.Such as
All charges are not released completely after fruit shutdown, just boot up movement again, and the timing powered at this time is chaotic, can to have
Board can be caused not to be switched on or partially have the chip of power supply timing requirements can not work normally.
Summary of the invention
It is an object of the invention to overcome problem above of the existing technology, provide fast after a kind of shutdown for mainboard
Fast discharge circuit, quick release charge effectively shorten the secondary available machine time, avoid the timing powered on chaotic.
To realize above-mentioned technical purpose and the technique effect, the invention is realized by the following technical scheme:
Quick discharging circuit after a kind of shutdown for mainboard, including the first N-channel MOS pipe, the second N-channel MOS pipe,
Three N-channel MOS pipes, the 4th N-channel MOS pipe, the 5th N-channel MOS pipe and the 6th N-channel MOS pipe, the first N-channel MOS pipe
Grid is electrically connected to SUS_S3# signal, and drain electrode is parallel with backup power source, the second N-channel MOS tube grid, third N-channel respectively
Metal-oxide-semiconductor grid, the 4th N-channel MOS tube grid, the 5th N-channel MOS tube grid and the 6th N-channel MOS tube grid, the 2nd N
The drain electrode of channel MOS tube, third N-channel MOS pipe, the 4th N-channel MOS pipe, the 5th N-channel MOS pipe and the 6th N-channel MOS pipe
It is electrically connected the first power supply, second source, third power supply, the 4th power supply, the 5th power supply, by first power supply to described
5th supply voltage successively reduces.
The present invention is further arranged to, the first N-channel MOS pipe, the second N-channel MOS pipe, third N-channel MOS pipe, the 4th N
Channel MOS tube, the 5th N-channel MOS pipe and the 6th N-channel MOS pipe pass through first resistor, second resistance, 3rd resistor, respectively
Four resistance, the 5th resistance and the 6th resistance and the backup power source, the first power supply, second source, third power supply, the 4th power supply,
5th power supply is connected.
The present invention is further arranged to, and the first N-channel MOS tube grid is by the 7th resistance in the SUS_3# signal
It is connected.
The present invention is further arranged to, the first N-channel MOS pipe, the second N-channel MOS pipe, third N-channel MOS pipe,
4th N-channel MOS pipe, the 5th N-channel MOS pipe and the 6th N-channel MOS pipe source electrode are grounded respectively.
The present invention is further arranged to, and first power supply is 5V direct current.
The present invention is further arranged to, and the second source is 3.3V direct current.
The present invention is further arranged to, and the third power supply is 1.8V direct current.
The present invention is further arranged to, and the 4th power supply is 1.5V direct current.
The present invention is further arranged to, and the 5th power supply is 1.0V direct current.
The present invention is further arranged to, and the backup power source is 5V direct current.
The beneficial effects of the present invention are:
1, compared with the prior art, circuit of the present invention after shut down, will be five kinds corresponding by five N-channel MOS pipes
The power ground of voltage, quick release charge fall without waiting for the charge Spontaneous release of capacitors all on mainboard, effectively shorten two
The interval time of secondary booting, avoid being switched on again the timing confusion problem powered on.
2, when mainboard powers on booting, SUS_S3# signal is high level, and the first N-channel MOS pipe can be opened at this time, the
The drain electrode of one N-channel MOS pipe is low level, the second N-channel MOS pipe, third N-channel MOS pipe, the 4th N-channel MOS pipe, the 5th N
Channel MOS tube, the 6th N-channel MOS pipe will not all be opened, the first power supply+5V, second source+3.3V, third power supply+1.8V,
Four power supply+1.5V, the 5th power supply+1.0V etc. are normally powered on according to design timing, the work of mainboard normal boot-strap.
When mainboard shuts down, SUS_S3# signal is low level, and the first N-channel MOS pipe is closed at this time, the first N-channel MOS pipe
Drain electrode high level, the second N-channel MOS pipe, third N-channel MOS pipe, the 4th N-channel MOS pipe, the 5th N are pulled by backup power source
Channel MOS tube, the 6th N-channel MOS Guan Douhui are opened, the first power supply+5V, second source+3.3V, third power supply+1.8V,
The meeting such as four power supply+1.5V, the 5th power supply+1.0V quick release power down over the ground, until all electricity can all be in zero level.It opens again
When machine, all electricity are not in electrifying timing sequence confusion, are once powered on according to design timing.
The above description is only an overview of the technical scheme of the present invention, in order to better understand the technical means of the present invention,
And can be implemented in accordance with the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention and the accompanying drawings.
A specific embodiment of the invention is shown in detail by following embodiment and its attached drawing.
Detailed description of the invention
The drawings described herein are used to provide a further understanding of the present invention, constitutes part of this application, this hair
Bright illustrative embodiments and their description are used to explain the present invention, and are not constituted improper limitations of the present invention.In the accompanying drawings:
Fig. 1 is for quick discharging circuit schematic diagram after the shutdown of mainboard.
Specific embodiment
In order to which the present invention is understood completely, the preferred embodiment of the present invention will be described with reference to the drawings.It can repair in a variety of manners
Change the embodiment of the present invention, and the scope of the present invention should not be construed as limited to the embodiment being described below in detail.This is provided
The embodiment of invention is to enable those skilled in the art that the present invention is more fully understood.Therefore, can exaggerate in attached drawing
Element shape etc., to emphasize clearer explanation.It should be noted that in the accompanying drawings, identical component is by identical attached drawing mark
Note indicates.It may be by the detailed description of the purport of the invention known function unnecessarily obscured and configuration in addition, being omitted.
It is below with reference to the accompanying drawings and in conjunction with the embodiments, next that the present invention will be described in detail.
Shown in referring to Fig.1, quick discharging circuit after a kind of shutdown for mainboard, including the first N-channel MOS pipe Q1, the
Two N-channel MOS pipe Q2, third N-channel MOS pipe Q3, the 4th N-channel MOS pipe Q4, the 5th N-channel MOS pipe Q5 and the 6th N-channel
Metal-oxide-semiconductor Q6, the first N-channel MOS pipe Q1 grid are electrically connected to SUS_S3# signal, and drain electrode is parallel with backup power source, the respectively
Two N-channel MOS pipe Q2 grids, third N-channel MOS pipe Q3 grid, the 4th N-channel MOS pipe Q4 grid, the 5th N-channel MOS pipe Q5
Grid and the 6th N-channel MOS pipe Q6 grid.
The second N-channel MOS pipe Q2, third N-channel MOS pipe Q3, the 4th N-channel MOS pipe Q4, the 5th N-channel MOS pipe
The drain electrode of Q5 and the 6th N-channel MOS pipe Q6 have been electrically connected the first power supply, second source, third power supply, the 4th power supply,
Five power supplys are successively reduced by first power supply to the 5th supply voltage.
As a preferred embodiment of the present invention, first power supply be+5V direct current, the second source be+
3.3V direct current, the third power supply are+1.8V direct current, and the 4th power supply is+1.5V direct current, and the 5th power supply is
+ 1.0V direct current, the backup power source are+5VS direct current.
The first N-channel MOS pipe Q1, the second N-channel MOS pipe Q2, third N-channel MOS pipe Q3, the 4th N-channel MOS pipe
Q4, the 5th N-channel MOS pipe Q5 and the 6th N-channel MOS pipe Q6 source electrode are grounded respectively.
In this way, SUS_S3# signal is low level, and the first N-channel MOS pipe Q1 is closed at this time when mainboard shuts down, first
The drain electrode of N-channel MOS pipe Q1 pulls into high level, the second N-channel MOS pipe Q2, third N-channel MOS pipe Q3, the 4th by backup power source
N-channel MOS pipe Q4, the 5th N-channel MOS pipe Q5, the 6th N-channel MOS pipe Q6 can be opened, the first power supply+5V, second source
The meeting such as+3.3V, third power supply+1.8V, the 4th power supply+1.5V, the 5th power supply+1.0V quick release power down over the ground, until all
Electricity can all be in zero level.
As a preferred embodiment of the present invention, the first N-channel MOS pipe Q1, the second N-channel MOS pipe Q2, the 3rd N ditch
Road metal-oxide-semiconductor Q3, the 4th N-channel MOS pipe Q4, the 5th N-channel MOS pipe Q5 and the 6th N-channel MOS pipe Q6 pass through first resistor respectively
R1, second resistance R2,3rd resistor R3, the 4th resistance R4, the 5th resistance R5 and the 6th resistance R6 and the backup power source+5VS,
First power supply+5V, second source+3.3V, third power supply+1.8V, the 4th power supply+1.5V, the 5th power supply+1.0V are connected.It is described
First N-channel MOS pipe Q1 grid is connected by the 7th resistance R7 in the SUS_3# signal.
Working principle of the present invention is as follows:
At present in the motherboard design framework of X86, booting is represented when SUS_S3# signal high level, generation when low level
Table shutdown.When mainboard powers on booting, SUS_S3# signal is high level, and the first N-channel MOS pipe Q1 can be opened at this time, first
The drain electrode of N-channel MOS pipe Q1 is low level, the second N-channel MOS pipe Q2, third N-channel MOS pipe Q3, the 4th N-channel MOS pipe
Q4, the 5th N-channel MOS pipe Q5, the 6th N-channel MOS pipe Q6 will not be opened, the first power supply+5V, second source+3.3V, third
Power supply+1.8V, the 4th power supply+1.5V, the 5th power supply+1.0V etc. are normally powered on according to design timing, the work of mainboard normal boot-strap.
When mainboard shuts down, SUS_S3# signal is low level, and the first N-channel MOS pipe Q1 is closed at this time, the first N-channel MOS
The drain electrode of pipe Q1 pulls into high level, the second N-channel MOS pipe Q2, third N-channel MOS pipe Q3, the 4th N ditch by backup power source+5VS
Road metal-oxide-semiconductor Q4, the 5th N-channel MOS pipe Q5, the 6th N-channel MOS pipe Q6 can be opened, and the first power supply+5V, second source+
The meeting such as 3.3V, third power supply+1.8V, the 4th power supply+1.5V, the 5th power supply+1.0V quick release power down over the ground, until all electricity
Zero level will be in.When being switched on again, all electricity are not in electrifying timing sequence confusion, are once powered on according to design timing.
Compared with the prior art, circuit of the present invention after shut down, by five N-channel MOS pipes by corresponding five kinds
Power ground, quick release charge fall without waiting for the charge Spontaneous release of capacitors all on mainboard, effectively shorten secondary booting
Interval time, avoid being switched on again the timing confusion problem powered on.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
1. quick discharging circuit after a kind of shutdown for mainboard, it is characterised in that: including the first N-channel MOS pipe (Q1), second
N-channel MOS pipe (Q2), third N-channel MOS pipe (Q3), the 4th N-channel MOS pipe (Q4), the 5th N-channel MOS pipe (Q5) and the 6th
N-channel MOS pipe (Q6), the first N-channel MOS pipe (Q1) grid are electrically connected to SUS_S3# signal, and drain electrode is parallel with standby respectively
With power supply, second N-channel MOS pipe (Q2) grid, third N-channel MOS pipe (Q3) grid, the 4th N-channel MOS pipe (Q4) grid,
5th N-channel MOS pipe (Q5) grid and the 6th N-channel MOS pipe (Q6) grid, the second N-channel MOS pipe (Q2), the 3rd N ditch
The drain electrode point of road metal-oxide-semiconductor (Q3), the 4th N-channel MOS pipe (Q4), the 5th N-channel MOS pipe (Q5) and the 6th N-channel MOS pipe (Q6)
It is not electrically connected with the first power supply, second source, third power supply, the 4th power supply, the 5th power supply, by first power supply to described
Five supply voltages successively reduce.
2. quick discharging circuit after the shutdown according to claim 1 for mainboard, it is characterised in that: the first N-channel MOS
Manage (Q1), the second N-channel MOS pipe (Q2), third N-channel MOS pipe (Q3), the 4th N-channel MOS pipe (Q4), the 5th N-channel MOS
It manages (Q5) and the 6th N-channel MOS pipe (Q6) and passes through first resistor (R1), second resistance (R2), 3rd resistor (R3), the 4th respectively
Resistance (R4), the 5th resistance (R5) and the 6th resistance (R6) and the backup power source, the first power supply, second source, third power supply,
4th power supply, the 5th power supply are connected.
3. quick discharging circuit after the shutdown according to claim 1 for mainboard, it is characterised in that: the first N ditch
Metal-oxide-semiconductor (Q1) grid in road is connected by the 7th resistance (R7) Yu Suoshu SUS_3# signal.
4. quick discharging circuit after the shutdown according to claim 1 for mainboard, it is characterised in that: the first N ditch
Road metal-oxide-semiconductor (Q1), the second N-channel MOS pipe (Q2), third N-channel MOS pipe (Q3), the 4th N-channel MOS pipe (Q4), the 5th N ditch
Road metal-oxide-semiconductor (Q5) and the 6th N-channel MOS pipe (Q6) source electrode are grounded respectively.
5. quick discharging circuit after the shutdown according to claim 1 for mainboard, it is characterised in that: first power supply
For 5V direct current.
6. quick discharging circuit after the shutdown according to claim 1 for mainboard, it is characterised in that: the second source
For 3.3V direct current.
7. quick discharging circuit after the shutdown according to claim 1 for mainboard, it is characterised in that: the third power supply
For 1.8V direct current.
8. quick discharging circuit after the shutdown according to claim 1 for mainboard, it is characterised in that: the 4th power supply
For 1.5V direct current.
9. quick discharging circuit after the shutdown according to claim 1 for mainboard, it is characterised in that: the 5th power supply
For 1.0V direct current.
10. quick discharging circuit after the shutdown according to claim 1 for mainboard, it is characterised in that: the standby electricity
Source is 5V direct current.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910589303.4A CN110416986A (en) | 2019-07-02 | 2019-07-02 | For quick discharging circuit after the shutdown of mainboard |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910589303.4A CN110416986A (en) | 2019-07-02 | 2019-07-02 | For quick discharging circuit after the shutdown of mainboard |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110416986A true CN110416986A (en) | 2019-11-05 |
Family
ID=68358682
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910589303.4A Withdrawn CN110416986A (en) | 2019-07-02 | 2019-07-02 | For quick discharging circuit after the shutdown of mainboard |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110416986A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200602847A (en) * | 2004-07-09 | 2006-01-16 | Hon Hai Prec Ind Co Ltd | Switch control circuit for motherboard USB power |
| CN201114007Y (en) * | 2007-09-05 | 2008-09-10 | 青岛海信移动通信技术股份有限公司 | Energy supply control circuit and mobile communication apparatus employing same |
| CN104238703A (en) * | 2013-06-11 | 2014-12-24 | 鸿富锦精密电子(天津)有限公司 | Power circuit |
| CN105867523A (en) * | 2015-01-20 | 2016-08-17 | 鸿富锦精密工业(武汉)有限公司 | Discharging circuit and mainboard using same |
| CN107395005A (en) * | 2017-08-30 | 2017-11-24 | 固安华电天仁控制设备有限公司 | A kind of Switching Power Supply filter capacitor quick discharging circuit |
| CN210297251U (en) * | 2019-07-02 | 2020-04-10 | 昆山嘉提信息科技有限公司 | A quick discharge circuit after shutting down for mainboard |
-
2019
- 2019-07-02 CN CN201910589303.4A patent/CN110416986A/en not_active Withdrawn
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200602847A (en) * | 2004-07-09 | 2006-01-16 | Hon Hai Prec Ind Co Ltd | Switch control circuit for motherboard USB power |
| CN201114007Y (en) * | 2007-09-05 | 2008-09-10 | 青岛海信移动通信技术股份有限公司 | Energy supply control circuit and mobile communication apparatus employing same |
| CN104238703A (en) * | 2013-06-11 | 2014-12-24 | 鸿富锦精密电子(天津)有限公司 | Power circuit |
| CN105867523A (en) * | 2015-01-20 | 2016-08-17 | 鸿富锦精密工业(武汉)有限公司 | Discharging circuit and mainboard using same |
| CN107395005A (en) * | 2017-08-30 | 2017-11-24 | 固安华电天仁控制设备有限公司 | A kind of Switching Power Supply filter capacitor quick discharging circuit |
| CN210297251U (en) * | 2019-07-02 | 2020-04-10 | 昆山嘉提信息科技有限公司 | A quick discharge circuit after shutting down for mainboard |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20191105 |