CN110416254A - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
- Publication number
- CN110416254A CN110416254A CN201810396158.3A CN201810396158A CN110416254A CN 110416254 A CN110416254 A CN 110416254A CN 201810396158 A CN201810396158 A CN 201810396158A CN 110416254 A CN110416254 A CN 110416254A
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- Prior art keywords
- metal layer
- array substrate
- signal
- line
- connecting line
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
- H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
Abstract
The present invention provides a kind of array substrate and display panel, array substrate includes viewing area and non-display area, array substrate includes: the first and second metal layer, first and second metal layer is in forming a plurality of grid line in viewing area, wherein, the first metal layer and/or second metal layer extend to non-display area from viewing area, and in forming a plurality of first signal connecting line in non-display area；Driving chip is located at non-display area；Third metal layer, third metal layer is in forming multiple data lines in viewing area, third metal layer forms a plurality of second signal connecting line, every second signal connecting line is drawn from driving chip, every second signal connecting line is electrically connected to form a signal transmssion line with first signal connecting line for extending to non-display area from viewing area respectively, wherein, the resistivity of third metal layer is less than the first metal layer and second metal layer, and the impedance differences between a plurality of signal transmssion line are less than preset threshold.Array substrate provided by the invention and display panel improve display effect.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of array substrate and display panels.
Background technique
In recent years, OLED (Organic Light-Emitting Diode, Organic Light Emitting Diode) technology is quickly grown,
Have become the prospect technology of most possible substitution LCD (Liquid Crystal Display, liquid crystal display).
In the prior art, the data line of display panel or grid line are introduced to setting and are showing after non-display area concentration
The several specific welding disking areas of panel periphery carry out signal transmission with driving chip to realize
Since data line or grid line equisignal line have apart from welding disking area with short, in the region concentrated such as signal wire,
Signal wire longest close to display panel edge, resistance is maximum, and is located at the signal wire in the region center that signal wire is concentrated most
Short, resistance is also minimum.
Resistance is different caused by existing between different signal wires because of length difference, therefore when loading signal, different
The waveform delay that there is the data-signal transmitted thereon between signal wire is excessive, and the pixel intensity for controlling signal wire is uneven,
Influence display effect.
Summary of the invention
The present invention provides a kind of array substrate and display panel, changes to overcome the problems of the above-mentioned prior art
Kind display effect.
The present invention provides a kind of array substrate, and the array substrate includes viewing area and non-display area, comprising: the first metal
Layer and second metal layer, the first metal layer and second metal layer are in forming a plurality of grid line in the viewing area, and described the
One metal layer and/or second metal layer extend to the non-display area from the viewing area, and are formed in the non-display area
A plurality of first signal connecting line；Driving chip is located at the non-display area；Third metal layer, the third metal layer is in described
Multiple data lines are formed in viewing area, the third metal layer also forms a plurality of second signal connecting line, every second letter
Number connecting line is drawn from the driving chip, and is connected with first signal for extending to the non-display area from the viewing area
Wiring is electrically connected to form a plurality of signal transmssion line, and the impedance differences between a plurality of signal transmssion line are less than preset threshold, wherein
The resistivity of the third metal layer is less than the first metal layer and second metal layer.
Optionally, the impedance differences between a plurality of signal transmssion line are equal to 0.
Optionally, each second signal line in the array substrate along the projected length phase in the data line direction
Deng.
Optionally, the signal transmssion line is longer in the projected length in the array substrate, the second signal line in
Projection in the array substrate is longer.
Optionally, the part signal transmssion line only includes first signal connecting line.
Optionally, first signal connecting line is alternatively formed by the first metal layer and the second metal layer.
Optionally, first signal connecting line is electrically connected with the second signal by via hole.
Optionally, the second metal layer is between the first metal layer and the third metal layer.
Optionally, the first metal layer and the second metal layer are formed by molybdenum or aluminium.
Optionally, the third metal layer is formed by the composite layer of titanium aluminium titanium or by copper.
According to another aspect of the invention, a kind of display panel is also provided, comprising: array substrate as described above；And
OLED element is formed in the array substrate.
Compared with prior art, the second signal connecting line that the present invention is formed by setting third metal layer, makes the second letter
The first signal that the both ends of number connecting line are separately connected the pad of driving chip and the first metal layer and/or second metal layer are formed
Connecting line, reduces the resistance of signal transmssion line, and reduces the resistance difference between signal transmssion line.
Detailed description of the invention
Its example embodiment is described in detail by referring to accompanying drawing, above and other feature of the invention and advantage will become
It is more obvious.
Fig. 1 shows the schematic diagram of the display panel of the embodiment of the present invention.
Fig. 2 shows the sectional views of the viewing area of the display panel of the embodiment of the present invention.
Fig. 3 shows the schematic diagram of the array substrate of the embodiment of the present invention.
Fig. 4 shows the schematic diagram of the signal connecting line electrical connection of the embodiment of the present invention.
Specific embodiment
Example embodiment is described more fully with reference to the drawings.However, example embodiment can be with a variety of shapes
Formula is implemented, and is not understood as limited to embodiment set forth herein；On the contrary, thesing embodiments are provided so that the present invention will
Fully and completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.It is identical attached in figure
Icon note indicates same or similar structure, thus will omit repetition thereof.
Described feature, structure or characteristic can be incorporated in one or more embodiments in any suitable manner
In.In the following description, many details are provided to provide and fully understand to embodiments of the present invention.However,
One of ordinary skill in the art would recognize that without one or more in specific detail, or using other methods, constituent element, material
Material etc., can also practice technical solution of the present invention.In some cases, be not shown in detail or describe known features, material or
Person operates to avoid the fuzzy present invention.
Attached drawing of the invention is only used for signal relative positional relationship, and the size at certain positions uses the plotting mode lavished praise on oneself
In order to understand, the size in attached drawing does not represent the proportionate relationship of actual size.
The schematic diagram of the display panel of the embodiment of the present invention is shown referring first to Fig. 1, Fig. 1.Display panel is aobvious for OLED
Show panel 20.OLED display panel 20 includes at least display unit 200, scanner driver 220, data driver 230.OLED is aobvious
Show also may include other equipment and/or element in equipment 20.
Display unit 200 may include being connected to grid line (S1 to Sn), light emitting control line (EM1 to EMn) and data line (D1
To multiple sub-pixels (or pixel) 210 of Dm).
Display unit 200 can show image so as to the first power source (ELVdd) provided from outside and from outside
The second power source (ELVss) provided is corresponding.The grid that display unit 200 can also show and be generated by scanner driver 220
The LED control signal and driven by data that the scanning signal and light emitting control line EM1 to EMn that polar curve S1 to Sn is provided provide
The corresponding image of data-signal that data line D1 to the Dm that dynamic device 230 generates is provided.
Scanning signal and LED control signal can be generated in scanner driver 220.The scanning generated in scanner driver 220
Signal can be sequentially supplied to grid line (S1 to Sn), and LED control signal can be sequentially supplied to each and be shone
Control line (EM1 to EMn).Scanning signal and luminous signal can also be provided to out of turn respectively grid line S1 to Sn with
And light emitting control line EM1 to EMn.In other embodiments, LED control signal can also be generated by light emitting control driver.
Data driver 230 can receive input signal, such as RGB data, and the input that can be generated and receive
The corresponding data-signal of signal.The data-signal generated in data driver 230 can be mentioned by data line (D1 to Dm)
Sub-pixel 210 is supplied, so as to synchronous with scanning signal.Data-signal can also by with scanning signal it is nonsynchronous in a manner of be provided
Give data line D1 to Dm.
In the display panel of Fig. 1, display unit 200 forms the viewing area of display panel, and the part outside viewing area is non-
Viewing area, each driver and is located at non-display area from the signal connecting line that viewing area extends to non-display area.
Referring to Fig. 2, Fig. 2 shows the sectional views of the viewing area of the display panel of the embodiment of the present invention.
Display panel 300 includes substrate 310, thin film transistor (TFT) (TFT element) and display element 380.Thin film transistor (TFT) packet
Include the grid 320 successively formed on substrate 310, active layer 340 and source electrode 350 and drain electrode 360.Grid 320 and active layer
340, gate insulating layer 330 is also formed between source electrode 350 and drain electrode 360.Shape is gone back between thin film transistor (TFT) and display element 380
At there is passivation layer 370.Grid 320 and grid line same layer, are formed by the first metal layer.Source electrode 350 and drain electrode 360 are same with data line
Layer, is formed by second metal layer.
Display element 380 is preferably OLED element comprising the first electrode layer sequentially formed on passivation layer 370
381, organic function layer and the second electrode lay.In the present embodiment, first electrode layer 381 is anode, and the second electrode lay is cathode.
Anode 381 is preferably ITO/Ag/ITO laminated film.In some change case, anode 381 can also use other materials
It is formed.Anode 381 passes through passivation layer 370 and connect with the drain electrode 360 of thin film transistor (TFT).Cathode is preferably formed by Al.One
In a little change case, other materials or laminated film is can be used also to be formed in cathode.Organic function layer may include successively in anode
Hole transmission layer, luminescent layer and the electron transfer layer formed on 381.
It is formed by between pixel by display element 380 and is also formed with pixel defining layer 390.Pixel defining layer 390 is located at
On passivation layer 370, and it is spaced adjacent pixel.
Array substrate provided by the invention is described below with reference to Fig. 3 and Fig. 4.Fig. 3 shows the array of the embodiment of the present invention
The schematic diagram of substrate.
Fig. 4 shows the schematic diagram of the signal connecting line electrical connection of the embodiment of the present invention.Array substrate includes viewing area 110
With non-display area 120.The corresponding display unit shown in FIG. 1 in the viewing area 110 of array substrate.Non-display area 120 surrounds viewing area
110 in viewing area 110 grid line and data line etc. be connected to positioned at driving chip.Array substrate include the first metal layer,
Second metal layer, third metal layer and driving chip 140.
The first metal layer and second metal layer are in forming a plurality of grid line (as shown in Figure 1) and each pixel in viewing area 110
In thin film transistor (TFT) grid (as shown in Figure 2).The first metal layer and second metal layer are optionally formed by molybdenum or aluminium.In
In some specific embodiments, the first metal layer is located on a substrate, and the first metal layer is between substrate and second metal layer.
In the present embodiment, the first metal layer extends to non-display area 120 from viewing area 110, and a plurality of in being formed in non-display area 120
First signal connecting line 131.
Third metal layer can be located on second metal layer.In other words, in some embodiments, second metal layer is located at
Between the first metal layer and second metal layer.In some change case, third metal layer may be alternatively located at second metal layer and substrate
Between.Third metal layer is in the source for the thin film transistor (TFT) for forming multiple data lines (as shown in Figure 1) and each pixel in viewing area 110
Pole and drain electrode (as shown in Figure 2).Third metal layer forms a plurality of second signal connecting line 132.Every second signal connecting line 132
Drawn from driving chip 140, and be electrically connected with the first signal connecting line 131 for extending to non-display area 120 from viewing area 110 with
Form a plurality of signal transmssion line.Further, the first signal connecting line 131 is electrically connected with second signal connecting line 132 by via hole
It connects.Referring specifically to Fig. 4, on substrate 410, the first signal connecting line 420 for being formed by the first metal layer by the first metal layer and
The via hole of insulating layer between third metal layer is electrically connected with the second signal connecting line 430 that third metal layer is formed.Connection the
The via hole of one signal connecting line 420 and second signal connecting line 430 can be used as the pad of driving chip 140.Third metal layer
Resistivity is less than the first metal layer and second metal layer.Third metal layer can be formed by the composite layer of titanium aluminium titanium or by copper,
The resistivity of the material of third metal layer in this way is smaller.In the case where the source-drain electrode and data line different layers of thin film transistor (TFT),
Third metal layer can be used as data line and other need the place of conducting wire connection.
In the present embodiment, the impedance differences between a plurality of signal transmssion line are less than preset threshold.Specifically, signal passes
Defeated line is longer in the projected length in array substrate, and second signal line 131 is longer in the projection in the array substrate.It can manage
Solution, the impedance of signal transmssion line and the length of signal transmssion line are positively correlated, by being formed by the lower third metal layer of resistivity
Second signal line 132 connect with the first signal wire 131 to obtain the impedance of lesser signal transmssion line.Further, such as Fig. 3
Shown, the signal transmssion line closer to array substrate edge is longer, and the length of second signal line 132 is longer；Closer to array
The signal transmssion line of substrate center is shorter, and the length of second signal line 132 is shorter, can reduce a plurality of signal transmssion line in this way
Between impedance differences so that impedance differences between a plurality of signal transmssion line are less than preset threshold (for example, adjacent resistor difference
Less than 5~10 Ω, minimum and maximum resistance difference is less than 10 times).In a preferred embodiment, each second signal line can be calculated
132 length makes the impedance differences between a plurality of signal transmssion line equal.
In a change case of the present embodiment, for the ease of the processing procedure of second signal line, each second signal line is in array
Projected length on substrate along data line direction is equal.In such embodiments, each signal transmssion line is in edge in array substrate
The projected length in data line direction is equal, and closer to the signal transmssion line at array substrate edge in the upright projection of array substrate
Length it is longer.Although not accurately calculating the length of second signal line, it is also possible that closer to the of array substrate edge
Binary signal line is longer in the length of the upright projection of array substrate, and then reduces the impedance differences between a plurality of signal transmssion line.
In another change case of the present embodiment, only the part signal transmission line close to array substrate edge uses third
The second signal connecting line 132 that metal layer is formed, and the signal transmssion line close to array substrate center can only include the first signal
Connecting line 131.Thus, it is possible to which only production part second signal connecting line 132 can reduce the resistance between a plurality of signal transmssion line
Robust value.
In another change case of the present embodiment, the first signal connecting line 131 can be by the first metal layer and the second metal
Layer is alternatively formed.In other words, have between adjacent two the first signal connecting lines 131 formed by the first metal layer one by second
The first signal connecting line 131 that metal layer is formed.
Above-mentioned each embodiment and change case are only to illustrate schematically basic conception of the invention, art technology
More variation patterns may be implemented in personnel, and under the premise of without prejudice to basic idea of the present invention, these variation patterns are all at this
Within the protection scope of invention.
Compared with prior art, the second signal connecting line that the present invention is formed by setting third metal layer, makes the second letter
The first signal that the both ends of number connecting line are separately connected the pad of driving chip and the first metal layer and/or second metal layer are formed
Connecting line, reduces the resistance of signal transmssion line, and reduces the resistance difference between signal transmssion line.
It is particularly shown and described exemplary embodiments of the present invention above.It should be understood that the present invention is not limited to institute
Disclosed embodiment, on the contrary, it is intended to cover comprising various modifications within the scope of the appended claims and equivalent set
It changes.
Claims (11)
1. a kind of array substrate, the array substrate includes viewing area and non-display area characterized by comprising
The first metal layer and second metal layer, the first metal layer and second metal layer are in forming a plurality of grid in the viewing area
Polar curve,
Wherein, the first metal layer and/or second metal layer extend to the non-display area from the viewing area, and in described
A plurality of first signal connecting line is formed in non-display area；
Driving chip is located at the non-display area；
Third metal layer, the third metal layer is in forming multiple data lines, the third metal layer also shape in the viewing area
At a plurality of second signal connecting line, every second signal connecting line is drawn from the driving chip, every second letter
Number connecting line be electrically connected respectively with first signal connecting line for extending to the non-display area from the viewing area with
Form a signal transmssion line, wherein the resistivity of the third metal layer is less than the first metal layer and second metal layer, a plurality of letter
Impedance differences between number transmission line are less than preset threshold.
2. array substrate as described in claim 1, which is characterized in that the impedance differences between a plurality of signal transmssion line are equal to
Zero.
3. array substrate as described in claim 1, which is characterized in that each second signal line is in edge in the array substrate
The projected length in the data line direction is equal.
4. array substrate as described in claim 1, which is characterized in that the signal transmssion line is in the throwing in the array substrate
Shadow length is longer, and the second signal line is longer in the projection in the array substrate.
5. array substrate as described in claim 1, which is characterized in that the part signal transmssion line only includes first letter
Number connecting line.
6. such as array substrate described in any one of claim 1 to 5, which is characterized in that first signal connecting line is by described
The first metal layer and the second metal layer are alternatively formed.
7. such as array substrate described in any one of claim 1 to 5, which is characterized in that first signal connecting line with it is described
Second signal is electrically connected by via hole.
8. such as array substrate described in any one of claim 1 to 5, which is characterized in that the second metal layer is located at described the
Between one metal layer and the third metal layer.
9. such as array substrate described in any one of claim 1 to 5, which is characterized in that the first metal layer and described second
Metal layer is formed by molybdenum or aluminium.
10. such as array substrate described in any one of claim 1 to 5, which is characterized in that the third metal layer is by titanium aluminium titanium
Composite layer is formed by copper.
11. a kind of display panel characterized by comprising
Array substrate as described in any one of claim 1 to 10；And
OLED element is formed in the array substrate.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810396158.3A CN110416254B (en) | 2018-04-27 | 2018-04-27 | Array substrate and display panel |
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|---|---|---|---|
| CN201810396158.3A CN110416254B (en) | 2018-04-27 | 2018-04-27 | Array substrate and display panel |
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| CN110416254B CN110416254B (en) | 2022-03-01 |
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Cited By (6)
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| CN111613656A (en) * | 2020-05-28 | 2020-09-01 | 维沃移动通信有限公司 | Display substrate, display device and mobile terminal |
| CN111952343A (en) * | 2020-08-21 | 2020-11-17 | 昆山国显光电有限公司 | Array substrate and display panel |
| CN113410262A (en) * | 2020-08-10 | 2021-09-17 | 錼创显示科技股份有限公司 | Micro light-emitting diode display panel |
| EP4047662A1 (en) * | 2019-11-15 | 2022-08-24 | BOE Technology Group Co., Ltd. | Array substrate and display device |
| WO2023005235A1 (en) * | 2021-07-26 | 2023-02-02 | 合肥维信诺科技有限公司 | Array substrate, display module, and display apparatus |
| WO2023070404A1 (en) * | 2021-10-27 | 2023-05-04 | 京东方科技集团股份有限公司 | Display panel and preparation method therefor, and display apparatus |
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| WO2023070404A1 (en) * | 2021-10-27 | 2023-05-04 | 京东方科技集团股份有限公司 | Display panel and preparation method therefor, and display apparatus |
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