CN110416162A - The process of FD-SOI - Google Patents
The process of FD-SOI Download PDFInfo
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- CN110416162A CN110416162A CN201910820714.XA CN201910820714A CN110416162A CN 110416162 A CN110416162 A CN 110416162A CN 201910820714 A CN201910820714 A CN 201910820714A CN 110416162 A CN110416162 A CN 110416162A
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- soi
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- oxide layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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Abstract
The invention discloses the processes of FD-SOI a kind of, include: step 1, provide a FD-SOI wafer, and the FD-SOI wafer includes lower layer's oxide layer, soi layer and the upper layer oxide layer on the silicon substrate and silicon substrate being made of monocrystalline silicon；Isolated area is formed by trench process, is then defined using photoresist, the wafer area for needing to etch is opened；Step 2, the window opened by photoresist, performs etching FD-SOI wafer, the upper layer oxide layer in window is etched away, and opens the soi layer below the oxide layer of upper layer；Step 3 removes photoresist；The soi layer below the upper layer oxide layer opened in window is etched away using wet-etching technology.The process of FD-SOI wafer of the present invention, pass through the update of technique, using dry etching plus the group technology of acid etching technique, it is more easier the removal of soi layer, it will not influence the oxide skin(coating) even silicon substrate of lower layer simultaneously, be conducive to improve the controllability of technique and the reliability of device, reduce the influence to device performance.
Description
Technical field
The present invention relates to process for fabrication of semiconductor device field, particularly relate to a kind of be related to the process of FD-SOI.
Background technique
As sophisticated semiconductor manufacturing process is transferred to 28 nanometers hereinafter, variety of problems occurs in traditional technique comprehensively, by
Too small in characteristic size, gate oxide is also very thin, it is easy to the problem of short-channel effect and electric leakage of the grid occurs.Modern half
Conductor manufacturing process has developed two big routes: FinFET and FD-SOI (fully depleted silicon-on-
Insulator: fully- depleted silicon-on-insulator) technology.FD-SOI is a kind of innovated greatly based on two to realize planar transistor structure
Technology: first is that introduced in body silicon it is ultra-thin bury oxygen (BOX) layer, as insulating layer；Second is that with ultra-thin top silicon layer
Produce the transistor channel of fully- depleted.The feature of FD-SOI maximum is can be without modernization overlay device structure, integrality
With realized under the premise of production procedure under Moore's Law chip area is miniature, energy consumption is saved, performance boost and functions expanding.FD
Wafer is made of the very thin silicon layer on buried oxide (BOX) and BOX, to provide uniqueness for the transistor established in this layer
Energy.FD-SOI ensures the various determinant attributes of transistor with very thin top layer, compared with traditional bulk CMOS, is keeping
Under identical performance, FD wafer can save up to 40% power consumption, equally, according to different design optimizations, be with fully- depleted wafer
The processor peak performance on basis can improve 60%.FD-SOI technology can not only obtain finFET fully depleted transistor and bring plane
Whole benefits of traditional technology, but also it is able to achieve advanced back bias voltage (back bias) technology that the latter is unable to reach.FD-
SOI requires design substrate very thin in the monocrystalline silicon layer of buried insulator layer, to ensure that channel region is completely depleted.Traditional FD-SOI
In skill, the removal of soi layer can be related to, this is the device in order to make similar planar technology in the partial region of chip, full
Sufficient design requirement.
As shown in Figure 1, the SOI wafer that existing FD-SOI technique uses is that also have lower layer's oxide layer on a silicon substrate,
Soi layer and upper layer oxide layer.In order to meet design to the needs of different components, need to remove the soi layer of different zones.
The removal of soi layer is typically all the method using dry etching, first passes through the region that lithographic definition needs to etch out, then passes through dry etching
The oxide layer for etching away surface, then etches away soi layer again, due to soi layer in the shallow channel technique of preamble through peroxidating, it is past
Toward will form bent angle, i.e., after over etching, isolated groove is etched on wafer, is then filled to form isolation, such as Fig. 2 institute
Show, due to, there are also the technique for forming cushion oxide layer, will cause the soi layer near groove before trench fill and becoming circular arc
Shape, so will cause the SOI that is difficult to remove in bent angle of etching when etching, as shown in figure 3, in order to by soi layer remaining in bent angle
Etching is clean, and a direct method is to increase etch quantity, but it is excessively thin to will lead to the oxide layer left in this way, as shown in figure 4, scheming
Lower layer's oxide layer at middle arrow meaning has been etched thinning, and etching can even hurt the surface of underlying substrate monocrystalline silicon,
It is impacted to subsequent technique.
Summary of the invention
Technical problem to be solved by the present invention lies in a kind of process of FD-SOI wafer is provided, can completely remove
Soi layer does not cause SOI to remain, and does not cause to damage to lower layer's oxide layer.
To solve the above problems, the process of FD-SOI wafer of the present invention.Include:
Step 1, provides a FD-SOI wafer, and the FD-SOI wafer includes the silicon substrate and silicon substrate being made of monocrystalline silicon
On lower layer's oxide layer, soi layer and upper layer oxide layer；Isolated area is formed by trench process, is then defined using photoresist,
Open the wafer area for needing to etch.
Step 2, the window opened by photoresist, performs etching FD-SOI wafer, by the upper layer oxide layer in window
It etches away, opens the soi layer below the oxide layer of upper layer.
Step 3 removes photoresist；Using wet-etching technology by the soi layer below the upper layer oxide layer opened in window
It etches away.
A further improvement is that the trench process in the step 1 forms isolated area, it further include forming liner in the trench
Oxide layer is subsequently filled medium and forms isolated groove.
A further improvement is that etching technics uses dry etching in the step 2, in the window that photoresist is opened
Upper layer oxide layer completely remove, and over etching removes the partial SOI layer below the upper layer oxide layer, makes still remaining in window
Soi layer with certain residual volume.
A further improvement is that the wet-etching technology, is completely removed soi layer using the acid cleaning process of high selectivity ratio
Completely, not damaged to lower layer's oxide layer.
A further improvement is that the pickling, is high temperature APM solution, the i.e. mixed solution of ammonium hydroxide and hydrogen peroxide.
A further improvement is that FD- can be completely removed since acid cleaning process has very high selection when isotropism
Remaining soi layer in SOI wafer.
The process of FD-SOI wafer of the present invention is washed by the update of technique using dry etching acid adding
The group technology of etching is more easier the removal of soi layer, while will not influence the oxide skin(coating) even silicon substrate of lower layer, has
Conducive to the reliability for the controllability and device for improving technique, reduce the influence to device performance.
Detailed description of the invention
Fig. 1 is the diagrammatic cross-section with the FD-SOI wafer of isolated groove.
Fig. 2 is the etching removal technique that upper layer oxide layer and soi layer are ready for after blocking using photoresist.
Fig. 3 is using after dry etching removal soi layer, and remaining soi layer can not be etched into arc-shaped bent angle.
Fig. 4 is using dry etching, and over etching removal soi layer, and also resulting in etching to lower layer's oxide layer leads to lower layer's oxygen
Change the excessively thin schematic diagram of layer.
Fig. 5 is that the present invention is blocked using photoresist, and removes upper layer oxide layer with dry etching, exposes showing for soi layer
It is intended to.
Fig. 6 is the present invention in the schematic diagram for removing remaining soi layer using acid cleaning process.
Fig. 7 is process flow chart of the invention.
Description of symbols
1 is silicon substrate, and 2 be lower layer's oxide layer, and 3 be soi layer, and 4 be upper layer oxide layer, and 5 be isolated groove, and 6 be photoresist.
Specific embodiment
The wafer containing soi layer that existing FD-SOI technique uses is that also have lower layer's oxide layer on a silicon substrate,
Soi layer and upper layer oxide layer.Since cushion oxide layer can be made when forming traditional device isolation groove, lead to soi layer
It will become arc-shaped, traditional dry etch process in downward etching close to its edge of the position of isolated groove, due to each
The characteristics of anisotropy, arc-shaped side, top has blocking for oxide layer and that dry etching not can be removed is arc-shaped
Soi layer in position causes dry etching that can not etch completely, causes the residual of soi layer, and remaining soi layer will cause device
Failure.And if completely remove soi layer by increasing dry etching amount, and can not accurately determine etching terminal, led to quarter
Erosion, so that lower layer's oxide layer below soi layer is excessively thin, the silicon substrate being even damaged to below lower layer's oxide layer causes device
Potential failure.
The present invention provides the process of FD-SOI a kind of, can be while completely removing soi layer not to lower layer's oxide layer
It causes to damage.
The process of FD-SOI of the present invention is as follows:
Step 1, first progress preamble technique: providing a FD-SOI wafer, and the FD-SOI wafer includes to be made of monocrystalline silicon
Silicon substrate also has lower layer's oxide layer, soi layer and upper layer oxide layer from bottom to up on a silicon substrate；Pass through trench process shape
At isolated area.The isolated area is isolated groove, is to etch groove on FD-SOI wafer, then forms cushion oxide layer,
Then it carries out media filler and forms isolation structure.During forming cushion oxide layer, soi layer will lead to close to isolating trenches
There is arc-shaped in the position of slot, i.e., the side of the side of former soi layer not instead of not straight up and down becomes round and smooth drum side.So
It is defined afterwards using photoresist, opens the wafer area for needing to etch, by the region for needing to retain soi layer and need to remove soi layer
Region distinguish.
Step 2, the window opened by photoresist, performs etching FD-SOI wafer, by the upper layer oxide layer in window
It etches away, opens the soi layer below the oxide layer of upper layer.The lithographic method uses traditional dry etch process, from upper direction
The upper layer oxide layer on surface is etched removal, while removing the soi layer of part by lower etching.The dry etch process includes to pass
The physics or chemical drying method etching technics of system are controlled based on the considerations of etch rate and line width, generally use physical ion
Sputtering technology performs etching.In downward etching, the soi layer as caused by preamble technique close to the radiused of isolation trench region,
Cause be located at circular arc in soi layer due to dry etching anisotropy, blocking for top and can not be arrived by lateral etching, because
This, when dry etching is nearly completed, there are still residuals for the soi layer in circular arc.Dry etching need to only get rid of SOI in this step
The upper layer oxide layer of layer top, and soi layer is slightly etched into, soi layer is fully exposed, without considering soi layer
Etch amount.
Step 3 removes photoresist；Using wet-etching technology by the soi layer below the upper layer oxide layer opened in window
It etches away.By highly selective acid cleaning process by the soi layer being exposed all remove, due to wet-etching technology it is each to
The process characteristic of the same sex, wet-etching technology can by circular arc remaining soi layer and other be exposed to immediately below window
Soi layer completely removes, and will not be damaged to lower layer's oxide layer of lower section, will not more impact to silicon substrate.
Generally, highly selective acid cleaning process performs etching soi layer using high temperature APM solution, the APM solution
It is the mixed solution of ammonium hydroxide and hydrogen peroxide, and is reacted at moderate temperatures, the soi layer for needing to etch away on wafer is gone
Except clean.
It is of the present invention to be removed in technique in traditional SOI, after photoetching, the surface above SOI is etched away by dry etching
Then oxide layer removes photoresist, the rear acid solution (such as high temperature APM) using high selectivity ratio is come the SOI in SOI removal region
It washes off.Because being acid cleaning process, stronger selection ratio and isotropism are had than dry carving technology, corner can be effectively removed
Soi layer without to lower layer oxide layer and silicon have an impact.
The above is only a preferred embodiment of the present invention, is not intended to limit the present invention.Come for those skilled in the art
It says, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any modification, equivalent
Replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (7)
1. a kind of process of FD-SOI, it is characterised in that: include following processing step:
Step 1, provides a FD-SOI wafer, and the FD-SOI wafer includes the silicon substrate and silicon substrate being made of monocrystalline silicon
On lower layer's oxide layer, soi layer and upper layer oxide layer；Isolated area is formed by trench process, is then defined using photoresist,
Open the wafer area for needing to etch；
Step 2, the window opened by photoresist, performs etching FD-SOI wafer, and the upper layer oxide layer in window is etched
Fall, opens the soi layer below the oxide layer of upper layer；
Step 3 removes photoresist；The soi layer below the upper layer oxide layer opened in window is etched using wet-etching technology
Fall.
2. the process of FD-SOI as described in claim 1, it is characterised in that: the trench process in the step 1 is formed
Isolated area further includes forming cushion oxide layer in the trench, is subsequently filled medium and forms isolated groove.
3. the process of FD-SOI as described in claim 1, it is characterised in that: in the step 2, etching technics is using dry
Method etching, the upper layer oxide layer in the window of photoresist opening is completely removed, and over etching removes under the upper layer oxide layer
The partial SOI layer of side makes the still remaining soi layer with certain residual volume in window.
4. the process of FD-SOI as described in claim 1, it is characterised in that: the wet-etching technology, using Gao Xuan
The acid cleaning process for selecting ratio completely removes soi layer completely, not damaged to lower layer's oxide layer.
5. the process of FD-SOI as claimed in claim 4, it is characterised in that: the pickling is high temperature APM solution,
That is the mixed solution of ammonium hydroxide and hydrogen peroxide.
6. the process of FD-SOI as claimed in claim 4, it is characterised in that: since acid cleaning process has very high selection
When isotropism can completely remove soi layer remaining in FD-SOI wafer.
7. the process of FD-SOI as claimed in claim 2, it is characterised in that: the liner oxidation layer process will lead to
It is radiused that in the part close to isolated groove side can occur for soi layer, is formed to isolated groove bulging side outstanding；In subsequent dry method
When etching, bulging side outstanding causes soi layer to remain since blocking for top can not be etched into.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201910820714.XA CN110416162A (en) | 2019-08-29 | 2019-08-29 | The process of FD-SOI |
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| CN201910820714.XA CN110416162A (en) | 2019-08-29 | 2019-08-29 | The process of FD-SOI |
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Patent Citations (8)
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| CN101151725A (en) * | 2005-03-28 | 2008-03-26 | 德州仪器公司 | Building fully-depleted and partially-depleted transistors on same chip |
| CN101924110A (en) * | 2010-04-22 | 2010-12-22 | 复旦大学 | SOI (Silicon On Insulator) transistor structure of body contact and preparation method thereof |
| JP2013202559A (en) * | 2012-03-29 | 2013-10-07 | Tokyo Electron Ltd | Method for producing filter for filtration |
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Application publication date: 20191105 |