CN110400141A - Block chain digital signature method and system - Google Patents
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Abstract
The embodiment of the present invention provides block chain digital signature method and system.Above-mentioned block chain digital signature system includes primary processor and coprocessor；Primary processor is at least used to run block chain application main program；Coprocessor is as hardware acceleration unit, for running multiple digital signature subprograms；Multiple digital signature subprograms correspond to different digital signature types；The above method includes: the digital signature type belonging to the digital signature processing that block chain application main program executes needed for determining when needing to be digitally signed processing；The digital signature type determined is target number signature type；The corresponding digital signature subprogram of target number signature type is digital signature subprogram；Block chain application main program calls coprocessor operational objective digital signature subprogram, to carry out the digital signature processing of parallel and streamlined.
Description
Technical field
The present invention relates to Reconfigurable Computing Technology fields, in particular to block chain digital signature method and system.
Background technique
Due to exploding for information age data volume, the personal secrets of information and data become most worthy in each commercial field
Assets, especially more focus on the privacy and safety of data in the application of block chain.
In the application of block chain using digital signature (including but not limited to: group ranking, ring signatures, standard digital signature algorithm,
Proxy Signature etc.) realize message accuracy and non-repudiation.The basic technology and core that digital signature is applied as block chain
Algorithm, plays extremely important safety effect, and the response time of block chain application is directly affected in data processing speed, is gulped down
The amount of spitting and scalability.
Summary of the invention
In view of this, the embodiment of the present invention provides block chain digital signature method and system, to improve the number of digital signature
According to processing speed.
To achieve the above object, the embodiment of the present invention provides the following technical solutions:
A kind of block chain digital signature method is based on block chain digital signature system, the block chain digital signature system
Including primary processor and coprocessor；The primary processor is at least used to run block chain application main program；The coprocessor
As hardware acceleration unit, for running multiple digital signature subprograms；The multiple digital signature subprogram corresponds to different
Digital signature type；
The described method includes:
The primary processor runs the block chain application main program；
When needing to be digitally signed processing, at the digital signature that the block chain application main program executes needed for determining
Digital signature type belonging to reason；The digital signature type determined is target number signature type；The target number signature
The corresponding digital signature subprogram of type is digital signature subprogram；
The block chain application main program calls the coprocessor to run the target number signature subprogram, to carry out
Parallel and streamlined digital signature processing.
Optionally, the primary processor is universal cpu；The coprocessor is on-site programmable gate array FPGA.
Optionally, before the calling coprocessor runs the target number signature subprogram, the block chain is answered
It is also used to perform the following operations with main program:
Prepare pending data collection；
It creates host side and the end FPGA carries out the caching of data communication；
Auxiliary data collection is transferred to the caching；
Ready pending data collection is transferred to the caching；
Parameter information needed for the operation of the end FPGA is set；
After the calling coprocessor runs the target number signature subprogram, the block chain application main program
It is also used to perform the following operations:
After the end FPGA returns to completion signal, the implementing result at the end FPGA is read.
Optionally, the coprocessor runs the target number signature subprogram, to carry out the number of parallel and streamlined
Word signature is handled
The auxiliary data collection and the pending data collection are read from the caching；
According to the auxiliary data collection, parallel and streamlined calculating is carried out to the data that the pending data is concentrated and is grasped
Make；
The caching is written into calculating operation the data obtained；
After the calculating for the data concentrated to the pending data, is returned to host side and complete signal.
Optionally, the parameter information includes: cache size, the write-in of data and reading configuration information, the number of targets
The execution configuration information and FPGA platform information of word signature subprogram.
Optionally, before the primary processor runs the block chain application main program, the method also includes: it uses
High-level language completes the description of a plurality of types of Digital Signature Algorithms, obtains the multiple digital signature subprogram；Pass through mapping
Tool completes the automation mapping for being described to bit stream performed by FPGA of a plurality of types of Digital Signature Algorithms, generates phase
The AOCX file answered；The main program is compiled, the executable program file that can be executed on the universal cpu is generated.
Optionally, the primary processor run block chain application the main program include: can described in the universal cpu is run
Execution；It includes: that the FPGA runs the target that the coprocessor, which runs the target number signature subprogram,
The corresponding AOCX file of digital signature subprogram.
A kind of block chain digital signature system, including primary processor and as the coprocessor of hardware acceleration unit；Wherein,
The coprocessor is for running multiple digital signature subprograms；The multiple digital signature subprogram corresponds to different number label
Name type；
The primary processor is used for:
Run block chain application main program；
When needing to be digitally signed processing, the affiliated digital signature class of the digital signature processing executed needed for determining
Type；The digital signature type determined is target number signature type；The corresponding digital signature of the target number signature type
Subprogram is digital signature subprogram；
The coprocessor is called to run the target number signature subprogram, to carry out parallel and streamlined number label
Name processing.
Optionally, the primary processor is CPU；The coprocessor is on-site programmable gate array FPGA.
As it can be seen that in embodiments of the present invention, primary processor and the cooperation of collaborative process device provide the application service of block chain, wherein
Primary processor is responsible for when needing to be digitally signed processing, determines required target number from a variety of digital signature types
Signature type, and collaborative process device is called to execute the signature subprogram of target number corresponding to operational objective digital signature type,
The degree of parallelism and data processing speed of Digital Signature Algorithm can be improved in the parallel stream hydrate technology of collaborative process device, and then improves number
Data processing speed when word signature algorithm executes improves the response time, handling capacity and scalability of the application of block chain.
Detailed description of the invention
Fig. 1 is block chain digital signature system application scenarios schematic diagram provided in an embodiment of the present invention；
Fig. 2 is block chain digital signature system exemplary block diagram provided in an embodiment of the present invention；
Fig. 3 is block chain digital signature system another exemplary structure chart provided in an embodiment of the present invention；
Fig. 4 is block chain digital signature method exemplary process diagram provided in an embodiment of the present invention；
Fig. 5 is file generated exemplary diagram provided in an embodiment of the present invention；
Fig. 6 is the another exemplary flow chart of block chain digital signature method provided in an embodiment of the present invention.
Specific embodiment
For the sake of quoting and understanding, hereafter used in technical term, write a Chinese character in simplified form or abridge and be summarized as follows:
Block chain: Blockchain.Block chain is Distributed Storage, point-to-point transmission, common recognition mechanism, Encryption Algorithm
Etc. computer technologies new application mode.Block chain is a key concept of bit coin, it is substantially one and goes to center
The database of change, while the Floor layer Technology as bit coin are a string using the associated data block generated of cryptography method, often
The information of a batch bit coin network trading is contained in one data block, for verifying the validity (anti-fake) and life of its information
At next block；
OpenCL:Open Computing Language, open computing language；
DDR:Dual Data Rate, Double Data Rate synchronous DRAM；
FPGA:Field-Programmable Gate Array, field programmable gate array；
DSA:Digital Signature Algorithm, standard digital signature algorithm；
GPU:Graphics Processing Unit, graphics processor；
PCI:Peripheral Component Interconnect, Peripheral Component Interconnect standard；
PCI-E:PCI Express, PCI-E interface are a kind of interface standards more common on mainboard, are mainly mentioned at present
Supply needs the equipment that is directly communicated with CPU to use, typically to not having the function of supporting on extension mainboard；
DDRSDRAM:Double Data RateSDRAM, Double Data Rate synchronous DRAM；
A kind of DDR3: calculator memory specification.The memory article for belonging to SDRAM family, provides compared to DDR2
The higher Operating ettectiveness of SDRAM and lower voltage, are the subsequent of DDR2 SDRAM (synchronous dynamic dynamic random access memory)
Person (increases to octuple), and current popular memory article specification；
EXE File:executable program, executable program.Executable program is can to store sky in operating system
Between it is middle float positioning binary executable.It can be loaded into memory, and loaded by operating system and executed；
OpenCL:Open Computing Language, open operation language.OpenCL is first towards isomery system
It unites general the open of purpose multiple programming, free standard and a unified programmed environment, is convenient for software developer
High performance computing service device, desktop computing system, handheld device write the code of high-efficient light, and are widely used in multi-core
Other parallel processings such as processor (CPU), graphics processor (GPU), Cell type architecture and digital signal processor (DSP)
Device has vast potential for future development in the various fields such as game, amusement, scientific research, medical treatment；
GCC:GNU Compiler Collection, GNU compiler external member, including C, C++, Objective-C,
The front end of Fortran, Java, Ada and Go language also includes the library (such as libstdc++, libgcj) of these language.
GCC is used as official's compiler of GNU operating system originally, by most several classes of Unix operating system (such as Linux, BSD, Mac
OS X etc.) it is adopted as the compiler of standard；
MAC:MessageAuthenticationCode, message authentication code.
Block chain technology can be applied to that commodity are traced to the source, fields, the digital signature such as personal reference are the bases of block chain application
Technology and core algorithm.
Digital Signature Algorithm is using relatively early, technology maturation some algorithms.In Digital Signature Algorithm, signer is utilized
The key pair message of oneself is handled, and is generated digital signature (stamped signature).Receiving message is verifier, is disclosed using system
The public key of (can verify that) verifies digital signature, is used to confirmation message source and its accuracy.
Digital signature treatment process needs certain computing resource.Under the conditions of data explode, the response time is limited, energy
It is enough that user is met to the access response of data as a stern challenge with most fast speed.
To solve the above problems, the embodiment of the invention provides block chain digital signature method and systems.
Referring to Figure 1, above-mentioned block chain digital signature system concretely back-end server 102 (such as application server,
Platform Server, digital signature server), Application Scenarios-Example is as follows: user submits digital label to web server 101
Name processing request (generates information signature request or checking request), and web server 101 and back-end server 102 communicate, by rear end
Server 102 is digitally signed processing.
Fig. 2 is referred to, above-mentioned block chain digital signature system may include primary processor 1 and coprocessor 2；Wherein, main place
Reason device 1 is at least for running block chain application main program 3；And coprocessor 2 is used as hardware acceleration unit, for running multiple numbers
Word signature subprogram 4.
When needing to be digitally signed processing, block chain application main program can call coprocessor 2 to run digital signature
Subprogram, to carry out the digital signature processing of parallel and streamlined.Number can be improved in the parallel stream hydrate technology of collaborative process device
The degree of parallelism and data processing speed of signature algorithm, and then improve throughput performance when Digital Signature Algorithm executes.
In one example, Fig. 3 is referred to, block chain digital signature system is that isomery accelerates platform: primary processor 1 is logical
With CPU1 ', and coprocessor 2 is FPGA 2 '.Data communication is carried out using PCI-E interface between universal cpu 1 ' and FPGA2 ',
And using the DDR3 memory on FPGA development board as data buffer storage (Buffer).
In another example, coprocessor can also be GPU.
Digital Signature Algorithm is very suitable for parallel, streamlined acceleration processing, suitable with the calculation features of FPGA, GPU
It coincide.Therefore, the hardware acceleration unit (or for hardware circuit) for using FPGA or GPU to handle as digital signature, it is parallel
The degree of parallelism and data processing speed of Digital Signature Algorithm can be improved in streamlined processing mode, and then improves Digital Signature Algorithm and hold
Throughput performance when row.
In addition, can be easily achieved grain refined parallel by FPGA, it is equivalent to CPU and plays multiple threads.But CPU plays multiple threads
Expensive server or cluster is needed to be supported, and FPGA is not needed then, therefore, is provided using the embodiment of the present invention
Scheme can reduce hardware cost.
Below by by taking primary processor is universal cpu, coprocessor is the block chain digital signature system of FPGA as an example, to this
Technical solution provided by inventing specifically is introduced.
One kind that Fig. 4 and Fig. 5 shows the block chain digital signature method as performed by block chain digital signature system is shown
Example property process, comprising:
S0: block chain application main program is generated；
In one example, block chain application main program can be used C language and write.Block chain application main program is executable to be removed
Except digital signature processing or processing operation before, for example, scheduling, preparing pending data, data record etc..
S1: completing the description of a plurality of types of Digital Signature Algorithms using OpenCL high-level language, obtains multiple number label
Name subprogram.
Digital Signature Algorithm type is exemplary to be obtained can include: standard digital signature algorithm, allograph algorithm, Proxy Signature are calculated
Method, group ranking algorithm and ring signatures algorithm etc..Algorithms of different is applied in different field to realize its specific function, but is signed
Algorithm never changes: ensuring source and its reliability of message.
Specifically, each digital signature subprogram could be an upwardly facing FPGA platform for linux operating system
Kernel program file.
It should be noted that digital signature Processing Algorithm includes signing and verifying two parts, then in one example, with one
The corresponding Kernel program file of digital signature Processing Algorithm specifically may include the Kernel program file for signature, Yi Jiyong
In the Kernel program file of verifying.
It should be noted that since FPGA only supports OpenCL high-level language at present, the present embodiment uses OpenCL
The description of high-level language completion Digital Signature Algorithm.But FPGA, which is not precluded, in future can support the possibility of other high-level languages.This
Outside, if coprocessor is GPU, other high-level languages can also be used to complete the description of Digital Signature Algorithm.
S2: by mapping tool complete a plurality of types of Digital Signature Algorithms be described to bit stream performed by FPGA from
Dynamicization mapping, generate it is corresponding, can AOCX file (bit stream) running on the FPGA.
Specifically, AOC (Altera SDK for OpenCL) High Level Synthesis tool can be used to Kernel program file
It is compiled comprehensive (i.e. automation mapping), generates AOCX file.
In one example, if Kernel program file corresponding with a Digital Signature Algorithm includes for signature
Kernel program file, and for the Kernel program file of verifying, then AOCX file accordingly includes the AOCX for signature
File, and the AOCX file for verifying.
Specifically, AOCX file executes calculating on the digital signature core algorithm hardware circuit on FPGA.
S3: being compiled block chain application main program, generates the executable program file that can be executed on universal cpu.
Host side program is compiled specifically, GCC compiler can be used, generates EXE File.
S4: primary processor runs block chain application main program.
Specifically, being to run above-mentioned executable program file on universal cpu.
Executable program file can be loaded onto memory operation by universal cpu.
S5: when needing to be digitally signed processing, at the digital signature that block chain application main program executes needed for determining
Digital signature type belonging to reason.
Certainly, actually universal cpu runs executable program file to determine that the required digital signature executed handles institute
The digital signature type of category.
Each digital signature type can correspond to unique identification, and digital signature type can be determined by type identification.Type
Mark can carry in application request.
It should be noted that application request is the request for triggering block chain application main program and being digitally signed processing.
It is convenient for subsequent address, the digital signature type determined can be known as to target number signature type, and by target
The corresponding digital signature subprogram of digital signature type is known as digital signature subprogram.
S6: block chain application main program calls coprocessor operational objective digital signature subprogram, to carry out parallel and stream
The digital signature of aquation is handled.
Certainly, what FPGA bottom really executed is AOCX file.
As it can be seen that in embodiments of the present invention, primary processor and the cooperation of collaborative process device provide the application service of block chain, wherein
Primary processor is responsible for when needing to be digitally signed processing, determines required target number from a variety of digital signature types
Signature type, and collaborative process device is called to execute the signature subprogram of target number corresponding to operational objective digital signature type,
The degree of parallelism and data processing speed of Digital Signature Algorithm can be improved in the parallel stream hydrate technology of collaborative process device, and then improves number
Data processing speed when word signature algorithm executes improves the response time, handling capacity and scalability of the application of block chain.
Use FPGA as coprocessor, can effectively promote the execution performance of digital signature core algorithm, it is above-mentioned from
It the time that dynamicization mapping mode can effectively shorten when Digital Signature Algorithm to be deployed to the isomery acceleration platform based on FPGA, mentions
The high product R&D cycle.
Concrete operations performed by universal cpu operation executable program file and FPGA operation AOCX text is described below
Concrete operations performed by part.
Fig. 6 is referred to, universal cpu runs concrete operations performed by executable program file can include:
S601: prepare pending data collection.
Aforementioned to be referred to, digital signature processing includes signature and verifying, and for signature process, pending data collection may include
Data to be signed；And for verification process, pending data collection may include data to be verified (signed data).
S602: the caching of creation host side and the end FPGA progress data communication.
The caching is located on the DDR memory of FPGA development board.
S603: auxiliary data collection is transferred to above-mentioned caching.
Auxiliary data collection participates in the operation of digital signature processing.By taking signature process as an example, auxiliary data collection can include: will be to
Used in the blocking information (instruction by data to be signed with much piecemeals) of signed data, private key for user and signature process
When function (such as hash function) information such as calls.
In verifying, auxiliary data collection includes signature system parameter (modulus, number field etc.) and public key.
S604: ready pending data collection is transferred to above-mentioned caching.
It should be noted that auxiliary data collection will be transmitted prior to pending data collection.
S605: the setting end FPGA runs required parameter information.
Wherein, parameter information can include: cache size, data write-in and read configuration information (such as when be written, what
When reading, the data volume of write-once, the data volume once read etc.), the execution configuration information of kernel file (for example, what
When call) and FPGA platform information (such as FPGA board model).
S606: digital signature type belonging to the digital signature processing executed needed for determining calls the end FPGA operational objective
Digital signature subprogram.
Specifically, enabling signal first can be sent to FPGA, the end FPGA operational objective digital signature subprogram is recalled.
FPGA runs concrete operations performed by AOCX file then can include:
S607: above-mentioned auxiliary data collection and pending data collection are read.
It is aforementioned to refer to, it can be used the DDR of FPGA as caching, then in this step, can be read from the DDR batch of FPGA auxiliary
The on piece for helping data set and pending data collection to FPGA caches.
S608: according to auxiliary data collection, parallel and streamlined calculating operation is carried out to the data in data set to be processed.
S609: above-mentioned caching is written into calculating operation the data obtained；
S610: it to after the calculating of the data in data set to be processed, is returned to host side and completes signal.
After signature or verification step are finished, it can be returned to host side and complete signal.It is read in caching by host side
Data.
Then concrete operations performed by universal cpu operation executable program file further include:
S611: after receiving the end FPGA and returning to completion signal, the data that digital signature is handled are read from caching；
S612: it completes digital signature procedure and exports corresponding signing messages or verification result.
Professional further appreciates that, unit described in conjunction with the examples disclosed in the embodiments of the present disclosure
And model step, can be realized with electronic hardware, computer software, or a combination of the two, in order to clearly demonstrate hardware and
The interchangeability of software generally describes each exemplary composition and step according to function in the above description.These
Function is implemented in hardware or software actually, the specific application and design constraint depending on technical solution.Profession
Technical staff can use different methods to achieve the described function each specific application, but this realization is not answered
Think beyond the scope of this invention.
The step of method described in conjunction with the examples disclosed in this document or model, can directly be held with hardware, processor
The combination of capable software module or the two is implemented.Software module can be placed in random access memory (RAM), memory, read-only deposit
Reservoir (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, WD-ROM or technology
In any other form of storage medium well known in field.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (9)
1. a kind of block chain digital signature method, which is characterized in that be based on block chain digital signature system, the block chain number
Signature system includes primary processor and coprocessor；The primary processor is at least used to run block chain application main program；It is described
Coprocessor is as hardware acceleration unit, for running multiple digital signature subprograms；The multiple digital signature subprogram pair
Answer different digital signature types；
The described method includes:
The primary processor runs the block chain application main program；
When needing to be digitally signed processing, the digital signature that the block chain application main program executes needed for determining handles institute
The digital signature type of category；The digital signature type determined is target number signature type；The target number signature type
Corresponding digital signature subprogram is digital signature subprogram；
The block chain application main program calls the coprocessor to run the target number signature subprogram, parallel to carry out
It is handled with the digital signature of streamlined.
2. the method as described in claim 1, which is characterized in that the primary processor is universal cpu；The coprocessor is existing
Field programmable gate array FPGA.
3. method according to claim 2, which is characterized in that run the target number signature in the calling coprocessor
Before subprogram, the block chain application main program is also used to perform the following operations:
Prepare pending data collection；
It creates host side and the end FPGA carries out the caching of data communication；
Auxiliary data collection is transferred to the caching；
Ready pending data collection is transferred to the caching；
Parameter information needed for the operation of the end FPGA is set；
After the calling coprocessor runs the target number signature subprogram, the block chain application main program is also used
In performing the following operations:
After the end FPGA returns to completion signal, the implementing result at the end FPGA is read.
4. method as claimed in claim 3, which is characterized in that the coprocessor runs the sub- journey of the target number signature
Sequence, handle with the digital signature of streamlined parallel and include:
The auxiliary data collection and the pending data collection are read from the caching；
According to the auxiliary data collection, parallel and streamlined calculating operation is carried out to the data that the pending data is concentrated；
The caching is written into calculating operation the data obtained；
After the calculating for the data concentrated to the pending data, is returned to host side and complete signal.
5. method as claimed in claim 3, which is characterized in that the parameter information includes:
Cache size, data write-in and read configuration information, the target number signature subprogram execution configuration information with
And FPGA platform information.
6. such as the described in any item methods of claim 2-5, which is characterized in that
Before the primary processor runs the block chain application main program, the method also includes:
The description that a plurality of types of Digital Signature Algorithms are completed using high-level language obtains the multiple digital signature subprogram；
The automatic of bit stream performed by FPGA is described to by what mapping tool completed a plurality of types of Digital Signature Algorithms
Change mapping, generates corresponding AOCX file；
The main program is compiled, the executable program file that can be executed on the universal cpu is generated.
7. method as claimed in claim 6, which is characterized in that
It includes: that the universal cpu runs the executable program text that the primary processor, which runs the block chain application main program,
Part；
It includes: that the FPGA runs target number signature that the coprocessor, which runs the target number signature subprogram,
The corresponding AOCX file of program.
8. a kind of block chain digital signature system, which is characterized in that at including primary processor and as the association of hardware acceleration unit
Manage device；Wherein, the coprocessor is for running multiple digital signature subprograms；The multiple digital signature subprogram is corresponding not
Same digital signature type；
The primary processor is used for:
Run block chain application main program；
When needing to be digitally signed processing, the affiliated digital signature type of the digital signature processing executed needed for determining；Really
The digital signature type made is target number signature type；The corresponding digital signature subprogram of the target number signature type
For digital signature subprogram；
The coprocessor is called to run the target number signature subprogram, to carry out at the parallel and digital signature of streamlined
Reason.
9. system as claimed in claim 8, which is characterized in that the primary processor is CPU；The coprocessor is that scene can
Program gate array FPGA.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910575768.4A CN110400141A (en) | 2019-06-28 | 2019-06-28 | Block chain digital signature method and system |
| PCT/CN2019/108917 WO2020258567A1 (en) | 2019-06-28 | 2019-09-29 | Blockchain digital signing method and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910575768.4A CN110400141A (en) | 2019-06-28 | 2019-06-28 | Block chain digital signature method and system |
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| Publication Number | Publication Date |
|---|---|
| CN110400141A true CN110400141A (en) | 2019-11-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201910575768.4A Withdrawn CN110400141A (en) | 2019-06-28 | 2019-06-28 | Block chain digital signature method and system |
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| Country | Link |
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| CN (1) | CN110400141A (en) |
| WO (1) | WO2020258567A1 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111459871A (en) * | 2020-04-01 | 2020-07-28 | 济南浪潮高新科技投资发展有限公司 | FPGA heterogeneous computation based block chain acceleration system and method |
| CN111510306A (en) * | 2020-06-30 | 2020-08-07 | 杭州智块网络科技有限公司 | Offline signature method and device based on block chain |
| WO2020258567A1 (en) * | 2019-06-28 | 2020-12-30 | 苏州浪潮智能科技有限公司 | Blockchain digital signing method and system |
| CN112636926A (en) * | 2020-12-24 | 2021-04-09 | 网易（杭州）网络有限公司 | Signature processing method and device and electronic equipment |
| CN114944016A (en) * | 2022-05-31 | 2022-08-26 | 南方电网深圳数字电网研究院有限公司 | Method and device for acquiring electronic signature |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10447770B2 (en) * | 2017-05-30 | 2019-10-15 | Verizon Patent And Licensing Inc. | Blockchain micro-services framework |
| US10761877B2 (en) * | 2017-07-21 | 2020-09-01 | Intel Corporation | Apparatuses, methods, and systems for blockchain transaction acceleration |
| CN107491317A (en) * | 2017-10-10 | 2017-12-19 | 郑州云海信息技术有限公司 | A kind of symmetrical encryption and decryption method and systems of AES for accelerating platform based on isomery |
| CN108063758A (en) * | 2017-11-27 | 2018-05-22 | 众安信息技术服务有限公司 | For the node in the signature verification method of block chain network and block chain network |
| CN110400141A (en) * | 2019-06-28 | 2019-11-01 | 苏州浪潮智能科技有限公司 | Block chain digital signature method and system |
-
2019
- 2019-06-28 CN CN201910575768.4A patent/CN110400141A/en not_active Withdrawn
- 2019-09-29 WO PCT/CN2019/108917 patent/WO2020258567A1/en active Application Filing
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020258567A1 (en) * | 2019-06-28 | 2020-12-30 | 苏州浪潮智能科技有限公司 | Blockchain digital signing method and system |
| CN111459871A (en) * | 2020-04-01 | 2020-07-28 | 济南浪潮高新科技投资发展有限公司 | FPGA heterogeneous computation based block chain acceleration system and method |
| CN111510306A (en) * | 2020-06-30 | 2020-08-07 | 杭州智块网络科技有限公司 | Offline signature method and device based on block chain |
| CN112636926A (en) * | 2020-12-24 | 2021-04-09 | 网易（杭州）网络有限公司 | Signature processing method and device and electronic equipment |
| CN112636926B (en) * | 2020-12-24 | 2022-05-27 | 网易（杭州）网络有限公司 | Signature processing method and device and electronic equipment |
| CN114944016A (en) * | 2022-05-31 | 2022-08-26 | 南方电网深圳数字电网研究院有限公司 | Method and device for acquiring electronic signature |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020258567A1 (en) | 2020-12-30 |
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