CN110391143A - Semiconductor package and its packaging method - Google Patents

Semiconductor package and its packaging method Download PDF

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Publication number
CN110391143A
CN110391143A CN201910591921.2A CN201910591921A CN110391143A CN 110391143 A CN110391143 A CN 110391143A CN 201910591921 A CN201910591921 A CN 201910591921A CN 110391143 A CN110391143 A CN 110391143A
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CN
China
Prior art keywords
island
pin
stationed
support plate
mask layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910591921.2A
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Chinese (zh)
Inventor
杨志强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dongguan Chain Core Semiconductor Technology Co Ltd
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Dongguan Chain Core Semiconductor Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Dongguan Chain Core Semiconductor Technology Co Ltd filed Critical Dongguan Chain Core Semiconductor Technology Co Ltd
Priority to CN201910591921.2A priority Critical patent/CN110391143A/en
Publication of CN110391143A publication Critical patent/CN110391143A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4885—Wire-like parts or pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4885—Wire-like parts or pins
    • H01L21/4889—Connection or disconnection of other leads to or from wire-like parts, e.g. wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

This application discloses a kind of semiconductor package and its packaging methods.Method for packaging semiconductor includes: offer support plate, has first surface and second surface；Mask layer is formed on one surface of support plate；Metal layer is prepared on one surface of support plate；Remove mask layer；Stationed on the island and pin is formed on one surface of support plate；Chip is arranged on stationed on the island；Disclosed herein as well is a kind of semiconductor packages prepared using the above method.Thickness of detector can be reduced using this method for packaging semiconductor, realize device miniaturization；The preparation for also helping irregular encapsulating structure stationed on the island, realizes the preparation of special structure devices stationed on the island.

Description

Semiconductor package and its packaging method
Technical field
This application involves semiconductor field more particularly to a kind of method for packaging semiconductor and its structures.
Background technique
Semiconductor devices slimming, lightness and more environmentally friendly manufacturing method are Developing directions.Currently, semiconductor The size of device and semiconductor packaging are closely related.It realizes that semiconductor devices is lightening, semiconductor packages will be required Industry develops device to lighter, thinner direction, i.e., proposes the requirement of more Gao Gengxin to semiconductor packaging.
There are many encapsulate pattern, quad flat non-pin package (QFN, Quad Flat No-lead for semiconductor devices It Package) is one of currently used packaging method.
QFN is a kind of leadless packages, is in square or rectangular, and package bottom central location usually has a large area naked The pad of dew can be used for thermally conductive, to have realization to be electrically connected around the encapsulation periphery of pad conductive welding disk.Due to inner core The pin of piece and packaging pin conductive path are short, and routing resistance is very low in electrodynamic capacity and packaging body, so QFN encapsulation can mention For outstanding electrical property and heat dissipation performance.Meanwhile QFN packaging is small in size, and it is light-weight, it is very suitable to answer Yu Shouji, it is digital The high-density printed circuit board of the portable compact electronics equipment such as camera.
Conventional QFN (i.e. chip bearing area) stationed on the island and pin figure (i.e. lead electrical connection area), by etching metal The mode of layer (common copper sheet) is formed.Copper sheet forms the structure with part hollow out (being open) after overetch.To guarantee erosion Stationed on the island, pin configuration is stable, reliable after quarter, copper sheet need to meet certain thickness, and otherwise stationed on the island, pin figure exists from copper sheet On the risk that falls off, to influence device performance.In addition, when support plate surface forms stationed on the island, in different units group it is stationed on the island, draw It needs copper product to connect between leg structure, greatly limits arrangement mode of the stationed on the island, pin configuration on support plate.
Since there are above-mentioned technical problems for QFN encapsulation, so that QFN package dimension is thicker, it is difficult to it is thick that device further be thinned Degree meets thinner package requirements；Meanwhile QFN encapsulates the arrangement of stationed on the island, pin configuration there are certain limitations, it is difficult to be suitable for Encapsulating structure with irregular or random pin, that is, be dfficult to apply in the device that pin need to customize；
In addition, QFN technique is relative complex and needs to be easy to cause heavy metal pollution, environmental friendliness using electroplating technology It is lower, do not meet the development trend for pollution-free industry.
Summary of the invention
The embodiment of the present application provides a kind of semiconductor package and its packaging method, can reduce thickness of detector, into one Step realizes device miniaturization.
On the one hand, a kind of semiconductor package, including metal layer, chip and lead are provided；Metal layer includes staying Island and pin configuration；Chip is provided on stationed on the island, pin configuration with lead for being electrically connected.
On the other hand, a kind of method for packaging semiconductor is provided, comprising:
Support plate is provided, there are first surface and second surface；
Setting has patterned mask layer on support plate first surface；
Metal layer is prepared on support plate first surface；
Remove mask layer；
Stationed on the island and pin figure is formed on support plate first surface；
Chip is arranged on stationed on the island；
Lead is set, and lead one end is electrically connected with chip far from the surface of support plate, the other end is electrically connected with pin figure；
Packaging body is set, and packaging body at least partly coats stationed on the island, pin figure, chip and lead
Remove support plate.
According to technical solution provided by the embodiments of the present application, encapsulation body thickness can be further decreased, is prepared smaller Device, simultaneously, additionally it is possible to according to the actual needs of device customize pin, with meet have different pin out requirements chip seal Dress.
Other features and advantage will illustrate in the following description, also, partly become from specification It obtains it is clear that being understood and implementing the application.The purpose of the application and other advantages can be by specifications, right Specifically noted structure is achieved and obtained in claim and attached drawing.
Detailed description of the invention
Attached drawing is used to provide to further understand technical scheme, and constitutes part of specification, with this The embodiment of application is used to explain the technical solution of the application together, does not constitute the limitation to technical scheme.
Fig. 1 to Fig. 8 show the structural schematic diagram of one embodiment encapsulating structure making step of the application；
Fig. 9 show the semiconductor package of the embodiment of the present application；
Description of symbols:
100- support plate；
110- first surface；
120- second surface；
200- mask layer；
210- opening；
211 chip bearing regions；
The electric coupling area 212-
300- metal layer；
310- is stationed on the island；
320- pin figure；
400- chip；
500- lead；
600- packaging body；
700- Cutting Road.
Specific embodiment
Below with reference to embodiment and attached drawing to the technical effect of design of the invention, specific system, method and generation into Row clearly and completely describes, to be completely understood by the purpose of the present invention, feature and effect.Obviously, described embodiment is A part of the embodiments of the present invention, rather than whole embodiments, based on the embodiment of the present invention, those skilled in the art is not Other embodiments obtained, belong to the scope of protection of the invention under the premise of making the creative labor.
It should be noted that unless otherwise specified, in embodiment used in the "an" of singular, " described " and "the" is also intended to including most forms, unless the context clearly indicates other meaning.In addition, unless otherwise defined, this paper institute All technical and scientific terms used are identical as the normally understood meaning of those skilled in the art.This paper specification Used in term be intended merely to description specific embodiment, be not intended to be limiting of the invention.Term as used herein "and/or" includes the arbitrary combination of one or more relevant listed items.
It should be appreciated that be referred to as " being set to " another element when element, it can directly on the other element or There may also be another elements placed in the middle.When an element is considered as " connection " another element, it, which can be, directly connects It is connected to another element or may be simultaneously present another element placed in the middle.Term as used herein " vertically ", " level ", "left", "right" and similar statement for illustrative purposes only, be not meant to be the only embodiment.
As shown in Figure 1, providing, there is the encapsulation of first surface 110 and the second surface 120 opposite with first surface 110 to carry Plate 100, the preferred metal substrate of support plate 100.It, can also be to the one of support plate 100 in order to further decrease the difficulty of removing support plate 100 Surface is surface-treated, and to reduce the affinity of support plate 100, is prepared for subsequent technique；It is preferred that a surface of support plate 100 Carry out oxidation processes, improve support plate 100 and metal/encapsulating material affinity, convenient for it is subsequent by support plate 100 from metal layer 300, it is removed in the contact surface of packaging body 600.
As shown in Fig. 2, mask layer 200 is arranged on support plate 100；Mask layer 200 has the opening of multiple exposed support plates 100 210；Multiple openings 210, which at least have, is used to form chip bearing region 211 and for electric coupling area 212.Mask layer 200 can Think the screen printing template being placed on support plate 100.Different figures can be arranged in screen printing template according to different encapsulating structures Shape, to needed for being formed stationed on the island 310 and pin figure 320.
As shown in figure 3, forming metal layer 300 on the support plate 100 for be provided with mask layer 200, partial metal layers 300 are arranged In opening 210；Metal material can be printed on support plate 100 by metal layer 300 by mode of printing by mask layer 200.
As shown in figure 4, removing mask layer 200, the metal material left forms stationed on the island 310 and pinouts on support plate 100 Shape 320；Between each stationed on the island 310, it is mutually indepedent between each pin figure 320 and between each stationed on the island 310 and each pin, and have There is an interval of certain distance, i.e., is connected between each stationed on the island 310, each pin figure 320 without excess metal material.Remove mask layer After 200, it can also be sintered technique, so that figure shapes on support plate 100.
Stationed on the island 310 and pin figure 320 are formed using the above method, only need to guarantee 100 rigidity of support plate and/or thickness i.e. Can, there is no limit for rigidity and/or thickness to metal layer, therefore the thickness of stationed on the island 310, pin 320 can be made thinner；Due to Support plate 100 will be stripped after the completion of prepared by integral device, i.e., the thickness of support plate 100 does not influence device integral thickness, therefore, adopts The thickness of encapsulating structure can be reduced in aforementioned manners.
The above method when 100 surface of support plate prepares stationed on the island 310, pin figure 320, in different units group it is stationed on the island 310, Between pin figure 320 without excess metal material connect, stationed on the island 310 and pin figure 320 on support plate 100 arrangement limit System is less, and the pin limitation of corresponding irregular encapsulating structure also can be smaller.
As shown in figure 5, chip 400 is bonded on stationed on the island 310 by binding material；Using bonding wire craft, pass through lead 500 are electrically connected the solder joint of chip 400 with pin figure 320, to realize chip and external electrical connections.
As shown in fig. 6, packing colloid 600 is at least partly covered on support plate 100 by sealing adhesive process, and by chip 400 and bonding wire 500 seal；Packing colloid 600 has also filled up the interval between each stationed on the island 310 and pin figure 320, and stationed on the island 310 It is electrically insulated from each other with pin 320.
As shown in fig. 7, support plate 100 and packed colloid 600 are coated on interior entire packaging part point by stripping technology From.For affinity processing can be carried out in advance to 100 surface of support plate convenient for removing, reduce damage of the removing to packaging.
As shown in figure 8, cutting packaging body along Cutting Road 700 by cutting technique, each independent QFN packaging part is formed.
Referring to Fig. 9, another embodiment of the application discloses a kind of semiconductor package, including stationed on the island 310 and pinouts Shape 320, chip 400, lead 500 and packaging body 600.Stationed on the island 310 and pin figure 320 be prepared by metal layer 300, And it is electrically insulated from each other.Chip 400 is arranged on stationed on the island 310 by binding material.500 both ends of lead respectively with table on chip 400 Face and pin figure 320 are electrically connected.600 coating chip 400 of packaging body, lead 500 and part stationed on the island 310 and pin figure 320, stationed on the island 310 and pin figure 320 far from chip 400 surface exposure.
The above, only presently preferred embodiments of the present invention, the invention is not limited to above embodiment, as long as It reaches technical effect of the invention with identical means, all within the spirits and principles of the present invention, any modification for being made, Equivalent replacement, improvement etc., should be included within the scope of the present invention.Its technical solution within the scope of the present invention And/or embodiment can have a variety of different modifications and variations.

Claims (10)

1. a kind of method for packaging semiconductor: including:
It provides an encapsulating carrier plate (100), encapsulating carrier plate (100) at least surface is provided with peelable metal material and encapsulation The first surface (110) of material；
It is formed on the first surface (110) patterned mask layer (200), the patterned mask layer (200) has more The opening (210) of a exposure first surface (110)；
A metal layer (300) are formed on the patterned mask layer (200), at least partly described metal layer (300) filling is opened Mouth (210)；
It removes the patterned mask layer (200), forms (310) stationed on the island and pin (320)；
Chip (400) are set on (310) stationed on the island；
The lead (500) of connection chip (400) solder joint and the pin (320) is set.
2. method for packaging semiconductor as described in claim 1, it is characterised in that: further include:
Packing colloid 600 is formed, covers the first surface (110) of the support plate (100), covering is arranged in the first surface (110) (310) stationed on the island, pin (320), chip (400) and lead (500) on.
3. method for packaging semiconductor as described in claim 1, it is characterised in that: further include:
Oxidation processes are carried out to encapsulating carrier plate (100) first surface (110), to reduce surface affinity.
4. method for packaging semiconductor as described in claim 1, it is characterised in that:
The patterned mask layer (200) is the screen printing template being placed on encapsulating carrier plate (100) first surface (110).
5. method for packaging semiconductor as described in claim 1, it is characterised in that:
Between each (310) stationed on the island, between each pin (320), it is mutually indepedent between (310) stationed on the island and pin (320).
6. method for packaging semiconductor as described in claim 1, it is characterised in that:
Each pin (320) array can be irregular arrangement.
7. method for packaging semiconductor as described in claim 1, it is characterised in that:
The removal patterned mask layer (200) further includes to described stationed on the island after forming (310) stationed on the island and pin (320) (310) and pin (320) is sintered.
8. method for packaging semiconductor as described in claim 1, it is characterised in that:
Using the lead (500) of bonding wire craft connection chip (400) solder joint and the pin (320).
9. a kind of semiconductor package being fabricated using method as described in claim 1.
10. a kind of semiconductor package being fabricated using method as claimed in claim 2.
CN201910591921.2A 2019-07-02 2019-07-02 Semiconductor package and its packaging method Pending CN110391143A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910591921.2A CN110391143A (en) 2019-07-02 2019-07-02 Semiconductor package and its packaging method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910591921.2A CN110391143A (en) 2019-07-02 2019-07-02 Semiconductor package and its packaging method

Publications (1)

Publication Number Publication Date
CN110391143A true CN110391143A (en) 2019-10-29

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Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113380638A (en) * 2021-05-21 2021-09-10 苏州通富超威半导体有限公司 Method for setting through hole on packaging body and method for preparing packaging body
CN113991004A (en) * 2021-10-26 2022-01-28 东莞市中麒光电技术有限公司 LED substrate manufacturing method, LED substrate, LED device manufacturing method and LED device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102460722A (en) * 2009-06-05 2012-05-16 株式会社半导体能源研究所 Photoelectric conversion device and method for manufacturing the same
CN103403864A (en) * 2011-02-23 2013-11-20 德克萨斯仪器股份有限公司 Semiconductor packages with agglomerate terminals
CN103907185A (en) * 2011-08-11 2014-07-02 联达科技控股有限公司 Lead carrier with multi-material print formed package components
CN107960132A (en) * 2015-05-04 2018-04-24 由普莱克斯有限公司 Leaded carriers with printed and formed package parts and conductive path redistribution structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102460722A (en) * 2009-06-05 2012-05-16 株式会社半导体能源研究所 Photoelectric conversion device and method for manufacturing the same
CN103403864A (en) * 2011-02-23 2013-11-20 德克萨斯仪器股份有限公司 Semiconductor packages with agglomerate terminals
CN103907185A (en) * 2011-08-11 2014-07-02 联达科技控股有限公司 Lead carrier with multi-material print formed package components
CN107960132A (en) * 2015-05-04 2018-04-24 由普莱克斯有限公司 Leaded carriers with printed and formed package parts and conductive path redistribution structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113380638A (en) * 2021-05-21 2021-09-10 苏州通富超威半导体有限公司 Method for setting through hole on packaging body and method for preparing packaging body
CN113991004A (en) * 2021-10-26 2022-01-28 东莞市中麒光电技术有限公司 LED substrate manufacturing method, LED substrate, LED device manufacturing method and LED device

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Application publication date: 20191029