CN110380598A - Device pressure resistance improvement method and device based on mixing dynamic electric voltage balance - Google Patents
Device pressure resistance improvement method and device based on mixing dynamic electric voltage balance Download PDFInfo
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- CN110380598A CN110380598A CN201910623756.4A CN201910623756A CN110380598A CN 110380598 A CN110380598 A CN 110380598A CN 201910623756 A CN201910623756 A CN 201910623756A CN 110380598 A CN110380598 A CN 110380598A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- Electronic Switches (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of device pressure resistance improvement methods and device based on mixing dynamic electric voltage balance, wherein, this method comprises: Metal-Oxide Semiconductor field effect transistor is carried out processing of connecting with active clamping circuir and passive RCD buffer circuit respectively in the circuit for including Metal-Oxide Semiconductor field effect transistor；The drain-source voltage of Metal-Oxide Semiconductor field effect transistor is obtained, if drain-source voltage is greater than the breakdown voltage of the Zener diode in active clamping circuir, determines drain-source voltage clamper in clamp voltage value；Due to voltage spikes caused by when the Zener diode in active clamping circuir is connected is absorbed by passive RCD buffer circuit, so that drain-source voltage is stablized in clamp voltage value.This method can greatly improve converters switching voltage grade, and can reduce the weight and volume of converters.
Description
Technical field
The present invention relates to power electronics field, in particular to a kind of device pressure resistance based on mixing dynamic electric voltage balance
Improvement method and device.
Background technique
The power semiconductor made of the materials such as broad stopband power semiconductor SiC, GaN, because having switching speed
Fastly, the advantages that loss is small is increasingly valued by people.Due to the limitation of SiC manufacturing process, in high-voltage applications, SiC's
Withstanding voltage is always held at lower level.Currently, the withstanding voltage highest of commercialization SiC-MOSFET is about 1700V.Cause
This, improves voltage class using the method for series connection SiC-MOSFET, especially in the higher occasion of network voltage, has important
Meaning.Stable state and dynamic electric voltage balance are two hang-ups in SiC-MOSFET concatenation.Steady state voltage balance only needs
MOSFET drain electrode and one in parallel of source electrode two sides are much smaller than the resistance of MOSFET equivalent resistance, therefore, dynamic electric voltage balance
The problem of thing series connection in be more difficult to solve the problems, such as.The method for solving dynamic electric voltage equilibrium problem has passive snubber circuit, active door
Control circuit, active voltage clamp and driven with current sources etc..Since SiC-MOSFET switching speed is fast, in extremely short switch time
Feedback difficult to realize, therefore active gate is not appropriate for series connection SiC-MOSFET.It is in serial semiconductor using passive snubbers
One of most simple, most reliable balance of voltage method, but it is bulky, and be lost larger.
Summary of the invention
The present invention is directed to solve at least some of the technical problems in related technologies.
For this purpose, an object of the present invention is to provide a kind of device pressure resistance raising sides based on mixing dynamic electric voltage balance
Method, this method can greatly improve converters switching voltage grade, and can reduce the weight of converters
Amount and volume.
It is another object of the present invention to propose a kind of device pressure resistance raising device based on mixing dynamic electric voltage balance.
In order to achieve the above objectives, one aspect of the present invention embodiment proposes a kind of device based on mixing dynamic electric voltage balance
Pressure-resistant improvement method, comprising:
In the circuit for including Metal-Oxide Semiconductor field effect transistor, by the Metal-Oxide Semiconductor field
Effect transistor carries out processing of connecting with active clamping circuir and passive RCD buffer circuit respectively；
The drain-source voltage of the Metal-Oxide Semiconductor field effect transistor is obtained, if the drain-source voltage is greater than institute
When stating the breakdown voltage of the Zener diode in active clamping circuir, determine the drain-source voltage clamper in clamp voltage value；With
And
Caused by being absorbed when the Zener diode in the active clamping circuir is connected by the passive RCD buffer circuit
Due to voltage spikes, so that the drain-source voltage is stablized in the clamp voltage value.
The device pressure resistance improvement method based on mixing dynamic electric voltage balance of the embodiment of the present invention, by concatenated SiC
Active clamp and passive snubber technology are used in MOSFET simultaneously, the deficiency of conventional method is overcome, electric power can be greatly improved
Electronic converter switching voltage grade.On the one hand help to further increase the space utilization rate of converters, into one
Step reduces the weight and volume of converters, improves whole power density；On the other hand facilitate to reduce converter
The difficulty of internal structure design.In summary two o'clock can greatly improve the insulation performance of converters, improve its work
Make voltage class and power density.
In addition, the device pressure resistance improvement method according to the above embodiment of the present invention based on mixing dynamic electric voltage balance may be used also
With following additional technical characteristic:
Further, in one embodiment of the invention, the active voltage clamp circuit by the Zener diode,
Diode and clamp resistance composition.
Further, in one embodiment of the invention, the clamp voltage value are as follows:
VDS=VBR+IGDRGD+VGS
Wherein, IGDTo pass through the electric current of the clamp resistance, VBRFor the breakdown voltage of the Zener diode, VGSFor institute
State Metal-Oxide Semiconductor field effect transistor gate source voltage, RGDFor the resistance value of the clamp resistance.
Further, in one embodiment of the invention, the diode in the active voltage clamp circuit point
It is not connected with the cathode of the drain electrode of the Metal-Oxide Semiconductor field effect transistor and the Zener diode；
The clamp resistance respectively with the grid and the Zener two of the Metal-Oxide Semiconductor field effect transistor
The anode of pole pipe is connected.
Further, in one embodiment of the invention, described active clamping circuir one end and the metal-oxide
The grid of semiconductor field effect transistor is connected, the drain electrode of the other end and the Metal-Oxide Semiconductor field effect transistor
It is connected；
Described passive RCD buffer circuit one end is connected with the drain electrode of the Metal-Oxide Semiconductor field effect transistor,
The other end is connected with the source electrode of the Metal-Oxide Semiconductor field effect transistor.
In order to achieve the above objectives, another aspect of the present invention embodiment proposes a kind of device based on mixing dynamic electric voltage balance
Part pressure resistance improves device, comprising:
Deployment module, for include Metal-Oxide Semiconductor field effect transistor circuit in, by the metal-
Oxide semiconductor field effect transistor carries out processing of connecting with active clamping circuir and passive RCD buffer circuit respectively；
First processing module, for obtaining the drain-source voltage of the Metal-Oxide Semiconductor field effect transistor, if institute
When stating breakdown voltage of the drain-source voltage greater than the Zener diode in the active clamping circuir, the drain-source voltage clamper is determined
In clamp voltage value；
Second processing module, for absorbing the Zener in the active clamping circuir by the passive RCD buffer circuit
Due to voltage spikes caused by when diode current flow, so that the drain-source voltage is stablized in the clamp voltage value.
The device pressure resistance based on mixing dynamic electric voltage balance of the embodiment of the present invention improves device, by concatenated SiC
Active clamp and passive snubber technology are used in MOSFET simultaneously, the deficiency of conventional method is overcome, electric power can be greatly improved
Electronic converter switching voltage grade.On the one hand help to further increase the space utilization rate of converters, into one
Step reduces the weight and volume of converters, improves whole power density；On the other hand facilitate to reduce converter
The difficulty of internal structure design.In summary two o'clock can greatly improve the insulation performance of converters, improve its work
Make voltage class and power density.
May be used also in addition, the device pressure resistance according to the above embodiment of the present invention based on mixing dynamic electric voltage balance improves device
With following additional technical characteristic:
Further, in one embodiment of the invention, the active voltage clamp circuit by the Zener diode,
Diode and clamp resistance composition.
Further, in one embodiment of the invention, the clamp voltage value are as follows:
VDS=VBR+IGDRGD+VGS
Wherein, IGDTo pass through the electric current of the clamp resistance, VBRFor the breakdown voltage of the Zener diode, VGSFor institute
State Metal-Oxide Semiconductor field effect transistor gate source voltage, RGDFor the resistance value of the clamp resistance.
Further, in one embodiment of the invention, the diode in the active voltage clamp circuit point
It is not connected with the cathode of the drain electrode of the Metal-Oxide Semiconductor field effect transistor and the Zener diode；
The clamp resistance respectively with the grid and the Zener two of the Metal-Oxide Semiconductor field effect transistor
The anode of pole pipe is connected.
Further, in one embodiment of the invention, described active clamping circuir one end and the metal-oxide
The grid of semiconductor field effect transistor is connected, the drain electrode of the other end and the Metal-Oxide Semiconductor field effect transistor
It is connected；
Described passive RCD buffer circuit one end is connected with the drain electrode of the Metal-Oxide Semiconductor field effect transistor,
The other end is connected with the source electrode of the Metal-Oxide Semiconductor field effect transistor.
The additional aspect of the present invention and advantage will be set forth in part in the description, and will partially become from the following description
Obviously, or practice through the invention is recognized.
Detailed description of the invention
Above-mentioned and/or additional aspect and advantage of the invention will become from the following description of the accompanying drawings of embodiments
Obviously and it is readily appreciated that, in which:
Fig. 1 is the device pressure resistance improvement method process based on mixing dynamic electric voltage balance according to one embodiment of the invention
Figure；
Fig. 2 is the dynamic voltage-balancing topology theory figure according to one embodiment of the invention；
Fig. 3 is the particular circuit configurations figure according to one embodiment of the invention；
Fig. 4 is the driving circuit pictorial diagram according to one embodiment of the invention；
Fig. 5 is the main topological circuit pictorial diagram according to one embodiment of the invention；
Fig. 6 is imitative according to the drain-source voltage of two MOSFET when not using balance of voltage method of one embodiment of the invention
True result figure；
Fig. 7 is to emulate knot according to the drain-source voltage only with two MOSFET when clamp circuit of one embodiment of the invention
Fruit figure；
Fig. 8 is the drain-source voltage using two MOSFET when mixed-voltage balance method according to one embodiment of the invention
Simulation result diagram；
Fig. 9 is the drain-source voltage using two MOSFET when mixed-voltage balance method according to one embodiment of the invention
Experimental result picture；
Figure 10 is to improve device knot according to the device pressure resistance based on mixing dynamic electric voltage balance of one embodiment of the invention
Structure schematic diagram.
Specific embodiment
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, it is intended to is used to explain the present invention, and is not considered as limiting the invention.
The device pressure resistance based on mixing dynamic electric voltage balance proposed according to embodiments of the present invention is described with reference to the accompanying drawings
Improvement method and device.
The device based on mixing dynamic electric voltage balance for describing to propose according to embodiments of the present invention with reference to the accompanying drawings first is resistance to
Press improvement method.
Fig. 1 is the device pressure resistance improvement method process based on mixing dynamic electric voltage balance according to one embodiment of the invention
Figure.
As shown in Figure 1, should based on mixing dynamic electric voltage balance device pressure resistance improvement method the following steps are included:
Step S101, in the circuit for including Metal-Oxide Semiconductor field effect transistor, by metal-oxide half
Conductor field effect transistor carries out processing of connecting with active clamping circuir and passive RCD buffer circuit respectively.
It specifically, is including Metal-Oxide Semiconductor field effect transistor (Metal-Oxide-Semiconductor
Field-Effect Transistor, abbreviation MOSFET) circuit in access active clamping circuir and passive RCD buffer circuit,
In such a way that active clamp technology and passive RCD buffer circuit combine, overcome in conventional voltage balance mode volume greatly and
Big disadvantage is lost, suitable for the balance of multistage SiC MOSFET series voltage, improves the voltage class of SiC switching device.
As shown in Fig. 2, in circuit, active clamping circuir one end and Metal-Oxide Semiconductor field effect transistor
Grid is connected, and the other end is connected with the drain electrode of Metal-Oxide Semiconductor field effect transistor；Passive RCD buffer circuit one end
It is connected with the drain electrode of Metal-Oxide Semiconductor field effect transistor, the other end and Metal-Oxide Semiconductor field effect transistor
The source electrode of pipe is connected.
Further, active voltage clamp circuit is made of Zener diode, diode and clamp resistance.Active voltage pincers
The diode cathode phase with the drain electrode of Metal-Oxide Semiconductor field effect transistor and Zener diode respectively in the circuit of position
Even；Clamp resistance is connected with the anode of the grid of Metal-Oxide Semiconductor field effect transistor and Zener diode respectively.
Wherein, it is low between grid and drain electrode when SiC MOSFET being avoided to be powered using PN diode (general-purpose diode)
Impedance path, clamp resistance are used to limit the electric current by zener diode.
As shown in figure 3, can be gone here and there at the both ends of multiple Metal-Oxide Semiconductor field effect transistors in physical circuit
Join active clamping circuir and passive RCD buffer circuit.
Step S102 obtains the drain-source voltage of Metal-Oxide Semiconductor field effect transistor, if drain-source voltage, which is greater than, to be had
When the breakdown voltage of the Zener diode in the clamp circuit of source, determine drain-source voltage clamper in clamp voltage value.
Specifically, after active clamping circuir is accessed circuit, in the leakage of Metal-Oxide Semiconductor field effect transistor
When source voltage is not more than the breakdown voltage of the Zener diode in active clamping circuir, active clamping circuir does not work, in gold
Category-oxide semiconductor field effect transistor drain-source voltage is greater than the breakdown voltage of the Zener diode in active clamping circuir
When, electric current begins flow through Zener diode, diode and clamp resistance in active clamping circuir, finally makes SiC MOSFET
Drain-source voltage clamper is in clamp voltage value.
Further, in one embodiment of the invention, clamp voltage value are as follows:
VDS=VBR+IGDRGD+VGS
Wherein, IGDTo pass through the electric current of clamp resistance, VBRFor the breakdown voltage of Zener diode, VGSFor metal-oxide
Semiconductor field effect transistor gate source voltage, RGDFor the resistance value for clamping resistance.
Step S103 is absorbed when the Zener diode in active clamping circuir is connected by passive RCD buffer circuit and is caused
Due to voltage spikes so that drain-source voltage stablize in clamp voltage value.
Passing through active clamping circuir for the drain-source voltage clamper of Metal-Oxide Semiconductor field effect transistor in clamper
After voltage value, then it is used to reduce switching loss by a very little RCD buffer, so that it may obtain good equalizing effect.
Specifically, since the conducting of Zener diode needs certain time, this is possible to cause certain due to voltage spikes,
Passive RCD buffer circuit plays a role at this time, sponges due to voltage spikes, so that the drain-source voltage of MOSFET is more stable.
It as shown in Figure 4 and Figure 5, is the pictorial diagram of driving circuit and main topological circuit.
As shown in Fig. 6, Fig. 7, Fig. 8 and Fig. 9, illustrate not using the drain-source electricity of two MOSFET when balance of voltage method
Pressure, the drain-source voltage only with two MOSFET when clamp circuit and the leakage using two MOSFET when mixed-voltage balance method
The simulation result diagram of three kinds of situations of source voltage, from image as can be seen that using two MOSFET when mixed-voltage balance method
Drain-source voltage simulation result is better than the simulation result of first two situation.
As can be seen from Figures 7 and 8, after using passive RCD buffer circuit, the voltage shown in Fig. 7 can be absorbed
Spike, so that drain-source voltage clamper is in clamp voltage value.
The device pressure resistance improvement method based on mixing dynamic electric voltage balance proposed according to embodiments of the present invention, by going here and there
Active clamp and passive snubber technology are used in the SiC MOSFET of connection simultaneously, overcomes the deficiency of conventional method, it can be substantially
Improve converters switching voltage grade.On the one hand help to further increase the space utilization of converters
Rate further reduces the weight and volume of converters, improves whole power density；On the other hand help to reduce
The difficulty of converter internal structure design.In summary two o'clock can greatly improve the insulation performance of converters, mention
Its high operational voltage level and power density.
The device pressure resistance based on mixing dynamic electric voltage balance proposed according to embodiments of the present invention referring next to attached drawing description
Improve device.
Figure 10 is to improve device knot according to the device pressure resistance based on mixing dynamic electric voltage balance of one embodiment of the invention
Structure schematic diagram.
As shown in Figure 10, should based on mixing dynamic electric voltage balance device pressure resistance improve device include: deployment module 100,
First processing module 200 and Second processing module 300.
Deployment module 100, for include Metal-Oxide Semiconductor field effect transistor circuit in, by metal-oxygen
Compound semiconductor field effect transistor carries out processing of connecting with active clamping circuir and passive RCD buffer circuit respectively.
First processing module 200, for obtaining the drain-source voltage of Metal-Oxide Semiconductor field effect transistor, if leakage
When source voltage is greater than the breakdown voltage of the Zener diode in active clamping circuir, determine drain-source voltage clamper in clamp voltage
Value.
Second processing module 300, for absorbing the Zener diode in active clamping circuir by passive RCD buffer circuit
Due to voltage spikes caused by when conducting, so that drain-source voltage is stablized in clamp voltage value.
Further, in one embodiment of the invention, active voltage clamp circuit by Zener diode, diode and
Clamp resistance composition.
Further, in one embodiment of the invention, clamp voltage value are as follows:
VDS=VBR+IGDRGD+VGS
Wherein, IGDTo pass through the electric current of clamp resistance, VBRFor the breakdown voltage of Zener diode, VGSFor metal-oxide
Semiconductor field effect transistor gate source voltage, RGDFor the resistance value for clamping resistance.
Further, in one embodiment of the invention, the diode in active voltage clamp circuit respectively with metal-
The drain electrode of oxide semiconductor field effect transistor is connected with the cathode of Zener diode；
Clamp the resistance positive phase with the grid of Metal-Oxide Semiconductor field effect transistor and Zener diode respectively
Even.
Further, in one embodiment of the invention, active clamping circuir one end and Metal-Oxide Semiconductor field
The grid of effect transistor is connected, and the other end is connected with the drain electrode of Metal-Oxide Semiconductor field effect transistor；
Passive RCD buffer circuit one end is connected with the drain electrode of Metal-Oxide Semiconductor field effect transistor, the other end with
The source electrode of Metal-Oxide Semiconductor field effect transistor is connected.
It should be noted that the aforementioned explanation to the device pressure resistance improvement method embodiment based on mixing dynamic electric voltage balance
Illustrate the device for being also applied for the embodiment, details are not described herein again.
The device pressure resistance based on mixing dynamic electric voltage balance proposed according to embodiments of the present invention improves device, by going here and there
Active clamp and passive snubber technology are used in the SiC MOSFET of connection simultaneously, overcomes the deficiency of conventional method, it can be substantially
Improve converters switching voltage grade.On the one hand help to further increase the space utilization of converters
Rate further reduces the weight and volume of converters, improves whole power density；On the other hand help to reduce
The difficulty of converter internal structure design.In summary two o'clock can greatly improve the insulation performance of converters, mention
Its high operational voltage level and power density.
In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include at least one this feature.In the description of the present invention, the meaning of " plurality " is at least two, such as two, three
It is a etc., unless otherwise specifically defined.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not
It must be directed to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be in office
It can be combined in any suitable manner in one or more embodiment or examples.In addition, without conflicting with each other, the skill of this field
Art personnel can tie the feature of different embodiments or examples described in this specification and different embodiments or examples
It closes and combines.
Although the embodiments of the present invention has been shown and described above, it is to be understood that above-described embodiment is example
Property, it is not considered as limiting the invention, those skilled in the art within the scope of the invention can be to above-mentioned
Embodiment is changed, modifies, replacement and variant.
Claims (10)
1. a kind of device pressure resistance improvement method based on mixing dynamic electric voltage balance, which comprises the following steps:
In the circuit for including Metal-Oxide Semiconductor field effect transistor, by the Metal-Oxide Semiconductor field-effect
Transistor carries out processing of connecting with active clamping circuir and passive RCD buffer circuit respectively；
The drain-source voltage of the Metal-Oxide Semiconductor field effect transistor is obtained, if the drain-source voltage has greater than described
When the breakdown voltage of the Zener diode in the clamp circuit of source, determine the drain-source voltage clamper in clamp voltage value；And
Voltage caused by when the Zener diode in the active clamping circuir is connected is absorbed by the passive RCD buffer circuit
Spike, so that the drain-source voltage is stablized in the clamp voltage value.
2. the method according to claim 1, wherein the active voltage clamp circuit is by two pole of Zener
Pipe, diode and clamp resistance composition.
3. the method according to claim 1, wherein the clamp voltage value are as follows:
VDS=VBR+IGDRGD+VGS
Wherein, IGDTo pass through the electric current of the clamp resistance, VBRFor the breakdown voltage of the Zener diode, VGSFor the gold
Category-oxide semiconductor field effect transistor gate source voltage, RGDFor the resistance value of the clamp resistance.
4. the method according to claim 1, wherein
The diode in the active voltage clamp circuit respectively with the Metal-Oxide Semiconductor field effect transistor
Drain electrode be connected with the cathode of the Zener diode；
The clamp resistance respectively with the grid and the Zener diode of the Metal-Oxide Semiconductor field effect transistor
Anode be connected.
5. according to the method described in claim 2, it is characterized in that,
Described active clamping circuir one end is connected with the grid of the Metal-Oxide Semiconductor field effect transistor, the other end
It is connected with the drain electrode of the Metal-Oxide Semiconductor field effect transistor；
Described passive RCD buffer circuit one end is connected with the drain electrode of the Metal-Oxide Semiconductor field effect transistor, another
End is connected with the source electrode of the Metal-Oxide Semiconductor field effect transistor.
6. a kind of device pressure resistance based on mixing dynamic electric voltage balance improves device characterized by comprising
Deployment module, for include Metal-Oxide Semiconductor field effect transistor circuit in, by the metal-oxide
Object semiconductor field effect transistor carries out processing of connecting with active clamping circuir and passive RCD buffer circuit respectively；
First processing module, for obtaining the drain-source voltage of the Metal-Oxide Semiconductor field effect transistor, if the leakage
When source voltage is greater than the breakdown voltage of the Zener diode in the active clamping circuir, determine that the drain-source voltage clamper is clamping
Position voltage value；
Second processing module, for absorbing two pole of Zener in the active clamping circuir by the passive RCD buffer circuit
Due to voltage spikes caused by when pipe is connected, so that the drain-source voltage is stablized in the clamp voltage value.
7. device according to claim 6, which is characterized in that the active voltage clamp circuit is by two pole of Zener
Pipe, diode and clamp resistance composition.
8. device according to claim 6, which is characterized in that the clamp voltage value are as follows:
VDS=VBR+IGDRGD+VGS
Wherein, IGDTo pass through the electric current of the clamp resistance, VBRFor the breakdown voltage of the Zener diode, VGSFor the gold
Category-oxide semiconductor field effect transistor gate source voltage, RGDFor the resistance value of the clamp resistance.
9. device according to claim 6, which is characterized in that
The diode in the active voltage clamp circuit respectively with the Metal-Oxide Semiconductor field effect transistor
Drain electrode be connected with the cathode of the Zener diode；
The clamp resistance respectively with the grid and the Zener diode of the Metal-Oxide Semiconductor field effect transistor
Anode be connected.
10. device according to claim 6, which is characterized in that
Described active clamping circuir one end is connected with the grid of the Metal-Oxide Semiconductor field effect transistor, the other end
It is connected with the drain electrode of the Metal-Oxide Semiconductor field effect transistor；
Described passive RCD buffer circuit one end is connected with the drain electrode of the Metal-Oxide Semiconductor field effect transistor, another
End is connected with the source electrode of the Metal-Oxide Semiconductor field effect transistor.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101461137A (en) * | 2006-06-02 | 2009-06-17 | 飞思卡尔半导体公司 | Slew-rate control apparatus and methods for a power transistor to reduce voltage transients during inductive flyback |
| CN101728952A (en) * | 2009-12-02 | 2010-06-09 | 浙江大学 | IGBT series circuit based on control of ARM microprocessor |
| CN102361391A (en) * | 2011-10-21 | 2012-02-22 | 南京南瑞继保电气有限公司 | Power gaining circuit applicable to high-voltage field |
| CN104135141A (en) * | 2014-08-15 | 2014-11-05 | 上海理工大学 | Energy obtaining circuit for series-connected IGBT dynamic voltage balancing control |
| CN104579279A (en) * | 2015-01-20 | 2015-04-29 | 华北电力大学（保定） | Optical fiber trigger type high-voltage solid-state switch |
| CN106452404A (en) * | 2016-07-25 | 2017-02-22 | 天津理工大学 | Active gate control circuit and IGBT electromagnetic interference inhibition method thereof |
-
2019
- 2019-07-11 CN CN201910623756.4A patent/CN110380598A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101461137A (en) * | 2006-06-02 | 2009-06-17 | 飞思卡尔半导体公司 | Slew-rate control apparatus and methods for a power transistor to reduce voltage transients during inductive flyback |
| CN101728952A (en) * | 2009-12-02 | 2010-06-09 | 浙江大学 | IGBT series circuit based on control of ARM microprocessor |
| CN102361391A (en) * | 2011-10-21 | 2012-02-22 | 南京南瑞继保电气有限公司 | Power gaining circuit applicable to high-voltage field |
| CN104135141A (en) * | 2014-08-15 | 2014-11-05 | 上海理工大学 | Energy obtaining circuit for series-connected IGBT dynamic voltage balancing control |
| CN104579279A (en) * | 2015-01-20 | 2015-04-29 | 华北电力大学（保定） | Optical fiber trigger type high-voltage solid-state switch |
| CN106452404A (en) * | 2016-07-25 | 2017-02-22 | 天津理工大学 | Active gate control circuit and IGBT electromagnetic interference inhibition method thereof |
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Application publication date: 20191025 |