CN110379766B - Inverted pyramid type silicon through hole vertical interconnection structure and preparation method - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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Abstract
The invention discloses an inverted pyramid type vertical interconnection structure and a preparation method thereof, wherein the inverted pyramid type vertical interconnection structure comprises a substrate and inverted pyramid type through holes, the substrate adopts a monocrystalline silicon wafer, and the inverted pyramid type through holes penetrate through the upper surface and the lower surface of the substrate; the upper surface and the lower surface of the substrate are also provided with metal wiring, and the metal wiring on the upper surface of the substrate is electrically communicated with the metal wiring on the lower surface of the substrate through the side wall of the inverted pyramid through hole; the inverted pyramid type silicon through hole vertical interconnection structure is easy to realize, low in process cost, suitable for a silicon substrate with large thickness, and applicable to vertical transition transmission of direct current electrical signals and low-frequency-band radio frequency signals in the silicon substrate.
Description
Technical Field
The invention relates to the technical field of packaging, in particular to an inverted pyramid type through silicon via vertical interconnection structure and a preparation method thereof.
Background
With the development of advanced packaging technology, the system-in-package technology has the advantages of miniaturization and high integration, so that the system-in-package technology is widely applied to various fields of consumer electronics, automobile electronics, industrial electronics, military electronics and the like. Monocrystalline silicon has become one of the most promising substrate materials in system-in-package technology because of its numerous advantages, such as high manufacturing accuracy, low cost, mass production, easy integration, etc. Therefore, the research of the vertical interconnection structure in the monocrystalline silicon substrate has important significance for the structure, the electrical performance and the process design of the future silicon-based three-dimensional packaging micro-system.
Conventional vertical interconnects for through-silicon vias are metal filled hollow or solid cylindrical vias. The cylindrical through silicon via structure is generally prepared by a plasma deep silicon etching process (hereinafter abbreviated as DRIE process) and a metal electroplating process. In the current micro-nano processing technology, the DRIE process can realize deep hole etching with the depth of hundreds of micrometers, but the metal electroplating process still cannot realize metal filling with the depth. The current state of the art can only achieve metal plating fills up to 200-300 microns deep. Therefore, the vertical interconnection structure of through silicon vias prepared by advanced packaging manufacturers in China today has a maximum thickness ranging from 200 micrometers to 300 micrometers. On one hand, the structure reliability of the excessively thin silicon substrate is quite low, the larger-scale multi-chip system level package cannot be realized, and the embedded integration of a thick chip (with the thickness of more than 200 micrometers) in the silicon substrate is difficult to realize; on the other hand, the DRIE process and the deep hole electroplating process have high technical thresholds, the combined process has high technical difficulty and high cost. Therefore, it is difficult to realize large-scale popularization of the cylindrical through silicon via vertical interconnection structure in the system-in-package.
In view of the above drawbacks, the present inventors have finally achieved the present invention through long-time studies and practices.
Disclosure of Invention
In order to solve the technical defects, the technical scheme adopted by the invention is that the inverted pyramid type vertical interconnection structure comprises a substrate and inverted pyramid type through holes, wherein the substrate adopts a monocrystalline silicon wafer, and the inverted pyramid type through holes penetrate through the upper surface and the lower surface of the substrate; the upper surface and the lower surface of the substrate are also provided with metal wiring, and the metal wiring on the upper surface of the substrate is electrically communicated with the metal wiring on the lower surface of the substrate through the side wall of the inverted pyramid through hole.
Preferably, all side wall surfaces in the inverted pyramid-shaped through hole and the upper surface and the lower surface of the substrate are covered with insulating layers, and the insulating layers are arranged between the metal wiring and the substrate.
Preferably, the metal wiring of the upper surface includes a first metal region and a second metal region, the first metal region and the second metal region not communicating; the inverted pyramid through hole arranged on the first metal region is vertically interconnected with the radio frequency signal transmission line on the lower end surface of the substrate; the four inverted pyramid through holes arranged on the second metal area are vertically interconnected with the grounding metal on the lower end face of the substrate, and the inverted pyramid through holes on the second metal area are annularly arranged on the periphery of the inverted pyramid through holes on the first metal area.
Preferably, the preparation method of the inverted pyramid type vertical interconnection structure comprises the following steps:
s1, preparing a single crystal silicon wafer;
s2, forming an etching mask on the upper surface of the monocrystalline silicon wafer, and anisotropically etching the monocrystalline silicon wafer to form inverted pyramid-shaped pits;
s3, depositing a first insulating layer on the upper surface of the monocrystalline silicon wafer and the inner wall of the inverted pyramid pit;
s4, forming an etching mask, and removing the first insulating layer at the bottom of the inverted pyramid pit;
s5, depositing a first metal film on the upper surface of the monocrystalline silicon wafer and the side wall of the inverted pyramid pit, and patterning the first metal film to form metal wiring on the upper surface of the monocrystalline silicon wafer and in the inverted pyramid pit;
s6, thinning the monocrystalline silicon wafer from the lower surface until the first metal film at the bottom of the inverted pyramid pit is exposed out of the lower surface of the monocrystalline silicon wafer, so as to form an inverted pyramid through hole structure;
s7, depositing a second insulating layer on the lower surface of the thinned monocrystalline silicon wafer, and patterning the second insulating layer to expose the first metal film at the bottom of the inverted pyramid through hole;
and S8, depositing a second metal film on the lower surface of the monocrystalline silicon wafer, and patterning the second metal film to form metal wiring on the lower surface of the monocrystalline silicon wafer, and finally dicing the monocrystalline silicon wafer to form the monocrystalline silicon substrate with the inverted pyramid-shaped vertical interconnection structure.
Preferably, the wafer thickness of the single crystal silicon wafer in the step S1 is set to be 0.1mm to 1mm.
Preferably, the included angles between the four inner side surfaces of the inverted pyramid-shaped concave pit and the horizontal plane are 54.74 degrees.
Preferably, in the step S2, the monocrystalline silicon wafer is etched by wet anisotropic etching to form the inverted pyramid-shaped pit.
Preferably, the patterning of the first metal film, the second metal film and the second insulating layer all adopts photoetching patterning and film etching processes.
Preferably, the preparation method of the inverted pyramid type vertical interconnection structure comprises the following steps:
s1, preparing a single crystal silicon wafer;
s2, forming an etching mask on the upper surface of the monocrystalline silicon wafer, and anisotropically etching the monocrystalline silicon wafer to form inverted pyramid-shaped pits;
s3, depositing a first metal film on the upper surface of the monocrystalline silicon wafer and the side wall of the inverted pyramid pit, and patterning the first metal film to form metal wiring on the upper surface of the monocrystalline silicon wafer and in the inverted pyramid pit;
s4, thinning the monocrystalline silicon wafer from the lower surface until the first metal film at the bottom of the inverted pyramid pit is exposed out of the lower surface of the monocrystalline silicon wafer, so that an inverted pyramid through hole structure is formed;
and S5, depositing a second metal film on the lower surface of the monocrystalline silicon wafer, and patterning the second metal film to form metal wiring on the lower surface of the monocrystalline silicon wafer, and finally dicing the monocrystalline silicon wafer to form the monocrystalline silicon substrate with the inverted pyramid-shaped vertical interconnection structure.
Preferably, the resistivity of the monocrystalline silicon wafer is higher than 1000Ω·cm.
Compared with the prior art, the invention has the beneficial effects that: the inverted pyramid type silicon through hole vertical interconnection structure is easy to realize, low in process cost, suitable for a silicon substrate with large thickness, and applicable to vertical transition transmission of direct current electrical signals and low-frequency-band radio frequency signals in the silicon substrate.
Drawings
FIG. 1 is a cross-sectional view of a single inverted pyramid type vertical interconnect of the present invention;
FIG. 2 is a flow chart of a process for fabricating the inverted pyramid-type vertical interconnect structure of the present invention;
FIG. 3 is a view of an inverted pyramid type vertical interconnect for radio frequency signal transmission;
FIG. 4 is a cross-sectional view of the RF signal transmission structure shown in FIG. 3 taken along line A-A';
fig. 5 is a graph of typical insertion loss for an inverted pyramid-type vertical interconnect structure used for radio frequency signal transmission.
The figures represent the numbers:
101-a substrate; 102-an inverted pyramid-shaped through hole; 103-an insulating layer; 104-metal wiring; 105-a first metal region; 106-a second metal region.
Detailed Description
The above and further technical features and advantages of the present invention are described in more detail below with reference to the accompanying drawings.
Example 1
As shown in fig. 1, fig. 1 is a cross-sectional view of a single inverted pyramid vertical interconnection structure in the present invention, where the inverted pyramid vertical interconnection structure includes a substrate 101 and an inverted pyramid through hole 102, the substrate 101 is a monocrystalline silicon wafer, and the inverted pyramid through hole 102 penetrates through the upper surface and the lower surface of the substrate 101.
The upper surface and the lower surface of the substrate 101 are further provided with metal wires 104, and the metal wires 104 on the upper surface of the substrate 101 are electrically communicated with the metal wires 104 on the lower surface of the substrate 101 through the side walls of the inverted pyramid through holes 102, so that a vertical interconnection structure of the upper surface and the lower surface of the substrate 101 is formed.
Preferably, insulating layers 103 are disposed on all side wall surfaces of the inverted pyramid-shaped through hole 102 and on the upper and lower surfaces of the substrate 101. The insulating layer 103 may be omitted if the resistivity of the substrate 101 is higher than 1000 Ω·cm.
Example two
As shown in fig. 2, fig. 2 is a process flow chart of preparing the inverted pyramid type vertical interconnection structure according to the present invention, and the preparation method of the inverted pyramid type vertical interconnection structure according to the present invention specifically includes the following steps:
s1, preparing a single crystal silicon wafer, wherein the wafer thickness of the single crystal silicon wafer can be set to any value in the range of 0.1 mm-1 mm;
s2, forming an etching mask on the upper surface of the monocrystalline silicon wafer by utilizing a photoetching patterning process, and then anisotropically etching the monocrystalline silicon wafer by utilizing a wet etching process to form inverted pyramid-shaped pits; the etching solution in the anisotropic etching can be TMAH, KOH or other solutions capable of carrying out anisotropic etching on the monocrystalline silicon material;
s3, depositing a first insulating layer on the upper surface of the monocrystalline silicon wafer and the inner wall of the inverted pyramid pit by utilizing a thin film deposition process so as to realize electrical isolation between the subsequent metal wiring and the monocrystalline silicon wafer; if the resistivity of the single crystal silicon wafer is higher than 1000Ω·cm, the first insulating layer may be omitted;
s4, forming an etching mask by utilizing a photoetching patterning process, and then removing the first insulating layer at the bottom of the inverted pyramid pit by utilizing a thin film etching process;
s5, depositing a first metal film on the upper surface of the monocrystalline silicon wafer and the side wall of the inverted pyramid pit by using a metal film deposition process, and then realizing the patterning of the first metal film by using photoetching patterning and a metal film etching process so as to form metal wiring on the upper surface of the monocrystalline silicon wafer and in the inverted pyramid pit;
s6, thinning the monocrystalline silicon wafer from the lower surface by using a wafer thinning process until the first metal film at the bottom of the inverted pyramid pit is exposed out of the lower surface of the monocrystalline silicon wafer, so as to form an inverted pyramid through hole structure;
s7, depositing a second insulating layer on the lower surface of the thinned monocrystalline silicon wafer by using a film deposition process, and then realizing the patterning of the second insulating layer by using photoetching patterning and a film etching process so as to expose the first metal film at the bottom of the inverted pyramid through hole;
and S8, depositing a second metal film on the lower surface of the monocrystalline silicon wafer by utilizing a metal film deposition process, and then utilizing a photoetching patterning and metal film etching process to realize the patterning of the second metal film so as to form metal wiring on the lower surface of the monocrystalline silicon wafer, and finally scribing the monocrystalline silicon wafer to form the monocrystalline silicon substrate with the inverted pyramid-shaped vertical interconnection structure.
The first insulating layer and the second insulating layer can be any material with insulating function such as silicon dioxide, silicon nitride, organic matters and the like; the specific deposition process can be any process such as chemical vapor deposition, physical sputtering, spin coating glue and the like.
The specific deposition process of the first metal film and the second metal film can be one of any deposition process such as electroplating, chemical plating, evaporation deposition, physical sputtering and the like; the specific patterning process can be any patterning process such as plasma reaction etching, ion beam etching, physical etching, laser etching and the like.
The invention uses a wet anisotropic etching process to etch the monocrystalline silicon wafer in a deep silicon manner to form an inverted pyramid type etching pit, then adopts a metal electroplating process to deposit metal on the inner surface of the pit, and finally thins the back surface of the wafer to form an inverted pyramid type vertical interconnection structure of the silicon substrate.
According to the invention, the inverted pyramid-shaped pit is obtained by using a monocrystalline silicon wet anisotropic etching process, and the four inner side surfaces of the inverted pyramid-shaped pit form an angle of 54.74 degrees with the horizontal plane instead of the 90 degrees of the traditional cylindrical through silicon hole, so that the inverted pyramid-shaped pit is in a wide-mouth horn-shaped structure as a whole, and therefore, metal is easy to deposit on all side walls and bottom surfaces of the pit in the subsequent metal electroplating process, and the preparation process difficulty is greatly reduced.
The adopted single crystal silicon wet anisotropic etching process can etch inverted pyramid-shaped pits with arbitrary depth by controlling the length of etching time, and the subsequent metal electroplating process does not increase the process difficulty along with the increase of the pit depth, so that the silicon substrate with the vertical interconnection structure with large thickness (more than 400 microns thick) is easy to prepare by the process combination.
The invention forms the inverted pyramid through hole on the monocrystalline silicon wafer by utilizing the wet anisotropic etching process so as to realize the vertical interconnection of the electrical signals. The batch and low cost characteristics of wet etching lead the inverted pyramid type vertical interconnection to have lower cost than the traditional cylindrical silicon through hole structure; the wet etching process has low difficulty, has no limitation on the thickness of the monocrystalline silicon substrate, can realize vertical interconnection of the silicon substrate with large thickness by increasing etching time, overcomes the defect that the traditional cylindrical silicon through hole is only suitable for a thin silicon substrate (the thickness is less than 300 um), and can be widely applied to silicon-based microsystems.
Example III
The inverted pyramid type vertical interconnection structure disclosed by the invention not only can be used for vertical transmission of direct current and low-frequency electrical signals, but also can be used for vertical transmission of radio frequency signals.
As shown in fig. 3, fig. 3 is a view of an inverted pyramid-shaped vertical interconnect structure for radio frequency signal transmission. In fig. 3, the gray areas are covered with a patterned metal film, specifically, the metal film includes a first metal area 105 and a second metal area 106, and the first metal area 105 and the second metal area 106 are not connected; the first metal region 105 is configured to transmit radio frequency signals, and the inverted pyramid through hole disposed on the first metal region 105 is vertically interconnected with a radio frequency signal transmission line on the lower end surface of the substrate 101. The second metal region 106 is configured to be grounded so as to realize shielding and impedance matching of radio frequency signals, in this embodiment, four inverted pyramid through holes disposed on the second metal region 106 are vertically interconnected with the grounded metal on the lower end surface of the substrate 101, and the inverted pyramid through holes on the second metal region 106 are annularly disposed on the periphery of the inverted pyramid through holes on the first metal region 105.
As shown in fig. 4, fig. 4 is a cross-sectional view of the radio frequency signal transmission structure shown in fig. 3 taken along A-A'. In fig. 4, the metal lead on the upper end face is vertically interconnected with the radio frequency signal on the lower end face of the substrate through the inverted pyramid through hole on the first metal region 105; the grounding metal of the upper end face is vertically interconnected with the grounding metal of the lower end face of the substrate through the inverted pyramid through hole on the second metal region 106; the whole vertical transmission structure of the radio frequency signal can be prepared by the process flow shown in fig. 2.
As shown in fig. 5, fig. 5 is a graph of typical insertion loss when the inverted pyramid type vertical interconnect structure is used for radio frequency signal transmission, and the graph in fig. 5 is obtained by HFSS simulation using finite element electromagnetic simulation software. The graph illustrates that the insertion loss begins to increase when the frequency of the radio frequency signal exceeds 8GHz and resonance occurs near both 9.5GHz and 16.8GHz frequency points. Therefore, the inverted pyramid type vertical interconnection structure has better transmission performance below 8 GHz.
The foregoing description of the preferred embodiment of the invention is merely illustrative of the invention and is not intended to be limiting. It will be appreciated by persons skilled in the art that many variations, modifications, and even equivalents may be made thereto without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (9)
1. The inverted pyramid type vertical interconnection structure is characterized by comprising a substrate and inverted pyramid type through holes, wherein the substrate is made of monocrystalline silicon wafers, and the inverted pyramid type through holes penetrate through the upper surface and the lower surface of the substrate; the upper surface and the lower surface of the substrate are also provided with metal wiring, the metal wiring on the upper surface of the substrate is electrically communicated with the metal wiring on the lower surface of the substrate through the side wall of the inverted pyramid-shaped through hole, insulating layers are arranged on all the side wall surfaces in the inverted pyramid-shaped through hole and the upper surface and the lower surface of the substrate in a covering mode, the insulating layers are arranged between the metal wiring and the substrate, the metal wiring on the upper surface comprises a first metal area and a second metal area, and the first metal area is not communicated with the second metal area; the inverted pyramid-shaped through hole arranged on the first metal region is vertically interconnected with the radio frequency signal transmission line on the lower end face of the substrate; the four inverted pyramid through holes arranged on the second metal area are vertically interconnected with the grounding metal on the lower end face of the substrate, and the inverted pyramid through holes on the second metal area are annularly arranged on the periphery of the inverted pyramid through holes on the first metal area.
2. The inverted pyramid type vertical interconnection structure is characterized by comprising a substrate and inverted pyramid type through holes, wherein the substrate is made of monocrystalline silicon wafers, and the inverted pyramid type through holes penetrate through the upper surface and the lower surface of the substrate; the upper surface and the lower surface of the substrate are also provided with metal wiring, the metal wiring on the upper surface of the substrate is electrically communicated with the metal wiring on the lower surface of the substrate through the side wall of the inverted pyramid-shaped through hole, the metal wiring on the upper surface comprises a first metal area and a second metal area, and the first metal area is not communicated with the second metal area; the inverted pyramid-shaped through hole arranged on the first metal region is vertically interconnected with the radio frequency signal transmission line on the lower end face of the substrate; the four inverted pyramid through holes arranged on the second metal area are vertically interconnected with the grounding metal on the lower end face of the substrate, and the inverted pyramid through holes on the second metal area are annularly arranged on the periphery of the inverted pyramid through holes on the first metal area.
3. A method of fabricating an inverted pyramidal vertical interconnect structure as defined in claim 1, comprising the steps of:
s1, preparing a single crystal silicon wafer;
s2, forming an etching mask on the upper surface of the monocrystalline silicon wafer, and anisotropically etching the monocrystalline silicon wafer to form inverted pyramid-shaped pits;
s3, depositing a first insulating layer on the upper surface of the monocrystalline silicon wafer and the inner wall of the inverted pyramid-shaped pit;
s4, forming an etching mask, and removing the first insulating layer at the bottom of the inverted pyramid-shaped pit;
s5, depositing a first metal film on the upper surface of the monocrystalline silicon wafer and the side wall of the inverted pyramid-shaped pit, and patterning the first metal film to form metal wiring on the upper surface of the monocrystalline silicon wafer and in the inverted pyramid-shaped pit;
s6, thinning the monocrystalline silicon wafer from the lower surface until the first metal film at the bottom of the inverted pyramid-shaped pit is exposed out of the lower surface of the monocrystalline silicon wafer, so as to form an inverted pyramid-shaped through hole structure;
s7, depositing a second insulating layer on the lower surface of the thinned monocrystalline silicon wafer, and patterning the second insulating layer to expose the first metal film at the bottom of the inverted pyramid-shaped through hole;
and S8, depositing a second metal film on the lower surface of the monocrystalline silicon wafer, and patterning the second metal film to form metal wiring on the lower surface of the monocrystalline silicon wafer, and finally dicing the monocrystalline silicon wafer to form the monocrystalline silicon substrate with the inverted pyramid-shaped vertical interconnection structure.
4. The method according to claim 3, wherein the wafer thickness of the single crystal silicon wafer in the step S1 is set to 0.1mm to 1mm.
5. A method of manufacturing as claimed in claim 3, wherein the four inner sides of the inverted pyramidal pits are at an angle of 54.74 ° to the horizontal.
6. The method of manufacturing according to claim 3, wherein in the step S2, the single crystal silicon wafer is subjected to deep silicon etching by a wet anisotropic etching process to form the inverted pyramid-shaped pits.
7. The method of claim 3, wherein patterning of the first metal film, the second metal film, and the second insulating layer uses photolithographic patterning and film etching processes.
8. A method of fabricating an inverted pyramidal vertical interconnect structure as defined in claim 2, comprising the steps of:
s1, preparing a single crystal silicon wafer;
s2, forming an etching mask on the upper surface of the monocrystalline silicon wafer, and anisotropically etching the monocrystalline silicon wafer to form inverted pyramid-shaped pits;
s3, depositing a first metal film on the upper surface of the monocrystalline silicon wafer and the side wall of the inverted pyramid-shaped pit, and patterning the first metal film to form metal wiring on the upper surface of the monocrystalline silicon wafer and in the inverted pyramid-shaped pit;
s4, thinning the monocrystalline silicon wafer from the lower surface until the first metal film at the bottom of the inverted pyramid-shaped pit is exposed out of the lower surface of the monocrystalline silicon wafer, so as to form an inverted pyramid-shaped through hole structure;
and S5, depositing a second metal film on the lower surface of the monocrystalline silicon wafer, and patterning the second metal film to form metal wiring on the lower surface of the monocrystalline silicon wafer, and finally dicing the monocrystalline silicon wafer to form the monocrystalline silicon substrate with the inverted pyramid-shaped vertical interconnection structure.
9. The method of manufacturing of claim 8, wherein the single crystal silicon wafer has a resistivity of greater than 1000 Ω·cm.
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| US7589009B1 (en) * | 2006-10-02 | 2009-09-15 | Newport Fab, Llc | Method for fabricating a top conductive layer in a semiconductor die and related structure |
| US7932179B2 (en) * | 2007-07-27 | 2011-04-26 | Micron Technology, Inc. | Method for fabricating semiconductor device having backside redistribution layers |
| CN102024782B (en) * | 2010-10-12 | 2012-07-25 | 北京大学 | Three-dimensional vertical interconnecting structure and manufacturing method thereof |
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| JPH0766430A (en) * | 1993-08-27 | 1995-03-10 | Fujikura Ltd | Wiring structure of semiconductor substrate and its manufacture |
| CN1685513A (en) * | 2002-09-24 | 2005-10-19 | 浜松光子学株式会社 | Photodiode array and method for manufacturing same |
| CN101238572A (en) * | 2005-08-05 | 2008-08-06 | 美光科技公司 | Methods of forming through-wafer interconnects and structures resulting therefrom |
| CN102881644A (en) * | 2012-10-12 | 2013-01-16 | 江阴长电先进封装有限公司 | Method for packaging wafer level chip |
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