CN110379712A - A kind of lithographic method - Google Patents
A kind of lithographic method Download PDFInfo
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- CN110379712A CN110379712A CN201910714777.7A CN201910714777A CN110379712A CN 110379712 A CN110379712 A CN 110379712A CN 201910714777 A CN201910714777 A CN 201910714777A CN 110379712 A CN110379712 A CN 110379712A
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- 238000000034 method Methods 0.000 title claims abstract description 80
- 238000005530 etching Methods 0.000 claims abstract description 100
- 239000012495 reaction gas Substances 0.000 claims abstract description 40
- 239000007789 gas Substances 0.000 claims abstract description 35
- 238000006243 chemical reaction Methods 0.000 claims abstract description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims description 20
- 230000008021 deposition Effects 0.000 claims description 18
- 239000011261 inert gas Substances 0.000 claims description 13
- 238000001020 plasma etching Methods 0.000 claims description 8
- 238000004544 sputter deposition Methods 0.000 claims description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- 230000005284 excitation Effects 0.000 claims description 6
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 5
- 230000001351 cycling effect Effects 0.000 claims description 4
- 230000003252 repetitive effect Effects 0.000 claims description 4
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 claims description 3
- 239000001307 helium Substances 0.000 claims description 3
- 229910052734 helium Inorganic materials 0.000 claims description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052743 krypton Inorganic materials 0.000 claims description 3
- DNNSSWSSYDEUBZ-UHFFFAOYSA-N krypton atom Chemical compound [Kr] DNNSSWSSYDEUBZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052754 neon Inorganic materials 0.000 claims description 3
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 229910052724 xenon Inorganic materials 0.000 claims description 3
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 42
- 238000004519 manufacturing process Methods 0.000 abstract description 13
- 238000003384 imaging method Methods 0.000 abstract description 8
- 239000000126 substance Substances 0.000 description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 24
- 125000006850 spacer group Chemical group 0.000 description 21
- 230000000694 effects Effects 0.000 description 16
- 239000000758 substrate Substances 0.000 description 16
- 229910052681 coesite Inorganic materials 0.000 description 12
- 229910052906 cristobalite Inorganic materials 0.000 description 12
- 238000010586 diagram Methods 0.000 description 12
- 230000008569 process Effects 0.000 description 12
- 239000000377 silicon dioxide Substances 0.000 description 12
- 235000012239 silicon dioxide Nutrition 0.000 description 12
- 229910052682 stishovite Inorganic materials 0.000 description 12
- 229910052905 tridymite Inorganic materials 0.000 description 12
- 230000006378 damage Effects 0.000 description 11
- 229910005883 NiSi Inorganic materials 0.000 description 10
- 239000000463 material Substances 0.000 description 10
- 150000002500 ions Chemical class 0.000 description 9
- 238000010849 ion bombardment Methods 0.000 description 8
- 230000003628 erosive effect Effects 0.000 description 6
- 208000027418 Wounds and injury Diseases 0.000 description 5
- 208000014674 injury Diseases 0.000 description 5
- 239000002245 particle Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000010926 purge Methods 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000004215 Carbon black (E152) Substances 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- -1 Hydrogen fluorine Hydrocarbon Chemical class 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 229930195733 hydrocarbon Natural products 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
Abstract
This disclosure relates to the manufacturing method of lithographic method and semiconductor devices and imaging sensor.One of embodiment provides a kind of lithographic method comprising: reaction gas is deposited on the surface to be etched of silicon nitride SiN；And the surface to be etched is sputtered using sputter gas, at least part of the SiN after etching reaction.
Description
Technical field
This disclosure relates to technical field of semiconductors, it particularly relates to the manufacturer of a kind of lithographic method, semiconductor devices
The manufacturing method of method and imaging sensor.
Background technique
In recent years, as semiconductor fabrication process and technology are constantly promoted, semiconductor chip is towards smaller, integrated level
Direction higher, with better function continues to develop, and requires in manufacturing process technique more accurate.
In semiconductor transistor, especially in the preparation of gate spacer, it is often necessary to be carried out to SiN layer
Accurate etching.But there are still problems for current SiN lithographic technique.For example, the ion bombardment in etching process can be to lining
Bottom surface brings etching injury, introduces white noise, increases dark current, and will receive depth-to-width ratio correlation etching (Aspect
Ratio Dependent Etching, ARDE) effect influence and cause etching uneven, and can etch away be not intended to by
Other substances, etc. of etching.
Therefore, in SiN etching, there is the demand for improved lithographic technique.
Summary of the invention
One purpose of the disclosure is to provide a kind of novel lithographic method, enables to mitigate and partly lead in etching process
The damage on body substrate surface reduces white noise, reduces dark current, eliminates depth-to-width ratio correlation etching ARDE effect and only etches institute
It is expected that the substance of etching, to realize more accurate etching.
According to the disclosure in a first aspect, providing a kind of lithographic method, comprising: by reaction gas be deposited on SiN to
On etching surface；And the surface to be etched is sputtered using sputter gas, at least one of the SiN after etching reaction
Part.
According to the second aspect of the disclosure, a kind of manufacturing method of semiconductor devices is provided, comprising: in semiconductor devices
Middle offer silicon nitride SiN spacer；And the SiN spacer is carved according to the method for the first aspect according to the disclosure
Erosion.
According to the third aspect of the disclosure, a kind of manufacturing method of imaging sensor is provided, comprising: in imaging sensor
Middle offer semiconductor devices；And the semiconductor devices is performed etching according to the method for the second aspect according to the disclosure.
By referring to the drawings to the detailed description of exemplary embodiment of the present invention, other feature of the invention and its
Advantage will become more apparent from.
Detailed description of the invention
The attached drawing for constituting part of specification describes embodiment of the disclosure, and together with the description for solving
Release the principle of the disclosure.
The disclosure can be more clearly understood according to following detailed description referring to attached drawing, in which:
Figure 1A is illustrated that there are the etching result schematic diagrams of the conventional etch of depth-to-width ratio correlation etching effect；
Figure 1B is illustrated the etching result schematic diagram of atomic layer etching；
Fig. 2 is illustrated the flow chart of the lithographic method according to disclosure exemplary embodiment；
Fig. 3 A is illustrated the structural schematic diagram of semiconductor transistor；
Fig. 3 B is illustrated the structural schematic diagram of the semiconductor transistor after handling by conventional etch；
Fig. 3 C is illustrated the semiconductor transistor after the etching processing according to disclosure exemplary embodiment
Structural schematic diagram；
Fig. 4 is illustrated the gas according to applied in the lithographic method of disclosure exemplary embodiment and etches situation
Schematic diagram；
Fig. 5 is illustrated the signal of the etching situation of different material in the lithographic method according to disclosure exemplary embodiment
Figure.
Fig. 6 is illustrated the etching of different material in each circulation in the lithographic method according to disclosure exemplary embodiment
Measure time history plot.
Note that same appended drawing reference is used in conjunction between different attached drawings sometimes in embodiments described below
It indicates same section or part with the same function, and omits its repeated explanation.In the present specification, using similar mark
Number and letter indicate similar terms, therefore, once being defined in a certain Xiang Yi attached drawing, then do not needed in subsequent attached drawing pair
It is further discussed.
In order to make it easy to understand, position, size and range of each structure shown in attached drawing etc. etc. do not indicate practical sometimes
Position, size and range etc..Therefore, disclosed invention is not limited to position, size and range disclosed in attached drawing etc. etc..
Specific embodiment
As it was noted above, the gas used is typically mixed forms plasma together in traditional Si N etching process,
The plasma often ion energy with higher, substrate surface can be caused by causing the ion bombardment in etching process to handle
Etching injury to introduce white noise to transistor, and increases dark current.Accordingly, there exist reduce SiN etching to substrate table
The demand of the etching injury in face.
In addition, there are depth-to-width ratio correlations to etch ARDE effect for traditional Si N etching.Figure 1A be illustrated there are depth-to-width ratio correlation
Etch the etching result schematic diagram of the conventional etch of ARDE effect.As shown in Figure 1A, various sizes of structure exists in etching
Rate difference, the structure A1 with high-aspect-ratio are lower than the etch rate of the structure B1 of low depth-to-width ratio.This is because having height
In the structure A1 of depth-to-width ratio, reaction particle is more difficult to reach structural base, lower so as to cause etch rate.Accordingly, there exist offset
Except the demand of the depth-to-width ratio correlation etching ARDE effect in SiN etching.
Furthermore when etching SiN, need to remove or damage while removing SiN other undesirable being etched
Substance, such as SiO2, Si, NiSi etc..This need SiN relative to other substances the etch rate ratio with higher in etching.
The etch rate ratio of different material is referred to as selection ratio.Therefore, there is also to the selection ratio for increasing SiN and other substances
Demand.
As can be seen that current lithographic method is difficult to realize the accurate etching of SiN.By further investigation, it is contemplated that above-mentioned
Content, present inventor expect that the thought that atomic layer can be etched to (Atomic Layer Etching, ALE) is integrated to
In SiN etching.Atomic layer lithographic technique is a kind of with from limiting and orderly mode successively removes in atom magnitude the skill of material
Art.Figure 1B is illustrated the etching result schematic diagram of atomic layer etching.Compared to the conventional etch in Figure 1A, as shown in Figure 1B,
In the case where atomic layer etching, from restricted so that etching only can remove layer of material every time, so that different deep wide
Also the etching that can be realized same depth in the structure A2 and B2 of ratio effectively overcomes depth-to-width ratio correlation etching ARDE effect.
However, although atomic layer lithographic technique has been applied in the etching of silicon Si at present, but it is to be understood that needle
The etching of other substances (for example, SiN) can not be simply applied to the atomic layer lithographic technique of Si, because substance is essential
There are many differences for the difference of matter, etching to other substances and the etching to Si.
Comprehensively consider the above content, present inventor combines the thought of atomic layer etching, by selecting gas appropriate
Body and etching condition (for example, voltage, frequency, power, temperature, time etc.) realize a kind of improved for silicon nitride SiN's
Lithographic method.Damage of the ion bombardment to semiconductor substrate surface can not only be reduced according to the lithographic method of the disclosure, is reduced
White noise reduces dark current, and can eliminate depth-to-width ratio correlation etching ARDE effect, increases the selection of SiN and other substances
Than, while there is low-load effect.
It is described in detail the various exemplary embodiments of the disclosure below with reference to accompanying drawings.It should also be noted that unless in addition having
Body explanation, the unlimited system of component and the positioned opposite of step, numerical expression and the numerical value otherwise illustrated in these embodiments is originally
Scope of disclosure.
Be to the description only actually of at least one exemplary embodiment below it is illustrative, never as to the disclosure
And its application or any restrictions used.That is, semiconductor device and its manufacturing method herein is with illustrative
Mode is shown, to illustrate the different embodiments of the structures and methods in the disclosure.It will be understood by those skilled in the art, however, that
They, which are merely illustrative, can be used to the exemplary approach of the invention implemented, rather than mode exhausted.In addition, attached drawing need not be by
Ratio is drawn, and some features may be amplified to show the details of specific component.
Technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, but suitable
In the case of, the technology, method and apparatus should be considered as authorizing part of specification.
It is shown here and discuss all examples in, any occurrence should be construed as merely illustratively, without
It is as limitation.Therefore, the other examples of exemplary embodiment can have different values.
In order to more comprehensively, the present invention is expressly understood, the novel skill according to the disclosure is illustrated below in conjunction with attached drawing
Art.
Fig. 2 is illustrated the flow chart of the lithographic method according to disclosure exemplary embodiment.
Specifically, as shown in Fig. 2, reaction gas is deposited on the surface to be etched of SiN at step 210.Example
Such as, it can be made to be deposited on the surface to be etched of SiN, to occur with SiN anti-by the way that reaction gas is passed through etching apparatus
It answers.It should be appreciated that reaction gas is in addition to being deposited on SiN, it is also possible to be deposited on the surface of other substances, and SiN to
Etching surface is not limited to the surface of uniform smooth, it is also possible to for coarse surface or stepped surface etc..It is worth noting
, the reaction of reaction gas has from restricted, once being saturated, reaction will stop on surface to be etched.
In some embodiments, reaction gas may include hydrofluorocarbon, and chemical formula can be expressed as CxHyFz.Hydrogen fluorine
Hydrocarbon, which is easy to react with SiN, generates volatile substance, is conducive to the etching of SiN.Specifically, in some embodiments,
Hydrofluorocarbon for example may include one of CHF3, CH2F2, CH3F, C4H8F2, C4H9F etc. or a variety of.Wherein, in hydrofluorocarbon
The ratio of hydrogen H and fluorine F are bigger, and the selection of SiN and other substances are bigger than then.
In some embodiments, before deposition step 210, first voltage can be applied to reaction gas, and will
Reaction gas excitation is the first plasma.In some embodiments, the first voltage that reaction gas is applied can be
High frequency voltage is the first plasma for decomposing, ionizing and exciting by reaction gas.Wherein, reaction gas is in high-frequency electrical
It can occur to ionize under the excitation of pressure and decompose, the particle of generation is for example including charged particle, active neutral particle and other particles.
In some embodiments, reaction gas is not applied to low-frequency voltage or is applied with lower low-frequency voltage, in order to avoid first
Energy of plasma is excessively high and substance to be etched is etched in advance, and wherein the low-frequency voltage power is preferably set to 0W
~10W.
In disclosure exemplary embodiment, the energy of the first plasma is less than SiN reactive ion etching energy, in order to avoid
SiN is etched in advance in deposition step.What SiN reactive ion etching energy can as etch away the SiN after reaction etc.
The threshold energy of gas ions.In some embodiments, SiN reactive ion etching energy for example can be 30eV.In some realities
It applies in mode, the energy of the first plasma for example can be 10eV~25eV.
In some embodiments, after step 210, reaction gas is reacted with the substance on surface to be etched, and
And excessive reaction gas can be removed after reacting.In some embodiments, it can sufficiently react straight in reaction gas
To being saturated and then remove excessive reaction gas.It in some embodiments, after reacting, can be with cleaning reaction institute
The new substance generated.As an example, excessive reaction gas can be removed by being passed through purge gas and using draw-out device
Substance to be purged is needed with other, wherein quick gas open-close valve advantageously improves etching performance.
In addition, it is worth noting that, the substance on surface to be etched not only may include SiN, also may include in addition to SiN
Other substances, such as SiO2, Si, NiSi etc..Therefore, reaction gas may also occur anti-with other substances in addition to SiN
It answers.In some embodiments, by controlling the selection ratio of SiN and other substances, to control reaction gas and SiN and other objects
The reaction rate of matter, to influence corresponding etch rate.
Next, treating etching surface at step 220 using sputter gas and being sputtered, with the SiN after etching reaction
At least part.Wherein, the SiN after reaction, which can according to need, is etched or is partially etched completely.In some implementations
In mode, it can be sputtered again after reaction gas reacts with surface to be etched and to reach saturation.
In some embodiments, sputter gas may include inert gas and oxygen.Inert gas is alternatively referred to as rare
Gas.As an example, can be raw by making ionized inert gas using high voltage electric field in inert gas filled etch chamber
At ion stream, to bombard substance to be etched.In some embodiments, inert gas may include helium He, neon Ne, argon Ar,
One of krypton Kr, xenon Xe etc. or a variety of.
Additionally, in some embodiments, it can also be passed through inert gas in deposition step 210, to reaction gas
Diluting effect is played, to control reaction rate, and then influences deposition rate, avoids reactant gas flow rate too fast and causes
React insufficient.
In some embodiments, before sputter step 220, second voltage can be applied to sputter gas, and will
Sputter gas excitation is the second plasma.In some embodiments, the second voltage that sputter gas is applied can be
Low-frequency voltage, for assigning ion energy for the second plasma.Wherein, the second plasma is under the action of low-frequency voltage,
Ion kinetic energy with higher, with the etching surface being used to after bombardment reaction.In some embodiments, sputter gas also by
Apply high frequency voltage, so that sputter gas is activated into the second plasma.
In disclosure exemplary embodiment, the energy of the second plasma is greater than SiN reactive ion etching energy, thus
There can be enough energy to perform etching the surface to be etched after reaction.In some embodiments, second plasma
Energy is greater than the energy of the first plasma.In some embodiments, the energy of the second plasma for example can be 50eV
~100eV.
In the disclosure, the frequency for the first voltage that reaction gas is applied is higher than second that sputter gas is applied
The frequency of voltage.In some embodiments, the frequency of first voltage for example can be 40MHz~100MHz, it is preferable that can be with
For 40MHz, 60MHz or 100MHz, the frequency of second voltage for example can be 400kHz~13.56MHz, it is preferable that Ke Yiwei
400kHz, 3.2MHz or 13.56MHz.
As an example, the power of first voltage can be set to 100W~500W.As an example, can be by low-frequency voltage
The set of frequency of (that is, second voltage) is 3.2MHz, and the low-frequency voltage power setting by the first plasma in deposition step is
0W~20W, and be 25W~50W by the second voltage power setting of the second plasma in sputter step.Show as another
The set of frequency of low-frequency voltage (that is, second voltage) can be 13.56MHz, by the first plasma in deposition step by example
Low-frequency voltage power setting is 0W~50W, and is 50W by the second voltage power setting of the second plasma in sputter step
~200W.
In some embodiments, after step 220, after completing sputtering, residue is removed, to complete primary carve
Erosion.Wherein, residue may include excessive sputter gas and the substance that sputters away from surface to be etched.As an example, can
With the residue by being passed through purge gas and using draw-out device, after removing sputtering.
In some embodiments, after completing primary depositing step 210 and sputter step 220, the etch amount of SiN for example may be used
Think 1nm~5nm.It in some embodiments, can be with repetitive cycling deposition step 210 and sputter step 220, to complete more
Secondary etch cycle, until SiN etching reaches thickness predetermined.Wherein, thickness predetermined can be operator
It is expected that the thickness of etching, can be preset by operator.In the etching processing according to the disclosure, have benefited from reaction process
From restricted, each etch cycle can only remove layer of material, this from restricted processed different structure to be realized
Identical etching depth.
It will be understood by those skilled in the art that above-mentioned steps are not intended to limit the solution of the present invention, but can be according to actually answering
With arbitrarily being modified or deleted.And it will be understood by those skilled in the art that quarter according to the exemplary embodiment of the disclosure
Etching method can also include the other steps that do not list herein as needed, for example, preparation process, parameter setting step, etc.
Deng.
In order to understand the present invention more complete and comprehensively, below in conjunction with Fig. 3 A- Fig. 6, the quarter for proposition that the present invention will be described in detail
The etching situation of etching method and its advantage compared to conventional etch.
Fig. 3 A is illustrated the structural schematic diagram of semiconductor transistor.As shown in Figure 3A, semiconductor transistor may include
Substrate 100.In some embodiments, substrate may include unitary semiconductor material or compound semiconductor materials (such as carbon
SiClx, SiGe, GaAs, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide etc.) or combinations thereof.In other embodiments
In, substrate may be the various compound substrates such as silicon-on-insulator (SOI), silicon germanium on insulator.In some embodiments, it serves as a contrast
Bottom 100 may include the impurity of the first conduction type, such as n-type impurity (for example, aluminium Al, boron, indium In, gallium Ga).This field skill
Art personnel understand that substrate is not any way limited, but can be selected according to practical application.In addition, can also be in substrate
It is formed with other semiconductor device components.
As shown in Figure 3A, in some embodiments, semiconductor transistor can also include well region 200.Well region 200 includes
Source electrode well region and drain electrode well region.Wherein, source electrode well region and drain electrode well region can according to need and be used interchangeably.In some embodiments
In, well region 200 may include the impurity of second conduction type opposite with the first conduction type, as p-type impurity (for example, phosphorus P,
Arsenic As etc.).
Continue as shown in Figure 3A, in some embodiments, semiconductor transistor can also include separator 300, such as
Shallow trench isolation (STI).Each semiconductor transistor is isolated from each other by separator 300, thus avoid semiconductor transistor it
Between interfere with each other.
In some embodiments, semiconductor transistor can also include gate spacer.Gate spacer is for adjusting
The region of ion implantation.Continue as shown in Figure 3A, gate spacer may include gate oxide 400 and grid 500.Wherein,
Gate oxide 400 is located among source electrode well region and drain electrode well region, and grid 500 is located on gate oxide 400.In some implementations
In mode, grid 500 can be polysilicon gate.In some embodiments, gate spacer can pass through chemical vapor deposition
Long-pending and photoetching treatment is formed.Specifically, as an example, the step of forming gate spacer may include: deposition gate silicon layer；?
Gate silicon layer surface forms photoresist layer；Photoresist layer is exposed and is developed, patterned photoresist layer is formed；With pattern
The photoresist layer of change is mask, is performed etching to gate silicon layer；And the patterned photoresist layer of removal.
Continue as shown in Figure 3A, in some embodiments, semiconductor transistor can also include first medium layer 600,
Wherein first medium layer 600 is covered on the surface of substrate 100, well region 200, separator 300 and grid 500.In some implementations
In mode, first medium layer 600 may include oxide, such as SiO2.
Continue as shown in Figure 3A, in some embodiments, semiconductor transistor can also include second dielectric layer 700,
Wherein second dielectric layer 700 is covered on the surface of first medium layer 600.In some embodiments, second dielectric layer 700 can
To include SiN.
Fig. 3 B is illustrated the structural schematic diagram of the semiconductor transistor after handling by conventional etch.Such as Fig. 3 B institute
Show, in the case where conventional etch, energy is higher when due to ion bombardment, can cause etching injury to 100 surface of substrate.Separately
Outside, there is also depth-to-width ratio correlations to etch ARDE effect for conventional etch, so that the etch rate of the SiN of gate spacer bottom is lower than
The etch rate of the SiN at 500 top of grid causes the SiN at 500 top of grid by overetch.And with semiconductor crystal
Grid width and grid pole spacing are more and more narrow in pipe, and depth-to-width ratio correlation etches ARDE effect can be more obvious.In addition, in tradition
In etching, SiN is relatively low relative to the selection of other substances, therefore includes that the second dielectric layer 700 of SiN is difficult to realize uniformly carve
Erosion may etch away the lower layer's substance for not needing etching originally and after SiN is etched, thus can be to the of its lower layer
One dielectric layer 600, grid 500, separator 300, well region 200 and substrate 100 etc. cause etching injury ED.
In contrast, Fig. 3 C is illustrated the semiconductor after the etching processing according to disclosure exemplary embodiment
The structural schematic diagram of transistor.Using the lithographic method of the disclosure, by the deposition and sputter step in control etching process
Used gas and etching condition (for example, voltage, frequency, power, temperature, time) etc., ion bombardment when reducing sputtering
Ion energy in addition eliminate the depth-to-width ratio of SiN etching to alleviate the damage of semiconductor substrate surface in etching process
Correlation etching ARDE effect, makes it possible to realize orientation etching and isotropic etching, thus even if depth-to-width ratio in SiN structure
Difference can also obtain equivalent etching, and increase the selection ratio of SiN Yu other substances.
As an example, as shown in Figure 3 C, it can be seen that realize the uniform quarter of second dielectric layer 700 (for example, SiN layer)
Erosion, alleviates damage of the ion bombardment to 100 surface of semiconductor substrate, realizes equivalent etching in the different place of depth-to-width ratio,
And it avoids non-SiN substance (for example, SiO2, Si etc.) accidentally to be etched.
Specifically, Fig. 4 be illustrated the gas according to applied in the lithographic method of disclosure exemplary embodiment and
The schematic diagram of etching condition.As shown in figure 4, an etching processing includes deposition processes and sputter process.It, can be with time t
Repetitive cycling deposition processes and sputter process, until etching reaches thickness predetermined.As shown in figure 4, in lodgment
In reason, reaction gas for example can be CH3F, and reaction gas is applied with high frequency voltage.As shown in figure 4, in sputter process,
Sputter gas for example can be Ar, and sputter gas is applied with low-frequency voltage.It should be appreciated that reaction gas is not limited to CH3F,
It can be any one or more in hydrofluorocarbon, and sputter gas is not limited to Ar, can be any one in inert gas
Kind is a variety of.
Fig. 5 is illustrated the signal of the etching situation of different material in the lithographic method according to disclosure exemplary embodiment
Figure.As an example, Fig. 5 shows the etching situation of SiN, SiO2, Si, NiSi.As shown in figure 5, being hydrofluorocarbon in reaction gas
In the case where polymer, it can be seen that compared with SiO2, Si, NiSi, the extent of reaction of SiN and reaction gas is higher, and its
Etch rate is significantly higher than the etch rate of SiO2, Si, NiSi, that is to say, that selection ratio of the SiN relative to SiO2, Si, NiSi
It is higher.
Fig. 6 is illustrated the etching of different material in each circulation in the lithographic method according to disclosure exemplary embodiment
Measure time history plot.As an example, Fig. 6 shows the feelings that the etch amount of SiN, SiO2, Si, NiSi change over time
Condition.In Fig. 6, trunnion axis indicate sputtering time t, vertical axes indicate each circulation etch amount (Etch Amount/Cycle,
EA/C).In some embodiments, the etch amount EA/C of each circulation can be calculated by formula 1.
[formula 1]
EA/C=ion energy * ion-flow rate * t
According to Fig. 6 as can be seen that the etch amount of SiN at any time is higher than the etch amount of SiO2, Si, NiSi, and in Fig. 6
In the dashed rectangle corresponding period, SiN increases very fast relative to the etch amount of SiO2, Si, NiSi, it means that the quarter of SiN
The rate of rise (that is, etch rate) of erosion amount is higher, and SiN is relatively high relative to the selection of SiO2, Si, NiSi.In some realities
It applies in mode, SiN can such as be greater than or equal to 30 relative to the selection percentage of other substances.
Lithographic method according to the exemplary embodiment of the disclosure can be adapted for include SiN spacer any semiconductor
Device.In some embodiments, SiN spacer can be gate spacer.In addition, according to an exemplary embodiment of the present disclosure
Lithographic method be readily applicable to include any semiconductor devices of SiN spacer imaging sensor and other devices.
In short, according to an exemplary embodiment of the present disclosure, realizing a kind of improved lithographic method.According to showing for the disclosure
The lithographic method of example property embodiment passes through gas and etching condition (example employed in the deposition and sputtering in control etching process
Such as, voltage, frequency, power, temperature, time) etc., the ion energy of ion bombardment when can reduce sputtering, to mitigate etching
Damage of the ion bombardment to semiconductor substrate surface in the process reduces white noise, reduces dark current, additionally is able to eliminate SiN quarter
The depth-to-width ratio correlation of erosion etches ARDE effect, thus realize the uniform etching of SiN, it can also in the different SiN structure of depth-to-width ratio
To obtain equivalent etching, additionally it is possible to increase the selection ratio of SiN Yu other substances, so as to avoid other substances in addition to SiN
It is accidentally etched, while there is low-load effect.
In addition, according to an exemplary embodiment of the present disclosure, can also realize a kind of manufacturing method of semiconductor devices.Specifically
Ground provides silicon nitride SiN spacer, then according to the lithographic method pair of the exemplary embodiment of the disclosure in the semiconductor device
SiN spacer performs etching.Furthermore it is also possible to realize a kind of manufacturing method of imaging sensor.Specifically, in imaging sensor
Middle offer semiconductor devices, which includes silicon nitride SiN spacer, then according to the exemplary embodiment of the disclosure
Lithographic method silicon nitride SiN spacer is performed etching.
In the word "front", "rear" in specification and claim, "top", "bottom", " on ", " under " etc., if deposited
If, it is not necessarily used to describe constant relative position for descriptive purposes.It should be appreciated that the word used in this way
Language be in appropriate circumstances it is interchangeable so that embodiment of the disclosure described herein, for example, can in this institute
It is operated in those of description show or other other different orientations of orientation.
As used in this, word " illustrative " means " be used as example, example or explanation ", not as will be by
" model " accurately replicated.It is not necessarily to be interpreted than other implementations in any implementation of this exemplary description
It is preferred or advantageous.Moreover, the disclosure is not by above-mentioned technical field, background technique, summary of the invention or specific embodiment
Given in go out theory that is any stated or being implied limited.
As used in this, word " substantially " means comprising the appearance by the defect, device or the element that design or manufacture
Any small variation caused by difference, environment influence and/or other factors.Word " substantially " also allows by ghost effect, makes an uproar
Caused by sound and the other practical Considerations being likely to be present in actual implementation with perfect or ideal situation
Between difference.
In addition, just to the purpose of reference, can with the similar terms such as " first " used herein, " second ", and
And it thus is not intended to limit.For example, unless clearly indicated by the context, be otherwise related to structure or element word " first ", "
Two " do not imply order or sequence with other such digital words.
It should also be understood that one word of "comprises/comprising" as used herein, illustrates that there are pointed feature, entirety, steps
Suddenly, operation, unit and/or component, but it is not excluded that in the presence of or increase one or more of the other feature, entirety, step, behaviour
Work, unit and/or component and/or their combination.
In the disclosure, therefore term " offer " " it is right to provide certain from broadly by covering all modes for obtaining object
As " including but not limited to " purchase ", " preparation/manufacture ", " arrangement/setting ", " installation/assembly ", and/or " order " object etc..
It should be appreciated by those skilled in the art that the boundary between aforesaid operations is merely illustrative.Multiple operations
It can be combined into single operation, single operation can be distributed in additional operation, and operating can at least portion in time
Divide and overlappingly executes.Moreover, alternative embodiment may include multiple examples of specific operation, and in other various embodiments
In can change operation order.But others are modified, variations and alternatives are equally possible.Therefore, the specification and drawings
It should be counted as illustrative and not restrictive.
In addition, embodiment of the present disclosure can also include following example:
(1) a kind of lithographic method, which comprises the following steps:
Reaction gas is deposited on the surface to be etched of silicon nitride SiN；And
The surface to be etched is sputtered using sputter gas, at least part of the SiN after etching reaction.
(2) method according to 1, which is characterized in that further include:
Before deposition step, Xiang Suoshu reaction gas applies first voltage, and is first etc. by reaction gas excitation
Gas ions；And
Between deposition step and sputter step, Xiang Suoshu sputter gas applies second voltage, and sputter gas is swashed
Hair is the second plasma.
(3) method according to 2, it is characterised in that:
The energy of first plasma is less than SiN reactive ion etching energy；And
The energy of second plasma is greater than SiN reactive ion etching energy.
(4) method according to 2 or 3, it is characterised in that:
The frequency of the first voltage is higher than the frequency of the second voltage.
(5) method according to 1, it is characterised in that:
The reaction gas includes hydrofluorocarbon, and the hydrofluorocarbon includes in CHF3, CH2F2, CH3F, C4H8F2, C4H9F
It is one or more.
(6) method according to 1, it is characterised in that:
Inert gas is also passed through in the deposition step.
(7) method according to 1, it is characterised in that:
The sputter gas includes inert gas and oxygen.
(8) method according to 6 or 7, it is characterised in that:
The inert gas includes one of helium He, neon Ne, argon Ar, krypton Kr, xenon Xe or a variety of.
(9) method according to 1, which is characterized in that further include:
After reaction gas reaction, excessive reaction gas is removed；And
After the sputtering is completed, residue is removed.
(10) method according to 1, which is characterized in that further include:
Deposition and sputter step in repetitive cycling the method, until etching reaches thickness predetermined.
(11) method according to 1, it is characterised in that:
According to the method, the etch amount of SiN is 1nm~5nm after completion primary depositing and sputter step.
(12) a kind of manufacturing method of semiconductor devices, comprising:
Silicon nitride SiN spacer is provided in the semiconductor device；And
The SiN spacer is performed etching according to method described in any one of claim 1-11.
(13) method according to 12, it is characterised in that:
The SiN spacer is gate spacer.
(14) a kind of manufacturing method of imaging sensor, comprising:
Semiconductor devices is provided in the image sensor；And
The semiconductor devices is performed etching according to method described in 12 or 13.
Although being described in detail by some specific embodiments of the example to the disclosure, the skill of this field
Art personnel it should be understood that above example merely to be illustrated, rather than in order to limit the scope of the present disclosure.It is disclosed herein
Each embodiment can in any combination, without departing from spirit and scope of the present disclosure.It is to be appreciated by one skilled in the art that can be with
A variety of modifications are carried out without departing from the scope and spirit of the disclosure to embodiment.The scope of the present disclosure is limited by appended claims
It is fixed.
Claims (10)
1. a kind of lithographic method, which comprises the following steps:
Reaction gas is deposited on the surface to be etched of silicon nitride SiN；And
The surface to be etched is sputtered using sputter gas, at least part of the SiN after etching reaction.
2. the method according to claim 1, wherein further include:
Before deposition step, Xiang Suoshu reaction gas applies first voltage, and is the first plasma by reaction gas excitation
Body；And
Between deposition step and sputter step, Xiang Suoshu sputter gas applies second voltage, and is by sputter gas excitation
Second plasma.
3. according to the method described in claim 2, it is characterized by:
The energy of first plasma is less than SiN reactive ion etching energy；And
The energy of second plasma is greater than SiN reactive ion etching energy.
4. according to the method in claim 2 or 3, it is characterised in that:
The frequency of the first voltage is higher than the frequency of the second voltage.
5. according to the method described in claim 1, it is characterized by:
The reaction gas includes hydrofluorocarbon, and the hydrofluorocarbon includes one of CHF3, CH2F2, CH3F, C4H8F2, C4H9F
Or it is a variety of.
6. according to the method described in claim 1, it is characterized by:
Inert gas is also passed through in the deposition step.
7. according to the method described in claim 1, it is characterized by:
The sputter gas includes inert gas and oxygen.
8. method according to claim 6 or 7, it is characterised in that:
The inert gas includes one of helium He, neon Ne, argon Ar, krypton Kr, xenon Xe or a variety of.
9. the method according to claim 1, wherein further include:
After reaction gas reaction, excessive reaction gas is removed；And
After the sputtering is completed, residue is removed.
10. the method according to claim 1, wherein further include:
Deposition and sputter step in repetitive cycling the method, until etching reaches thickness predetermined.
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|---|---|---|---|---|
| CN106057637A (en) * | 2015-04-03 | 2016-10-26 | 朗姆研究公司 | Deposition of conformal films by atomic layer deposition and atomic layer etch |
| US9779956B1 (en) * | 2017-02-06 | 2017-10-03 | Lam Research Corporation | Hydrogen activated atomic layer etching |
| US20180226260A1 (en) * | 2017-02-06 | 2018-08-09 | Lam Research Corporation | Dielectric contact etch |
| US20180269071A1 (en) * | 2017-03-20 | 2018-09-20 | Lam Research Corporation | Atomic layer etching of silicon nitride |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106057637A (en) * | 2015-04-03 | 2016-10-26 | 朗姆研究公司 | Deposition of conformal films by atomic layer deposition and atomic layer etch |
| US9779956B1 (en) * | 2017-02-06 | 2017-10-03 | Lam Research Corporation | Hydrogen activated atomic layer etching |
| US20180226260A1 (en) * | 2017-02-06 | 2018-08-09 | Lam Research Corporation | Dielectric contact etch |
| US20180269071A1 (en) * | 2017-03-20 | 2018-09-20 | Lam Research Corporation | Atomic layer etching of silicon nitride |
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