CN110376504B - IC high-voltage damage simulation system and method - Google Patents
IC high-voltage damage simulation system and method Download PDFInfo
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- CN110376504B CN110376504B CN201910566192.5A CN201910566192A CN110376504B CN 110376504 B CN110376504 B CN 110376504B CN 201910566192 A CN201910566192 A CN 201910566192A CN 110376504 B CN110376504 B CN 110376504B
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2836—Fault-finding or characterising
- G01R31/2839—Fault-finding or characterising using signal generators, power supplies or circuit analysers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
The invention relates to a simulation system and a method for IC high-voltage damage, wherein the system comprises a control device, a voltage pulse source device and a detection device; the control device is connected with the voltage device and the voltage pulse source device and is used for controlling the voltage device and the voltage pulse source device; the voltage device is used for providing working voltage for the IC to be detected; the voltage pulse source device is used for outputting level pulses to pins to be detected of the IC to be detected; the detection device is used for collecting the pressure resistance degree and the damage degree of the IC to be detected and generating a database. High-voltage damage simulation is carried out on the IC to be detected to form a specific database of each IC, when the IC fails, failure data are led into the database to be compared, the voltage state and the path which cause damage can be reversely deduced, root tracing and source tracing are achieved, failure sources are rapidly located, and the efficiency of solving the terminal problems is improved.
Description
Technical Field
The invention relates to the technical field of ICs (integrated circuits), in particular to a system and a method for simulating high-voltage damage of an IC.
Background
Electrical Overstress (EOS) is a common cause of damage to components, and is expressed in that overvoltage or overcurrent generates a large amount of heat energy, so that the internal temperature of the components is too high to damage the components (what is often called burn-out), which is a common way of damaging electronic devices due to pulses in an Electrical system. In the existing IC failure analysis technology, the chip can only be positioned where the chip is damaged by high voltage through technical means such as I/V, SAT, Thermal and the like, but the conclusion cannot be given: the high voltage is from where and from which PIN (PIN). The effect on solving the practical problem is very small. Especially, when the internal module of the chip is damaged, but no failure hot spot is found, the existing failure analysis means loses the effect, and the failure analysis direction loses.
Disclosure of Invention
Therefore, a system and a method for simulating the IC high-voltage damage are needed to be provided, so as to solve the problem that the existing FA technology can only determine the damage position and cannot provide the damage source and path for the EOS failure with the highest percentage in the actual terminal product production.
In order to achieve the above object, the inventor provides a system for simulating IC high voltage damage, comprising a control device, a voltage pulse source device and a detection device;
the control device is connected with the voltage device and the voltage pulse source device and is used for controlling the voltage device and the voltage pulse source device;
the voltage device is used for providing working voltage for the IC to be detected;
the voltage pulse source device is used for outputting level pulses to the pin to be detected of the IC to be detected;
the detection device is used for collecting the pressure resistance degree and the damage degree of the IC to be detected and generating a database.
The system is further optimized, and further comprises a real-time monitoring device, wherein the real-time monitoring device is connected to the control device and is used for acquiring state data of a pin to be detected of the IC to be detected and sending feedback information to the control device;
and the control device is used for controlling the voltage pulse source device to output the next group of level pulses after receiving the feedback information.
Further optimizing, the real-time monitoring device is also used for preliminarily detecting the damage of the IC to be detected;
the detection device is also used for collecting the pressure resistance degree and the damage degree of the IC to be detected and generating a database when the real-time monitoring device preliminarily detects that the IC to be detected is damaged.
Further optimizing, the device also comprises a switching device, and the voltage pulse source device injects level pulses into the IC to be detected through the switching device;
the switch device is connected to the control device and used for configuring the state of a pin to be detected of the IC to be detected and configuring the pulse period of a level pulse input into the IC to be detected.
Further preferably, the switch device is further used for switching the connection of the pin to be tested of the IC to be tested.
The inventor also provides another technical scheme that: a simulation method for IC high voltage damage comprises the following steps:
the control device is configured and provides working voltage of the IC to be detected through the voltage device;
the control device configures a pulse level value of a voltage pulse source device and inputs a level pulse to a pin to be detected of the IC to be detected through the voltage pulse source device;
the detection device collects the pressure resistance degree and the damage degree of the IC to be detected and generates a database.
Further optimization, the method also comprises the following steps after the voltage pulse source device inputs the level pulse to the pin to be detected of the IC to be detected:
the real-time monitoring device collects state data of a pin to be detected of the IC to be detected and sends feedback information to the control device;
and after the monitoring device receives the feedback information, controlling the voltage pulse source device to output the next group of level pulses.
Further optimizing, the step of acquiring the withstand voltage degree and the damage degree of the IC to be detected by the detection device and generating the database specifically comprises the following steps of:
when the real-time monitoring device preliminarily detects that the IC to be detected is damaged, the detection device collects the withstand voltage degree and the damage degree of the IC to be detected and generates a database.
Further optimization, before the control device configures and provides the working voltage of the IC to be detected through the voltage device, the method also comprises the following steps:
the control device configures the state of a pin to be tested of the IC to be tested through the switch device;
the step of inputting level pulses to the pin to be tested of the IC to be tested through the voltage pulse source device specifically comprises the following steps:
configuring a pulse period of a level pulse input to an IC to be detected through a switching device;
the voltage pulse source device injects level pulse to the IC to be detected through the switch device.
Further optimization, the method also comprises the following steps before the control device configures the state of the pin to be tested of the IC to be tested through the switch device;
the control device is switched to the pin to be detected of the IC to be detected through the switch device and establishes connection.
Different from the prior art, according to the technical scheme, the high-voltage damage simulation is carried out on the ICs to be detected to form a specific database of each IC, when the ICs fail, failure data are led into the database to be compared, the voltage state and the path which cause damage can be reversely deduced, the root tracing and the source locating are realized, the failure source is quickly located, and the solution efficiency of the terminal problem is improved.
Drawings
FIG. 1 is a schematic diagram of an embodiment of a system for simulating IC high voltage damage;
fig. 2 is a schematic flow chart of a method for IC high voltage damage simulation according to an embodiment.
Description of reference numerals:
110. a control device;
120. a voltage device;
130. a voltage pulse source device;
140. a detection device;
150. detecting an IC;
160. a real-time monitoring device;
170. a switching device.
Detailed Description
To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Referring to fig. 1, the present embodiment provides a system for simulating IC high voltage damage, which includes a control device 110, a voltage device 120, a voltage pulse source device 130, and a detection device 140;
the control device 110 is connected to the voltage device 120 and the voltage pulse source device 130, and the control device 110 is used for controlling the voltage device 120 and the voltage pulse source device 130;
the voltage device 120 is used for providing working voltage for the IC150 to be detected;
the voltage pulse source device 130 is configured to output a level pulse to a pin to be tested of the IC150 to be tested;
the detection device 140 is used for acquiring the withstand voltage degree and the damage degree of the IC to be detected and generating a database.
When performing high-voltage damage simulation on the IC150 to be detected, firstly, the control device 110 controls the voltage device 120 and the voltage pulse source device 130, configures the working voltage of the IC150 to be detected through the voltage device 120, and provides the working voltage for the IC150 to be detected; then, a pulse level value is configured through the voltage pulse source device 130, a level pulse is injected into a pin to be detected of the IC150 to be detected, the voltage withstanding degree and the damage degree of the IC150 to be detected are detected in detail through the detection device 140, and a database is generated. The voltage level or the voltage pulse causes damage to the IC150 to be tested, and the damage level is the voltage level or the voltage pulse causes damage to the IC. By establishing a database corresponding to the damage path and the failure phenomenon, when the IC fails, failure data is imported into the database for comparison, so that the voltage state and the path which cause damage can be reversely deduced, the root tracing and the source locating are realized, the failure source is rapidly positioned, and the solution efficiency of the terminal problem is improved. Meanwhile, the condition that a voltage-resistant element in the IC is selected wrongly can be effectively found in the early stage of chip development, and the conformity of the voltage in the design specification and an actual product is checked by a system for the first time; moreover, FA (Failure Analysis) cost can be effectively saved, accurate Analysis can be achieved, the time required by FA can be saved, and timely improvement of online projects is particularly facilitated; and the accuracy and the margin of the theoretical voltage parameters can be systematically checked.
In this embodiment, the apparatus further includes a real-time monitoring device 160, the real-time monitoring device 160 is connected to the control device 110, and the real-time monitoring device 160 is configured to collect status data of a pin to be tested of the IC150 to be tested, and send feedback information to the control device 110; the control device 110 is configured to control the voltage pulse source device 130 to output the next set of level pulses after receiving the feedback information. The monitoring device is used for acquiring state data of the pin to be detected of the IC150 to be detected, wherein the state data comprises voltage parameters, current parameters and whether the pin to be detected is damaged or not, when the pin to be detected is not damaged, feedback information is sent to the control device 110, and when the control information receives the feedback information, the voltage pulse source is controlled to output a next group of level pulses to be poured into the pin to be detected of the IC150 to be detected, so that high-voltage damage of the IC150 to be detected is rapidly simulated, and the efficiency is improved.
The real-time monitoring device 160 is further configured to preliminarily detect a damage of the IC150 to be detected; the detecting device 140 is further configured to collect the withstand voltage and the damage of the IC to be detected when the real-time monitoring device 160 preliminarily detects that the IC150 to be detected is damaged, and generate a database. When the real-time monitoring device 160 preliminarily detects that the IC150 to be detected is damaged, the withstand voltage degree and the damage degree of the IC to be detected are acquired, so that the energy consumption of the detection device 140 can be reduced, and the detection efficiency of the detection device 140 can be improved.
In this embodiment, the IC testing device further includes a switching device 170, and the voltage pulse source device 130 injects a level pulse to the IC150 to be tested through the switching device 170; the switching device 170 is connected to the control device 110, and the switching device 170 is configured to configure a state of a pin to be tested of the IC150 to be tested and configure a pulse period of a level pulse input to the IC150 to be tested. Before the high-voltage damage simulation of the IC150 to be detected is started, the state of the pin to be detected of the IC150 to be detected is configured through the switch device 170, the accuracy of the high-voltage damage simulation can be improved, meanwhile, the pulse period of the level pulse injected into the IC150 to be detected is configured through the switch device 170, the high-voltage damage can be simulated efficiently, and meanwhile, the damage degree of the level pulse of different pulse periods to the IC150 to be detected is obtained.
In this embodiment, the switch device 170 is further used for switching the connection of the pin to be tested of the IC150 to be tested. Before the high-voltage damage simulation, the connection of the pins to be detected of the IC150 to be detected is switched through the switching device 170, so that the damage condition of the different pins to be detected of the IC150 to be detected, which are filled with level pulses, to the IC150 to be detected can be quickly established, and the high-voltage damage simulation efficiency can be improved.
Referring to fig. 2, in another embodiment, a method for simulating IC high voltage damage includes the following steps:
step S210: the control device is configured and provides working voltage of the IC to be detected through the voltage device;
step S220: the control device configures a pulse level value of a voltage pulse source device and inputs a level pulse to a pin to be detected of the IC to be detected through the voltage pulse source device;
step S230: the detection device collects the pressure resistance degree and the damage degree of the IC to be detected and generates a database.
When the IC to be detected is subjected to high-voltage damage simulation, firstly, the control device controls the voltage device and the voltage pulse source device, the working voltage of the IC to be detected is configured through the voltage device, and the working voltage is provided for the IC to be detected; and then configuring a pulse level value through a voltage pulse source device, injecting a level pulse into a pin to be detected of the IC to be detected, detecting the withstand voltage degree and the damage degree of the IC to be detected in detail through a detection device, and generating a database. The voltage level or voltage pulse causes damage to the IC to be tested, and the damage level is the level of damage caused by the voltage level or voltage pulse and the damage caused by the voltage pulse. By establishing a database corresponding to the damage path and the failure phenomenon, when the IC fails, failure data is imported into the database for comparison, so that the voltage state and the path which cause damage can be reversely deduced, the root tracing and the source locating are realized, the failure source is rapidly positioned, and the solution efficiency of the terminal problem is improved. Meanwhile, the condition that a voltage-resistant element in the IC is selected wrongly can be effectively found in the early stage of chip development, and the conformity of the voltage in the design specification and an actual product is checked by a system for the first time; moreover, FA (Failure Analysis) cost can be effectively saved, accurate Analysis can be achieved, the time required by FA can be saved, and timely improvement of online projects is particularly facilitated; and the accuracy and the margin of the theoretical voltage parameters can be systematically checked.
In this embodiment, the step of inputting a level pulse to a pin to be tested of the IC to be tested through the voltage pulse source device further includes:
step S241: the real-time monitoring device collects state data of a pin to be detected of an IC to be detected;
step S242: the real-time monitoring device sends feedback information to the control device;
step S243: and after the monitoring device receives the feedback information, controlling the voltage pulse source device to output the next group of level pulses.
The method comprises the steps that the monitoring device is used for collecting state data of a pin to be detected of the IC to be detected, wherein the state data comprises voltage parameters, current parameters and whether the pin to be detected is damaged or not, when the pin to be detected is not damaged, feedback information is sent to the control device, and when the control information receives the feedback information, the voltage pulse source is controlled to output a next group of level pulses to be poured into the pin to be detected of the IC to be detected, so that high-voltage damage simulation of the IC to be detected is rapidly simulated, and the efficiency is improved.
The detection device collects the pressure resistance degree and the damage degree of the IC to be detected and generates the database, and the method specifically comprises the following steps of:
when the real-time monitoring device preliminarily detects that the IC to be detected is damaged, the detection device collects the withstand voltage degree and the damage degree of the IC to be detected and generates a database.
When the real-time monitoring device preliminarily detects that the IC to be detected is damaged, the withstand voltage degree and the damage degree of the IC to be detected are acquired, so that the energy consumption of the detection device can be reduced, and meanwhile, the detection efficiency of the detection device can be improved.
In this embodiment, before the step of configuring and providing the operating voltage of the IC to be tested by the control device through the voltage device, the method further includes the following steps:
the control device configures the state of a pin to be tested of the IC to be tested through the switch device;
the step of inputting level pulses to the pin to be tested of the IC to be tested through the voltage pulse source device specifically comprises the following steps:
configuring a pulse period of a level pulse input to an IC to be detected through a switching device;
the voltage pulse source device injects level pulse to the IC to be detected through the switch device.
Before starting to carry out high-voltage damage simulation on the IC to be detected, the state of the pin to be detected of the IC to be detected is configured through the switch device, the high-voltage damage simulation accuracy can be achieved, meanwhile, the pulse period of the level pulse injected into the IC to be detected is configured through the switch device, the high-voltage damage can be simulated efficiently, and meanwhile, the damage degree of the level pulse of different pulse periods to the IC to be detected is obtained.
In this embodiment, the step of configuring the state of the pin to be tested of the IC to be tested by the control device through the switch device further includes the following steps;
the control device is switched to the pin to be tested of the IC to be tested through the switch device and establishes connection.
Before high-voltage damage simulation, the connection of the pins to be detected of the IC to be detected is switched through the switching device, so that the damage condition of different pins to be detected of the IC to be detected, which is caused by level pulse poured into the pins to be detected, to the IC to be detected can be quickly established, and the high-voltage damage simulation efficiency can be improved.
It should be noted that, although the above embodiments have been described herein, the scope of the present invention is not limited thereby. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present invention.
Claims (10)
1. A simulation system for IC high voltage damage is characterized in that the simulation system comprises a control device, a voltage pulse source device and a detection device;
the control device is connected with the voltage device and the voltage pulse source device and is used for controlling the voltage device and the voltage pulse source device;
the voltage device is used for providing working voltage for the IC to be detected;
the voltage pulse source device is used for outputting level pulses to the pin to be detected of the IC to be detected and simulating different level pulses to damage the IC to be detected;
the detection device is used for acquiring the withstand voltage degree and the damage degree of the IC to be detected and generating a database corresponding to the damage path and the failure phenomenon;
the database is used for reversely deducing a voltage state and a damage path which cause damage of the failed IC through comparison when the failure data of the failed IC is imported.
2. The IC high-voltage damage simulation system according to claim 1, further comprising a real-time monitoring device, wherein the real-time monitoring device is connected to the control device, and is configured to collect status data of a pin to be tested of the IC to be tested, and send feedback information to the control device;
and the control device is used for controlling the voltage pulse source device to output the next group of level pulses after receiving the feedback information.
3. The IC high voltage damage simulation system of claim 2, wherein the real-time monitoring device is further configured to preliminarily detect an occurrence of damage to the IC to be detected;
the detection device is also used for collecting the withstand voltage degree and the damage degree of the IC to be detected and generating a database when the real-time monitoring device preliminarily detects that the IC to be detected is damaged.
4. The IC high voltage damage simulation system of claim 1, further comprising a switch device, wherein the voltage pulse source device injects a level pulse to the IC to be tested through the switch device;
the switching device is connected to the control device and used for configuring the state of a pin to be detected of the IC to be detected and configuring the pulse period of a level pulse input into the IC to be detected.
5. The IC high voltage damage simulation system of claim 4, wherein the switch device is further configured to switch the connection of a pin under test of the IC to be tested.
6. A method for simulating IC high voltage damage is characterized by comprising the following steps:
the control device is configured and provides working voltage of the IC to be detected through the voltage device;
the control device is configured with a voltage pulse source device pulse level value, and inputs level pulses to a pin to be detected of the IC to be detected through the voltage pulse source device to simulate different level pulses to damage the IC to be detected;
the detection device collects the voltage withstanding degree and the damage degree of the IC to be detected and generates a database of damage paths corresponding to failure phenomena, and the database is used for reversely deducing the voltage state and the damage paths which cause damage of the failed IC through comparison when failure data of the failed IC are imported.
7. The method for simulating the high voltage damage of the IC according to claim 6, wherein the step of inputting the level pulse to the pin to be tested of the IC to be tested by the voltage pulse source device further comprises the following steps:
the real-time monitoring device collects state data of a pin to be detected of the IC to be detected and sends feedback information to the control device;
and after the control device receives the feedback information, the voltage pulse source device is controlled to output the next group of level pulses.
8. The method for simulating the high-voltage damage of the IC according to claim 7, wherein the step of acquiring the withstand voltage degree and the damage degree of the IC to be detected by the detection device and generating the database of the damage path corresponding to the failure phenomenon comprises the following steps:
when the real-time monitoring device preliminarily detects that the IC to be detected is damaged, the detection device collects the withstand voltage degree and the damage degree of the IC to be detected and generates a database.
9. The method for simulating high voltage damage of an IC according to claim 6, wherein the step of configuring and providing the operating voltage of the IC to be tested by the control device via the voltage device comprises the following steps:
the control device configures the state of a pin to be tested of the IC to be tested through the switch device;
the step of inputting level pulses to the pin to be tested of the IC to be tested through the voltage pulse source device specifically comprises the following steps:
configuring a pulse period of a level pulse input to an IC to be detected through a switching device;
the voltage pulse source device injects level pulse to the IC to be detected through the switch device.
10. The method for simulating the high voltage damage of the IC according to claim 9, wherein the step before the step of configuring the state of the pin to be tested of the IC to be tested by the control device through the switch device further comprises the following steps;
the control device is switched to the pin to be tested of the IC to be tested through the switch device and establishes connection.
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| JP3701954B2 (en) * | 2003-07-08 | 2005-10-05 | 松下電器産業株式会社 | Semiconductor integrated circuit, electrostatic withstand voltage test method and apparatus thereof |
| JP4914589B2 (en) * | 2005-08-26 | 2012-04-11 | 三菱電機株式会社 | Semiconductor manufacturing apparatus, semiconductor manufacturing method, and semiconductor device |
| TWI288241B (en) * | 2005-11-30 | 2007-10-11 | Ip Leader Technology Corp | Probing apparatus, probing print-circuit board and probing system for high-voltage matrix-based probing |
| CN100523850C (en) * | 2006-12-13 | 2009-08-05 | 上海华虹Nec电子有限公司 | System plate and method for testing chip with high pressure |
| CN102109573B (en) * | 2009-12-23 | 2013-06-12 | 杭州士兰微电子股份有限公司 | Device and method for testing dV/dt tolerance of high voltage integrated circuit |
| CN108318803A (en) * | 2018-01-30 | 2018-07-24 | 中国空间技术研究院 | Chip single particle radiation test method, device, system and database building method |
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