CN110366781B

CN110366781B - Power MOSFET with deep source contact

Info

Publication number: CN110366781B
Application number: CN201780087729.9A
Authority: CN
Inventors: 林福任; F·巴约奇; H·林; Y·刘; L·刘; W·宋; Z·赵
Original assignee: Texas Instruments Inc
Current assignee: Texas Instruments Inc
Priority date: 2017-01-19
Filing date: 2017-01-19
Publication date: 2023-07-21
Anticipated expiration: 2037-01-19
Also published as: JP2021192431A; JP2020515050A; US10746890B2; US20180204917A1; JP6926212B2; JP7288287B2; US20190004201A1; CN110366781A; WO2018132991A1; US10068977B2

Abstract

A power MOSFET IC device includes an array of MOSFET cells (300A, 300B) formed in a semiconductor substrate. The array of MOSFET cells includes an inner region of inner MOSFET cells (300A) and an outer edge region of outer MOSFET cells (300B), each inner MOSFET cell of the inner region of the array including an inner MOSFET device pair coupled to each other at a common drain contact (314). In one example embodiment, each internal MOSFET device includes a Source Contact Trench (SCT) extending into a substrate contact region of a semiconductor substrate. An SCT trench is provided having a length (303) that is less than a linear portion (310A) of a polysilicon gate (312) of an internal MOSFET device, wherein the SCT trench is aligned with the polysilicon gate (312) having a curvilinear layout geometry.

Description

Power MOSFET with deep source contact

Technical Field

The present disclosure relates generally to the field of semiconductor devices and methods of manufacturing the same, and more particularly, but not by way of limitation, to power MOSFET devices and manufacturing the same.

Background

Power MOSFETs are a specific type of metal oxide semiconductor field effect transistor designed to handle significant power levels (e.g., typically involving a switch of greater than 1A). Power MOSFETs are well known for superior switching speeds and are used in many applications such as power supplies, DC-DC converters, piezoelectric controllers, and switches in other high frequency Pulse Width Modulation (PWM) applications.

Efficiency and power loss in microelectronic devices including power MOSFETs are major problems in power electronics applications. Engineers are continually challenged to increase power density while reducing the amount of power consumed in an application. The reduced power consumption helps to keep the device temperature below regulation, which results in a continuing need for better operating efficiency in power MOSFET applications. For example, conventional approaches for improving the efficiency of DC/DC synchronous buck converters include by designing a lower on-state resistance (R _DSON ) The device reduces conduction losses in the MOSFET and reduces switching losses by reducing device capacitance. However, for realizing R _DSON The current technology of progressive improvement of (c) is at a point of diminishing returns due to the tradeoff between the breakdown voltage of the device and its on-state resistance. This is because the breakdown voltage of the device directly affects the resistance contribution.

As integrated circuit designs and semiconductor fabrication continue to advance, improvements in semiconductor devices (including power MOSFETs) are also being pursued.

Disclosure of Invention

The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is intended to neither identify key or critical elements of the disclosure nor delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the disclosure in a simplified form as a prelude to the more detailed description that is presented later.

In one aspect, embodiments of an IC, such as a power mosfet IC, and fabrication thereof, are disclosed that overcome several challenges that may be encountered in processing deep Source Contact (SCT) trench features required in an IC fabrication flow by utilizing one or more innovative deep Source Contact (SCT) trench layout design enhancements. An example IC includes, among other things, a semiconductor substrate having a top surface and a bottom surface; and at least one MOSFET cell formed on the semiconductor substrate. The MOSFET cells include a pair of MOSFET devices coupled to each other at a common drain contact, wherein at least one MOSFET device includes an SCT trench that extends to a substrate contact region in the semiconductor substrate near the bottom surface. An SCT trench is provided having a length along the top surface that is less than a linear portion of the polysilicon gate of the at least one MOSFET device, wherein the SCT trench is aligned with a complementary profile (e.g., self-aligned source) of the polysilicon gate having a curvilinear layout geometry.

In another aspect, embodiments of a laterally diffused metal oxide semiconductor transistor (LDMOS) device are disclosed that include, inter alia: a semiconductor substrate having a top surface and a bottom surface, the semiconductor substrate having a doped layer positioned adjacent the top surface and having an upper surface; a source region and a drain region of the first conductivity type formed in the doped layer proximate an upper surface of the doped layer, the source region and the drain region being spaced apart from one another and separated by a channel region of the second conductivity type formed in the doped layer, the channel region having a portion extending below the source region, wherein the drain region includes a doped drain (e.g., LDD) region formed adjacent the channel region; a doped drain contact region separated from the channel region by a lightly doped drain region; a conductive gate having an upper surface and a sidewall surface, the conductive gate formed over a gate dielectric layer formed over the channel region, the conductive gate at least partially overlapping the source and drain regions; and a conductive path connecting the source region and the doped substrate via a conductor disposed in an SCT trench formed in the doped layer and extending into a substrate contact region in the semiconductor substrate. The length of the SCT trench, e.g., defined along the upper surface of the doped layer or the top surface of the semiconductor substrate, is less than the linear portion of the conductive gate, the SCT trench being aligned with the conductive gate formed to have a curvilinear geometry; a first insulating layer formed over an upper surface and sidewall surfaces of the conductive gate; a field plate provided over the lightly doped drain region and at least a portion of the first insulating layer, wherein the field plate is connected to the source; a second insulating layer formed over the field plate, the first insulating layer, and the trench; and a drain electrode electrically coupled to the drain contact region.

In a further aspect, a method of fabricating a power MOSFET integrated circuit, such as the LDMOS device set forth above, is disclosed that includes constraining SCT trench features to a linear portion of a polysilicon gate. In another embodiment, the edge cells of the array of power MOSFET cells (also referred to as termination cells) are fabricated to include inactive portions, in which SCT trenches and associated source regions are not formed, thereby specifically achieving non-functional portions in the edge cells. In yet another embodiment involving an edge cell having a non-active portion, a ground tab may be provided at the die edge to ensure that the die edge field plate associated with the non-active portion is at a stable potential during device operation. In further related embodiments involving edge cells having non-active portions, the edge cells may have a different feature geometry (e.g., internal cells or non-termination cells) than other cells of the MOSFET cell array.

Drawings

Embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements. It should be noted that different references to "an embodiment" or "one embodiment" in this disclosure are not necessarily to the same embodiment, and such references may mean at least one. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

The accompanying drawings are incorporated in and form a part of this specification to illustrate one or more exemplary embodiments of the present disclosure. Various advantages and features of the present disclosure will be understood by reference to the following detailed description taken in conjunction with the appended claims and with the accompanying drawings in which:

fig. 1 depicts a cross-sectional view of a portion of an example power MOSFET integrated circuit or device, according to one embodiment of the disclosure;

fig. 2 is a flow chart associated with a method of manufacturing a power MOSFET integrated circuit according to one embodiment of the present disclosure.

Fig. 3A-3C depict layout diagrams of example power MOSFET cells in accordance with one or more embodiments of the present disclosure;

fig. 4A depicts a cross-sectional view of the internal power MOSFET cell layout shown in fig. 3A, according to an example embodiment of the present disclosure; and

fig. 4B depicts a cross-sectional view of the external power MOSFET cell layout shown in fig. 3B, according to an example embodiment of the present disclosure.

Detailed Description

The present disclosure is described with reference to the drawings, wherein like reference numerals are generally used to refer to like elements throughout. The drawings are not to scale and are provided merely to illustrate the invention. For purposes of illustration, several aspects of the disclosure are described below with reference to example applications. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the disclosure. One skilled in the relevant art will readily recognize, however, that the disclosure may be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the disclosure. The present disclosure is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. In addition, not all illustrated acts or events are required to implement a methodology in accordance with the present disclosure.

In the following description, reference may be made to the accompanying drawings, in which certain directional terms (such as, for example, "upper," "lower," "top," "bottom," "left," "right," "front," "rear," "vertical," "horizontal," etc.) may be used with reference to the described drawings or orientations of the illustrative elements thereof. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. Also, references to features referred to as "first," "second," etc. do not indicate any particular order, importance, etc., and such references may be interchanged with one another as necessary depending on the context, implementation, etc. It is to be understood that additional embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Features of various exemplary embodiments described herein may be combined with one another unless specifically stated otherwise.

As used in this specification, the terms "coupled," "electrically coupled," "connected," or "electrically connected" do not mean that the elements must be directly coupled or connected together. Intervening elements may be provided between "coupled," "electrically coupled," "connected," or "electrically connected" elements.

The example semiconductor devices described below may include, or may be formed of, a semiconductor material, such as Si, siC, siGe, gaAs or an organic semiconductor material. The semiconductor material may be embodied as a semiconductor wafer or semiconductor chip containing one or more power MOSFET integrated circuits, input/output and control circuits, as well as microprocessors, microcontrollers and/or microelectromechanical components or systems (MEMS), etc. The semiconductor chip may also include inorganic and/or organic materials that are not semiconductors, such as insulators (such as dielectric layers, plastics or metals, etc.).

Referring now to the drawings and more particularly to fig. 1, depicted therein is a cross-sectional view of a portion of an example power MOSFET device 100 in accordance with one embodiment of the present disclosure in which one or more layout design innovations may be implemented to overcome certain problems associated with fabricating semiconductor devices having high aspect ratio features, such as deep source contact trenches. By way of illustration, the example power MOSFET device 100 is shown as a planar gate power MOSFET device with a metal-filled deep Source Contact (SCT) 120, which can be formed in a trench of semiconductor substrate material. In an example embodiment, the deep source contact 120 may be formed as a metal plug including a refractory metal filler 122, which refractory metal filler 122 may include a Platinum Group Metal (PGM) that connects the source region 127 formed in the body 114 of the power MOSFET cell portion 110A or 110B to the substrate contact region 139. In one example embodiment, tungsten may be used as the refractory metal filler. The refractory metals are distinguished by their heat resistance, with five industrial refractory metals (molybdenum (Mo), niobium (Nb), rhenium (Re), tantalum (Ta) and tungsten (W)) all having a melting point in excess of 2000 ℃, with tungsten having a melting point of 3422 ℃. Exemplary PGMs include iridium (Ir), osmium (Os), palladium (Pd), platinum (Pt), and rhodium (Rh), wherein Pt and Pd have melting points of 1769 ℃ and 1554 ℃, respectively. Such melting points may be compared to aluminum (Al) (not refractory metals or PGMs), which has a melting point of only 660 ℃ and is therefore not ideal for forming the disclosed metal-filled deep SCT 120.

In one example embodiment, power MOSFET 100 includes a doped layer 108 positioned near a top surface of substrate 105. Doped layer 108 may be developed as an epitaxial (epi) layer or formed by ion implantation. As previously described, the substrate 105 and/or epitaxial layer 108 may include silicon, silicon germanium, or other semiconductor materials. However, in some additional or alternative embodiments, MOSFET 100 can be formed directly on substrate 105 (such as a substrate comprising bulk silicon with appropriate doping species and concentrations). In one embodiment, the doped layer 108 is a lightly doped epitaxial layer 108 on a more heavily doped substrate 105 and has a layer thickness designed to increase the device breakdown voltage.

Thus, in embodiments of the present disclosure, power MOSFET 100 may be considered a semiconductor structure having a doped substrate (e.g., substrate 105) with a bottom surface and a top surface, and a doped layer (e.g., epi 108) positioned adjacent the top surface and having an upper surface, wherein source and drain regions of a first conductivity type may be formed in the doped layer proximate the upper surface of the doped layer, the source and drain regions being spaced apart from each other and separated by a channel region of a second conductivity type formed in the doped layer, the channel region having a portion extending below the source region, and further wherein the drain region forms a doped region 129 adjacent the channel region formed in body 114. In one example embodiment, doped region 129 includes a Lightly Doped Drain (LDD) having a lighter concentration than drain region 132.

In one example, the MOSFET IC 100, the drain region 132 may be provided with a Drain Contact (DCT) 130. The DCT 130 includes a metal plug 130A lined with a barrier metal 130B. In one embodiment, barrier metal liner 130 comprises titanium and/or titanium nitride (Ti/tin). Laterally surrounding a portion of the deep SCT 120, a source region 127 is coupled to the deep SCT 120. The source region 127 is typically formed by ion implantation. The deep SCT 120 provides a low resistance contact to the source region 127 by means of the metal fill 122. The deep SCT 120 connects the source 127 to the epi layer 108 or substrate 105 via a highly doped substrate contact region 139 (p+ doped for P-type substrates) (optionally through a thin region of the epi layer 108) at the bottom of the deep SCT 120 so that during operation when the power MOSFET 100 is on, current can flow vertically downward with minimal resistance and out the back side of the substrate 105 (e.g., semiconductor die) (in the example source-down embodiment).

Thus, for external circuitry, the backside of the substrate 105 may typically operate as a source lead. The topside metal (which would be on top of dielectric layer(s) 138 and coupled to the drain contact through dielectric layer 138 to drain 132) is operable as a drain lead. At the bottom of the deep SCT 120 is a substrate contact region 139, as described above, the substrate contact region 139 is typically implanted, which is the same type of doping as the epi layer 108 after etching the trench for the deep SCT 120. In an illustrative manufacturing flow, the substrate contact region 139 may have a boron doping level of about 1x10 ²⁰ cm ^-3 (e.g., 5X 10) ¹⁹ cm ^-3 Up to 1x10 ²¹ cm ^-3 ) To provide a low resistance ohmic contact to the substrate 105.

With continued reference to fig. 1, it should be appreciated that two separate power MOSFET devices 110A and 110B are shown forming a cell that can be used as a power MOSFET device building block, each device being defined from the midpoint of the deep SCT 120 to the midpoint of the DCT 130 in the exemplary arrangement shown in fig. 1. However, the skilled artisan will recognize that an actual power MOSFET device may be considered a 2D transistor array, as there may be hundreds or thousands of individual active MOSFET cells electrically coupled together in parallel, and that an example cell may be defined from the midpoint of one SCT to the midpoint of the next SCT. Thus, depending on how the repeating unit is defined, a 2D transistor array for forming a power MOSFET device is typically built in the circuit design by repeating a mirror image of a unit cell comprising two devices 110A, 110B, which devices 110A, 110B are coupled to each other by a common SCT or a common DCT.

The individual power MOSFET devices 110A/110B also include respective gate electrodes or gate stacks, e.g., gates 111A, 111B, formed over a suitable gate dielectric layer 112. Additionally or alternatively, an optional silicide layer 113A/113B may be provided as part of the gate stack of the MOSFET device. Whether or not a multi-layer stack is implemented, an insulating layer (e.g., first insulating layer 143 formed over the spacers above the sidewall surfaces and extending beyond the top surface of the stack) may be provided as a dielectric barrier. Furthermore, the gates/stacks 111A/1113A and 111B/1113B of the power MOSFET cells 110A/110B are each independently electrically coupled together by another metal or doped poly element (not shown) that may typically be connected to the gate electrode terminal of the device package. Since the transistor cell array is typically built up from repeated mirror images of the unit cells, it should be appreciated that one DCT 130 shares two gates on either side as shown in the example arrangement of FIG. 1, just as one deep SCT 120 shares two gates on either side.

The source field plate 117 may be provided as an extension of the deep SCT structure 120 to operate as a source metal envelope or extension adjacent to the respective gate electrode of the power MOSFET cell 110A/110B. In one example embodiment, the source Field Plate (FP) 117 may comprise a layer or stack of layers of refractory metal material formed of a material such as TiN/Ti, tungsten, ti-tungsten (Ti-W), or the like. In some embodiments, the refractory metal may be provided as a poly-silicon based material or stack. In addition, such refractory metal materials may also be provided at the bottom of the deep SCT 120. In an example fabrication flow, a Rapid Thermal Annealing (RTA) step may be performed after TiN/Ti deposition, which in one embodiment with epi layer 108 results in the formation of titanium silicide at the Ti/Si interface. This formation of metal silicide may also facilitate good ohmic contact between the deep SCT 120 and the epi layer 108 (or substrate 105).

With continued reference to the cross-sectional view of fig. 1, fabrication of the example power MOSFET device 100 can include forming one or more dielectric layers 138 over the gate stacks 111A/113A and 111B/113B and around and/or over the FP 117. Typically, such dielectric layer 138 may comprise a dielectric stack formed from one or more deposited silicon oxide layers, such as tetraethyl orthosilicate (TEOS) -derived boron and phosphorus doped TEOS (BPTEOS)/TEOS layers, which may be based on standard interlayer dielectric processing (deposition/lithography/etching).

In one example embodiment, a tilt implant step may also be provided, which facilitates a tilt implant of an appropriate species into the sidewall regions of SCT trench 120 to form doped liner 136 prior to forming metal fill 122. Those skilled in the art will recognize that such a tilted implant may help reduce the resistance between body region 114 (e.g., P-doped) and substrate 105 or epi layer 108. For power MOSFET device 100, illustrated as an NMOS device, the angled trench implant utilizes a first conductivity type (e.g., p-type). In general, implantation parameters for angled implants including boron may include from 1x10 ¹⁴ cm ^-2 To 5x10 ¹⁵ cm ^-2 A dose range of 20keV to 60keV, an energy range of 5 degrees to 25 degrees.

The skilled person will appreciate that the disclosed MOSFET has a form similar to an LDMOS (laterally diffused MOSFET) structure, which in some embodiments may be implemented as an asymmetric power MOSFET designed for low on-resistance and high blocking voltage. As used herein, an LDMOS device may be considered synonymous with a Diffused Metal Oxide Semiconductor (DMOS) device. In addition to tungsten (W), the metal fill 122 may also include other refractory metals (such as Ta) or PGMs (such as Pt or Pd), their metal silicides, or metal alloys of such metals (including Ti-W).

Although NMOS transistors are generally described herein, it should be apparent to those of ordinary skill in the art that PMOS transistors are also formed using the disclosure of the present patent application by replacing the n-doped regions with p-doped regions, and vice versa, wherein the resulting structures are generally similar. For example, the difference in the disclosed NMOS power MOSFET device versus PMOS power MOSFET device may involve the use of opposite types of doping, e.g., a P/p+ substrate for NMOS to an N/n+ substrate for PMOS, source and drain regions to change from N-type doping for NMOS to P-type doping for PMOS, and body regions to change from P-type for NMOS to N-type for PMOS. Furthermore, while the N-channel MOSFET cell structure includes a source-down enhancement transistor, illustrated in fig. 1, of a stand-alone power MOSFET device, those skilled in the art with reference to the present application will appreciate that P-channel device and/or drain-down architectures may also be utilized with appropriate polarity changes in power MOSFET embodiments, mutatis mutandis, in accordance with the teachings herein.

Those skilled in the art will recognize that the deep SCT structure 120 of the disclosed power MOSFET 100 is arranged to ohmically contact the source region and the substrate of the device, which may be doped with opposite types of species relative to each other. In addition, a metal (e.g., W) filled deep SCT is identified to reduce SCT parasitic resistance of the power FET and area normalized on-state Resistance (RSP). As noted elsewhere, the deep trench SCT structure 120 typically has a high Aspect Ratio (AR), e.g., with a Critical Dimension (CD) opening of 0.2-0.4 microns between the gate stacks 111A/113A and 111B/113B, which provides self-alignment of the source for a depth of 1.0 microns (including gate stacks) or greater. Thus, in some embodiments, the AR of deep SCT 120 may be 5:1 or more. In some other embodiments, the deep SCT 120 may have an opening of 0.4 microns and a depth (including gate stack thickness) of 1.2 microns, resulting in an AR of 3:1. those skilled in the art will recognize that various other AR combinations may be obtained depending on the semiconductor process and manufacturing flow.

The trench AR is provided with various target ranges (e.g., at least 2:1 to 5:1 in certain embodiments), in one example, the manufacturing flow herein recognizes that significant challenges result for using metal filling and etching processes in manufacturing deep SCT structures. Example challenges in fabricating deep SCT trenches with high AR values using metal fill and etch back processes may include the presence ofMetal residues or particles are formed over the plate structures (e.g., FP 117). As can be appreciated by those skilled in the art, such particles of metal residue may cause leakage and shorting between the source (as it is connected to the FP) and drain contacts. In addition, metal seams (or void regions) formed in SCT may be added to parasitic resistance, resulting in increased R _SP . Furthermore, SCT trenches with deep recess requirements may not open properly or consistently due to inherent process variations in metal fill and etch back operations across the die/wafer including the power MOSFET cell array. Still further, there is cell asymmetry in the layout of the SCT/polysilicon gates at the edges of the power MOSFET array (i.e., the outer regions of the cell array), which results in poor Ti/TiN coverage at the Si angle during the subsequent FP deposition process. These problems have been identified as not only resulting in reduced process flow robustness, but also negatively impacting throughput due to loss of parameters (e.g., due to I) _DSS Wherein I is a loss due to failure of _DSS Zero biased drain current, referred to as FET).

The process flow of an example power MOSFET that may encounter some of the problems described above may be set forth herein as an illustrative semiconductor process environment for the purpose of providing a reference process flow relative to one embodiment of the present disclosure. For example, a metal filler deposition/etchback process flow for planar gate power MOSFET fabrication may begin with a semiconductor wafer containing a P-type epitaxial layer on a p+ bulk silicon substrate. Including WSi ₂ The gate electrode, which is a silicide layer on the polysilicon, may be formed as the gate electrode of a MOSFET cell for two adjacent MOSFET devices (e.g., devices 110A and 100B described above). In one embodiment, a substrate comprising 175 angstroms may be formed over the substrateSilicon oxide (SiO) ₂ ) Is provided. A trench may be formed about 1.5 micrometers (μm) deep, the trench comprising a gate stack 0.5 μm high, the trench opening CD being about 0.3 μm, which may be at +_ of Ti>The upper lining is provided with a containing-> FP material of TiN. While such a Ti/TiN layer may extend into the deep SCT to coat its sidewalls, the TiN/Ti material itself may not be sufficient to provide a low resistance path from the source 127 to the doped layer 108 or substrate 105. The deep SCT 120 may be filled (e.g., by means of a chemical vapor deposition or CVD process) with a tungsten (W) deposition. Subsequently in an example process flow embodiment, the tungsten etch-back process may include a 3-step plasma etch in which the process gas contains SF ₆ /O ₂ /N ₂ The pressure is 30 mTorr to 35 mTorr, the plasma source power is +.>Bias power->And a chamber wall temperature of about 50 ℃ and an electrostatic chuck (ESC) temperature of about 30 ℃. In one exemplary process flow, various etching parameters may be set to a tolerance of at least 10%. Additional details regarding the metal filler deposition/etchback process flow for fabricating power MOSFETs may be found in commonly assigned co-pending U.S. patent application No. 15/171,136, filed on date 6/2 of 2016 (docket No. TI-76107), incorporated herein by reference.

To overcome at least some of these problems, novel SCT layout design innovations are set forth herein that may be implemented in various combinations, resulting in a number of embodiments. In summary, in one aspect, the length of the SCT layout feature (e.g., the horizontal dimension along the top surface of the substrate) is limited so that it does not extend beyond the polysilicon gate curve region, wherein the SCT is aligned to the complementary profile (i.e., straight line portion) of the polysilicon gate. Thus, in this aspect, the actual SCT width in a power MOSFET device or cell is determined by the gate-to-gate spacing (including the spacer width in which the gate spacers are provided) rather than the SCT layout dimensions in an arrangement where the SCT layout extends beyond the polysilicon gate curve region as required. With the disclosed method of limiting SCT layout features to linear portions of polysilicon gate features, the effects of non-uniformities in the process can be mitigated, as will be described in further detail below. In another aspect, the asymmetry at the edges of the polysilicon/SCT layout cell array is removed to ensure that all SCT trenches are between the two polysilicon gates, thereby determining that the Si corners of all SCTs (including those formed outside the array) will have the same profile, and thus uniform Ti/TiN coverage. In yet another aspect, a ground tab may be provided at the die edge to ensure that the die edge field plate is at a stable potential during device operation, as cell edge polysilicon/SCT layout asymmetry may have been eliminated in one embodiment. These various aspects will be described in greater detail below, recognizing that not all embodiments of the disclosure require each and every design innovative aspect in the practice of the disclosure.

Fig. 2 is a flow chart associated with a method 200 of manufacturing a power MOSFET integrated circuit according to one embodiment of the present disclosure. At block 202, a semiconductor substrate having a top surface and a bottom surface is provided, wherein a doped layer having an appropriate species and concentration may be formed adjacent the top surface of the semiconductor surface, and the semiconductor substrate has an upper surface (block 204). Source and drain regions of the first conductivity type may be formed in the doped layer positioned proximate to an upper surface of the doped layer, the source and drain regions being spaced apart from one another and separated by a channel region of the second conductivity type formed in the doped layer (block 206). In one embodiment, the channel region may be provided with a portion extending below the source region, wherein the drain region may comprise a portion (e.g., a Lightly Doped Drain (LDD) region) formed proximate to the channel region, of a suitable doped region. The doped drain contact region may be formed such that it is spaced apart from the channel region via the lightly doped drain region (block 208). A conductive gate having an upper surface and a sidewall surface may be formed over a gate dielectric layer formed over the channel region, wherein the conductive gate may partially overlap the source and drain regions (block 210). A conductive path for connecting the source region and the semiconductor substrate is formed via a conductor arranged in an SCT trench formed in the doped layer and extending into a substrate contact region in the semiconductor substrate. An SCT trench is provided having a length, e.g., along the longer of two dimensions in the upper surface of the doped layer (or, in one embodiment, along the top surface of the semiconductor substrate without the doped layer), that is less than the linear portion of the conductive gate formed to have a curvilinear geometry (block 212). It should be appreciated that the length of the linear portion, referred to herein as the conductive gate, is the length corresponding to the layout features of the conductive gate in top plan view, rather than the electrical "channel gate length" typically used to refer to the cross section of a MOSFET device. An insulating layer is formed over the upper surface and sidewall surfaces of the conductive gate (block 214), wherein a field plate layer having suitable metallurgical properties is formed over the lightly doped drain region and at least a portion of the first insulating layer, wherein the field plate layer is connected to the source region and SCT (block 216). A second insulating layer is formed over the field plate layer, the first insulating layer (e.g., not covered by the field plate layer), and the trench (block 218). A drain electrode electrically coupled to the drain contact region is formed to complete the fabrication of the power MOFET integrated circuit (block 220).

Fig. 3A-3C depict layout diagrams of example power MOSFET cells in top plan views in accordance with one or more embodiments of the present disclosure. Reference numeral 300A in fig. 3A relates to the interior region of an IC or die's power MOSFET cell array. A layout of three repeating cells 302-1, 302-2, 302-3, which may be referred to as internal cells, are shown, disposed consecutively in the internal region, wherein each internal cell comprises two adjacent MOSFET devices, as described in detail above. As illustrated with particular reference to cell 302-2, a common drain contact 314 (shown in detail in the cross-sectional view of fig. 4A) is provided between the pair of internal MOSFET devices, which are coupled to each other at the common drain contact 314. The polysilicon gate feature 312 is provided as a fork structure (e.g., as a closed tuning fork or racetrack shape, etc.) having an extension 311, wherein two linear portions 310A, 310B emanating from the extension 311 form a racetrack shape or closed tuning fork, the linear portions 310A/310B (termed "fingers" or "prongs" or terms of similar meaning) being the respective gates of the two MOSFET devices operable as cell 302-2. Thus, it can be seen that the example polysilicon gate feature 312 can include a curvilinear layout geometry formed of two substantially parallel linear portions 310A, 310B, the linear portions 310A, 310B having a substantially semicircular or arcuate portion 308A, 308B connected at each end, wherein the extension 311 forms a polysilicon boundary or edge 313 connected to a MOSFET IC device including a gate contact 316.

In accordance with the teachings of the present patent application, a substantially rectangular Source Contact (SCT) trench feature 304 is provided having a length 303 that is less than a linear portion (e.g., length portion or finger 310A/310B) of the polysilicon gate of the internal MOSFET device for defining a source contact conductor associated with the source region 306, wherein the SCT trench 304 is self-aligned to the gate (i.e., the SCT trench is aligned to a complementary contour or dimension of the gate). As will be appreciated by those skilled in the art, due to the repeating pattern of MOSFET cells in the array, the SCT trench 304 and associated source region 306 are operable as a source terminal for one of the MOSFET devices of the inner cell 302-2 and the successive MOSFET devices of the adjacent cell 302-3, similar to the cross-sectional arrangement shown in fig. 1 described in detail above. Fig. 4A and 4B also show similar cross-sectional views, which will be set forth below.

In one arrangement, the SCT trench 304 may be shorter than the specific distance of the end cap flexures 308A, 308B of the example polysilicon gate feature 312 (i.e., the length of the SCT trench is limited or confined in the linear portion of the gate feature) to ensure that the SCT trench features do not extend beyond each end cap flexure. In another arrangement, the SCT trench 304 may be restricted to one end, but not the other. In other arrangements, the SCT trench 304 may be pulled back from the respective end cap curved portion 308A, 308B of the example polysilicon gate feature 312 a different distance (e.g., the end of the SCT trench 304 may be less than the end cap curved portion 308A by a distance different than the distance that the opposite end of the SCT trench 304 is constrained relative to the other end cap curved portion 308B). Those skilled in the art will readily recognize that several variations of the SCT trench feature limitations with respect to the end cap curved portions 308A, 308B of the example polysilicon gate feature 312 may be obtained within the scope of the present disclosure. Regardless of variations in SCT trench formation, an FP layer 318 may be provided for overlying the polysilicon gate features, SCT trench features, and the channel and doped regions of the various MOSFET cells 302-1 through 302-3, in a manner as previously described.

Because the SCT trench feature 304 is limited to the linear portions 310A, 310B of the polysilicon gate feature 312, the actual cell region SCT width is determined by the gate-to-gate spacing (including any spacers) between two adjacent cells, e.g., cells 302-2 and 302-3, rather than the SCT trench layout dimensions, which may extend beyond the curved portions in conventional process flows. It has been noted elsewhere in this patent application that such extended SCT trench features are prone to non-uniform processing on the die, resulting in various process defects and concomitant yield degradation, especially where high AR is required for SCT structures.

Turning to fig. 3B, reference numeral 300B designates an outer edge or outer region of an array of power MOSFET cells, which may include an inner region having the above-described inner cells. Preferably, the outer region includes the last MOSFET cell 350-2 adjacent to the MOSFET cell 350-1, which is similar to the inner cell. While MOSFET cell 350-1 may have the same cell structure as internal cells 302-1 through 302-3, edge MOSFET cell 350-2 (also synonymously referred to as a termination cell, edge cell, or external cell, or terms of similar meaning) may include a fully formed MOSFET device 354 disposed adjacent to (i.e., partially formed of) non-active circuit portion 352 that does not contain SCT trench formation or source regions. In other words, the inactive circuit portion 352 includes a region without a source terminal, although a conventional polysilicon gate portion 356 may be provided as one branch of a forked polysilicon gate feature 358 that forms a polysilicon gate feature 312 similar to the internal MOSFET cells. In addition, a common drain contact 314, similar to the drain contact 314 of the internal MOSFET cell, may also be provided between the functional MOSFET device 354 and the adjacent nonfunctional portion 352 of the termination cell 350-2. Likewise, a field plate layer 318 may also be provided for the functional MOSFET device 354 and the non-functional portion 352 of the adjacent termination cell 350-2 in a similar manner, which may extend over the polysilicon boundary 313 to cover the polysilicon boundary 313.

It will be appreciated that the internal cells of the MOSFET IC device are arranged differently by providing termination cells. It may be determined that all SCT trench features are disposed between two polysilicon gate features. Thus, it can be ensured that all SCT/polysilicon corners have the same profile and the same FP coverage (e.g., ti/TiN coverage). As previously described, this arrangement may help ensure uniform processing of the entire device, thereby reducing process weaknesses that may be caused by non-self-aligned source contact sides (e.g., voids and thinning of the barrier layer).

A further variation of the exemplary external region 300C of the MOSFET IC device is shown in fig. 3C. Wherein the terminal unit 370-2 may have a characteristic geometry that is different from the geometry of the neighboring unit 370-1, the geometry of the neighboring unit 370-1 being the same as the internal unit, e.g., units 302-1 to 302-3. For example, the termination cell 370-2 is provided as a shorter cell than its neighboring cells 370, with a correspondingly shorter drain contact 380, a shorter polysilicon gate feature 382, and a shorter SCT contact feature 376 and associated source region 377. Thus, a cell such as cell 370-2 may include a MOSFET device 374 having a polysilicon gate of a second length that is less than the length of the polysilicon gate of the internal MOSFET device. Further, similar to the termination cell arrangement 350-2 of the outer region 300B shown in fig. 3B, in the embodiment shown in fig. 3C, the termination cell 370-2 may be provided with a non-functional circuit portion 372 adjacent to the functional MOSFET device 374. In yet another embodiment, the SCT contact feature 376 may be limited to the linear portion of the polysilicon gate feature 382 in a manner similar to the embodiment of fig. 3A.

In yet another aspect, a ground tab may be provided in either of the embodiments of fig. 3B and 3C to ensure that the field plate at the die/device edge is at a stable potential during device operation since the non-functional circuit portion 352 (in fig. 3B) and the non-functional circuit profile 372 (in fig. 3C) have no source trench formation and associated source regions. Illustratively, the ground tab 320 is shown coupled to the FP layer 318 in the embodiment of fig. 3B. Likewise, a similar ground tab arrangement may be provided in the embodiment of fig. 3C. It is apparent that the number, shape, size, and location of the ground tabs may be variable depending on the requirements of a particular manufacturing process.

Fig. 4A depicts a cross-sectional view 400A of the internal power MOSFET cell layout shown in fig. 3A taken along X-X'. In some embodiments, internal MOSFET cell 401A represents a cross-sectional view of cells 302-1 through 302-3 and cells adjacent to the termination cell. Fig. 4B depicts a cross-sectional view 400B taken along Y-Y' that includes an external/termination MOSFET cell 401B. It will be apparent to those skilled in the art that views 400A and 400B collectively represent a cross-sectional view of a power MOSFET IC device or die, with an interior region or portion shown by view 400A and an edge or exterior portion shown by view 400B. In both views 400A, 400B, a substrate 402 having a doped layer 404 (e.g., P-epi layer) supports a doped region 406, as previously described with reference to fig. 1. An n+ source 414 is formed in the P-type body 408 adjacent to the SCT 410, which is filled with a W plug 412. The n+ drain 416 defined in the doped region 406 is in contact with a drain plug 422. A polysilicon gate 418 overlapped by an oxide insulation (not specifically labeled) is covered by a field plate 420. The entire cell array may be covered with a protective oxide layer, such as TEOS 424, with the drain plugs exposed for electrical contact. In termination unit 401B, non-functional circuit portion 452 is exemplified by a non-active polysilicon "gate" 450, which is covered by a field plate 455, which field plate 455 extends to and above a boundary polysilicon region 456. As previously described, the non-functional circuit portion 452 lacks the source and associated SCT trench required for a functional MOSFET device.

The following table lists illustrative yield enhancements obtained by implementing the innovative SCT design aspects described above:

table-1 (if there is no innovative SCT design feature)

LOT-ID	Fault box	Yield loss
			LOT-1	Damage to	5.40％
LOT-2	Damage to	6.90％
			LOT-3	Damage to	17.04％

Watch-2 (with innovative SCT design features)

LOT-ID	Fault box	Yield loss
			LOT-A	Damage to	1.20％
LOT-B	Damage to	1.33％
			LOT-C	Damage to	1.20％

Those skilled in the art will appreciate that due to I _DSS Yield loss due to parameter failure is significantly improved in the splitting of wafers processed according to the SCT layout features set forth in this patent disclosure.

Based on the foregoing, the skilled artisan will recognize that the embodiments disclosed herein advantageously provide various SCT layout features that facilitate uniform processing of silicon trenches in which gate stack topography is present in a MOSFET cell array. In one implementation, embodiments of the present disclosure eliminate features whose trench boundaries are defined solely by the photoresist edges (e.g., SCT extensions beyond the curved portion of the curved polysilicon gate structure). Since all trenches are defined by self-aligned gate or spacer oxide formed around the gate, better process control can be achieved in the power MOSFET process flow, especially those for achieving breakdown voltage (BV _Dss ) And a specific on-resistance (R _SP ) A compromise between the above and a process flow optimized by the compromise between the above.

Although various embodiments have been illustrated and described in detail, the claims are not limited to any particular embodiment or example. None of the above detailed description should be read as implying that any particular component, element, step, act, or function is essential such that it must be included in the scope of the claims. References to elements in the singular are not intended to mean "one and only one" (unless explicitly so stated), but rather "one or more. All structural and functional equivalents to the elements of the above-described embodiments that are known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the present claims. Accordingly, those skilled in the art will recognize that the exemplary embodiments described herein can be practiced with various modifications and alterations within the spirit and scope of the appended claims.

Claims

1. An integrated circuit, IC, comprising:

a semiconductor substrate having a top surface and a bottom surface; and

at least one metal oxide semiconductor field effect transistor cell, MOSFET cell, formed in the semiconductor substrate, the MOSFET cell comprising a pair of MOSFET devices coupled to each other at a common drain contact, wherein the at least one MOSFET device comprises a source contact trench, SCT trench, extending into a substrate contact region in the semiconductor substrate adjacent the bottom surface, the SCT trench having a length along the top surface that is less than a linear portion of a polysilicon gate of the at least one MOSFET device, the SCT trench being aligned with a complementary profile of the polysilicon gate having a curvilinear layout geometry.

2. The IC of claim 1, further comprising an array of MOSFET cells, wherein external cells of the array comprise external MOSFET devices and inactive circuit portions formed in the semiconductor substrate.

3. The IC of claim 2, wherein the external MOSFET device comprises a second polysilicon gate having a second length along the top surface, and the second length is shorter than a length of the polysilicon gate of the at least one MOSFET device.

4. The IC of claim 2, the external MOSFET device comprising a second polysilicon gate having a second length along the top surface, and the second length being the same as a length of the polysilicon gate of the at least one MOSFET device.

5. The IC of claim 2, further comprising a ground tab coupled to a field plate of the external MOSFET device.

6. The IC of claim 5, wherein the field plate comprises at least one refractory metal material layer formed of a material selected from the group consisting of titanium, titanium nitride, i.e., ti/TiN, tungsten, and Ti-tungsten, i.e., ti-W.

7. The IC of claim 1, the SCT trench having a thickness of at least 2: an aspect ratio of 1.

8. The IC of claim 1, the SCT trench filled with a metal plug comprising a refractory metal or platinum group metal filler, PGM filler, for forming an electrical contact with a source terminal of the at least one MOSFET device.

9. A laterally diffused metal oxide semiconductor transistor device, LDMOS device, comprising:

a semiconductor substrate having a top surface and a bottom surface, the semiconductor substrate having a doped layer adjacent the top surface and having an upper surface;

a source region and a drain region of a first conductivity type positioned in the doped layer proximate the upper surface of the doped layer, the source region and the drain region being spaced apart from each other and separated by a channel region of a second conductivity type formed in the doped layer, the channel region having a portion extending below the source region, wherein the drain region includes a lightly doped drain region, LDD, region formed adjacent the channel region;

a doped drain contact region spaced from the channel region by the lightly doped drain region;

a conductive gate having an upper surface and a sidewall surface, the conductive gate formed over a gate dielectric layer formed over the channel region, the conductive gate at least partially overlapping the source region and the drain region;

A conductive path connecting the source region and the semiconductor substrate via a conductor disposed in a source contact trench, SCT, trench formed in the doped layer and extending into a substrate contact region in the semiconductor substrate, the SCT trench having a length along the top surface that is less than a linear portion of the conductive gate, the SCT trench aligned with a complementary profile of the conductive gate having a curvilinear geometry;

a first insulating layer over the upper surface and the sidewall surfaces of the conductive gate;

a field plate formed over the lightly doped drain region and at least a portion of the first insulating layer, wherein the field plate is connected to the source region;

a second insulating layer over the field plate layer, the first insulating layer, and the SCT trench; and

a drain electrode electrically coupled to the drain contact region.

10. The LDMOS device of claim 9, wherein the SCT trench has at least 2: an aspect ratio of 1.

11. The LDMOS device of claim 9 wherein the field plate comprises at least one layer of refractory metal material formed from a material selected from the group consisting of titanium, titanium nitride, i.e., ti/TiN, tungsten, and Ti-tungsten, i.e., ti-W.

12. The LDMOS device of claim 9, wherein the SCT trench is filled with a metal plug that forms a conductor comprising a refractory metal or platinum group metal filler, PGM filler.

13. A method of manufacturing a power metal oxide semiconductor field effect transistor integrated circuit, MOSFET, integrated circuit, the method comprising:

providing a semiconductor substrate having a top surface and a bottom surface;

forming a doped layer adjacent a top surface of the semiconductor surface and having an upper surface;

forming source and drain regions of a first conductivity type positioned in the doped layer adjacent the upper surface of the doped layer, the source and drain regions being spaced apart from one another and separated by a channel region of a second conductivity type formed in the doped layer, the channel region having a portion extending below the source region, wherein the drain region includes a lightly doped drain region, LDD, region formed adjacent the channel region;

forming a doped drain contact region, wherein the doped drain contact region is separated from the channel region by the lightly doped drain region;

forming a conductive gate having an upper surface and a sidewall surface, the conductive gate being formed over a gate dielectric layer formed over the channel region, the conductive gate at least partially overlapping the source region and the drain region;

Forming a conductive path connecting the source region and the semiconductor substrate via a conductor disposed in a source contact trench, SCT, trench formed in the doped layer and extending into a substrate contact region in the semiconductor substrate, the SCT trench having a length along the top surface that is less than a linear portion of the conductive gate, the SCT trench aligned with a complementary profile of the conductive gate having a curvilinear geometry;

forming a first insulating layer over the upper surface and the sidewall surface of the conductive gate;

forming a field plate layer over the lightly doped drain region, wherein the field plate layer is connected to the source region;

forming a second insulating layer over the field plate layer, the first insulating layer, and the SCT trench; and

a drain electrode is formed, the drain electrode electrically coupled to the drain contact region.

14. The method of claim 13, wherein the SCT trench has a thickness of at least 2: an aspect ratio of 1.

15. The method of claim 13, wherein the field plate layer comprises at least one refractory metal material layer formed from a material selected from the group consisting of titanium, titanium nitride, i.e., ti/TiN, tungsten, and Ti-tungsten, i.e., ti-W.

16. The method of claim 13, wherein the SCT trench is filled with a metal plug that forms a conductor comprising a refractory metal or platinum group metal filler, PGM filler.

17. A method of forming an electronic device, comprising:

forming a first doped region and a second doped region having a first conductivity type in an epitaxial layer over a substrate;

forming a first gate structure and a second gate structure over the first doped region;

forming a trench contact between the first gate structure and the second gate structure, the trench contact extending through the first doped region and contacting the substrate;

forming a third gate structure over the second doped region; and

forming a polysilicon boundary over the substrate, the polysilicon boundary being laterally spaced from the third gate structure and over the second doped region,

wherein the second doped region is continuous between the third gate structure and the polysilicon boundary.

18. The method of claim 17, further comprising forming a ground tab connecting the substrate to a field plate, the field plate overlying the third gate structure.

19. The method of claim 17, wherein the first gate structure and the second gate structure comprise parallel portions, and a range of the trench contact between the first gate structure and the second gate structure is limited to a range of the parallel portions.

20. The method of claim 19, wherein the parallel portion is linear.

21. The method of claim 17, further comprising forming a drain region of an opposite second conductivity type between the first doped region and the second doped region, and forming a source region of the second conductivity type between the trench contact and the first doped region.

22. The method of claim 17, wherein the first gate structure and the second gate structure are connected at respective ends to form a closed fork, and the closed fork is one of a plurality of closed forks, and the third gate structure is located at a periphery of the plurality of closed forks.

23. The method of claim 22, wherein the trench contact is one of a plurality of trench contacts corresponding to the plurality of closure tines, and each of the trench contacts is self-aligned to a corresponding pair of gate structures of a respective adjacent closure tine pair.

24. A method of forming an electronic device, comprising:

forming a plurality of closed tines over a semiconductor substrate having an epitaxial layer, each closed tine having first and second polysilicon gate structures joined at first and second ends, each closed tine including an inner portion in which the first polysilicon gate structure extends parallel to the second polysilicon gate structure, and an end portion including where the first and second polysilicon gate structures converge; and

Forming a plurality of trench contacts, each trench contact being located between a respective pair of closure tines, each of the trench contacts passing through the epitaxial layer and contacting the substrate,

wherein the trench contacts are coextensive with the inner portion.

25. The method of claim 24, further comprising:

forming a polysilicon boundary adjacent to the plurality of closed tines; and

in the epitaxial layer, a continuous doped region is formed below and between a peripheral one of the closure tines and the polysilicon boundary,

wherein the continuously doped region is free of trench contacts.

26. The method of claim 25, further comprising forming a field plate over the peripheral closure fork and the polysilicon boundary, and forming a ground tab connecting the substrate to the field plate.

27. The method of claim 25, wherein the epitaxial layer has a first conductivity type and each of the closed tines surrounds a corresponding doped region having an opposite second conductivity type.

28. The method of claim 24, wherein forming the trench contacts comprises etching corresponding trenches between adjacent ones of the closure tines using adjacent polysilicon gate structures to define widths of the corresponding trenches.

29. The method of claim 28 further comprising forming a metal layer within the trench contacting the substrate and overlying the adjacent polysilicon gate structure.

30. The method of claim 24 wherein the first polysilicon gate structure and the second polysilicon gate structure are linear within the inner portion.

31. A method of forming an electronic device, comprising:

forming a plurality of closed tines over a semiconductor substrate, the semiconductor substrate having an epitaxial layer thereon, each closed tine having a first polysilicon gate structure and a second polysilicon gate structure joined at first and second ends, each closed tine including an inner portion in which the first polysilicon gate structure extends parallel to the second polysilicon gate structure, and an end portion including where the first polysilicon gate structure converges with the second polysilicon gate structure; and

wherein the length of the trench contact is no greater than the length of the inner portion.

32. The method of claim 31 wherein the first polysilicon gate structure and the second polysilicon gate structure are curvilinear at the end portions.