CN110364508A - 装置、半导体封装以及制造半导体封装的方法 - Google Patents
装置、半导体封装以及制造半导体封装的方法 Download PDFInfo
- Publication number
- CN110364508A CN110364508A CN201811311514.3A CN201811311514A CN110364508A CN 110364508 A CN110364508 A CN 110364508A CN 201811311514 A CN201811311514 A CN 201811311514A CN 110364508 A CN110364508 A CN 110364508A
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- connection pad
- dielectric layer
- semiconductor device
- semiconductor packages
- pad pattern
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Abstract
本发明实施例涉及一种装置,其包含第一介电层、接垫图案以及第二介电层。接垫图案设置在第一介电层上且包含接垫部分和***部分。接垫部分嵌入于第一介电层中,其中接垫部分的下部表面与第一介电层的下部表面大体上共面。***部分围绕接垫部分。第二介电层设置在接垫图案上且包含延伸穿过***部分的多个延伸部分。
Description
技术领域
本发明实施例涉及一种装置、半导体封装以及制造半导体封装的方法。
背景技术
一般来说,半导体管芯可通过利用焊料凸块的一类封装来连接到在半导体管芯外部的其它装置。焊料凸块可通过以下操作形成:初始地形成与半导体管芯的导电部分相接触的凸块下金属化层,且随后将导电特征和焊料放置到凸块下金属化物上。可随后执行回焊操作以便将焊料塑形成所需形状。可随后将焊料放置成与外部装置物理接触,且可执行另一回焊操作以便使焊料与外部装置接合。以这种方式,可在半导体管芯与外部装置之间形成物理连接和电连接,所述外部装置如印刷电路板、另一半导体管芯或类似物。
用于形成半导体管芯的不同材料(如介电材料、金属化物材料、刻蚀终止层材料、阻挡层材料以及其它材料)可各自具有不同于另一材料的特有热膨胀系数。当在稍后处理、测试或使用期间加热半导体管芯时,这一类型的热膨胀系数失配导致材料中的每一种以不同方式膨胀。如此,在高温下,存在热膨胀系数失配,其导致在不同材料之间且从而在半导体管芯的不同部分之间形成应力。这些应力会导致在各种材料层之间出现分层。这一分层会在制造工艺期间或者在其既定使用期间损害半导体管芯。
发明内容
本发明是针对一种装置、半导体封装以及制造半导体封装的方法,其可以使在测试、制造以及操作过程的热循环期间所造成的接垫图案的侧壁上的应力减小或使其较不集中,从而得到更大的良率以及更可靠的装置。
根据本公开的一些实施例,装置包含第一介电层、接垫图案以及第二介电层。接垫图案设置在第一介电层上且包含接垫部分和***部分。接垫部分嵌入于第一介电层中,其中接垫部分的下部表面与第一介电层的下部表面大体上共面。***部分围绕接垫部分。第二介电层设置在接垫图案上且包含延伸穿过***部分的多个延伸部分。
根据本公开的一些实施例,半导体封装包含经包封半导体装置和重布线结构。经包封半导体装置包含由包封材料包封的半导体装置。重布线结构在经包封半导体装置上方延伸且电连接到半导体装置。重布线结构包含介电层、接垫图案以及多个介电插塞。接垫图案设置在介电层上,其中接垫图案包含嵌入于介电层中的至少一个接垫部分,且接垫图案的下部表面与远离经包封半导体装置的介电层的下部表面大体上共面。多个介电插塞延伸穿过接垫图案并围绕接垫部分。
根据本公开的一些实施例,制造半导体封装的方法包含以下步骤。在载体上形成重布线结构,其中在载体上形成重布线结构包含以下步骤:在载体上形成第一介电层,其中第一介电层包括接垫开口;在第一介电层上形成接垫图案,其中接垫图案延伸到接垫开口中且包括多个孔;以及在接垫图案上形成第二介电层,其中第二介电层填充所述孔。在重布线结构上形成经包封半导体装置。移除载体以显露接垫图案的下部表面。
附图说明
根据在结合附图阅读时的以下详细描述最好地理解本公开的方面。应注意,根据行业中的标准惯例,各种特征未按比例绘制。实际上,为了论述清晰起见,可任意增大或减小各种特征的尺寸。
图1到图10说明根据本公开的一些示例性实施例的在半导体封装结构的制造中的中间阶段的横截面视图。
图11说明根据本公开的一些示例性实施例的半导体封装的接垫图案的俯视图。
图12说明根据本公开的一些示例性实施例的半导体封装的重布线结构的一部分的横截面视图。
图13说明根据本公开的一些示例性实施例的半导体封装的横截面视图。
图14说明图13中的半导体封装的接垫图案的俯视图。
图15说明根据本公开的一些示例性实施例的半导体封装的横截面视图。
图16说明图15中的半导体封装的接垫图案的俯视图。
图17说明根据本公开的一些示例性实施例的半导体封装的横截面视图。
图18说明图17中的半导体封装的接垫图案的俯视图。
图19说明根据本公开的一些示例性实施例的半导体封装的横截面视图。
图20说明图19中的半导体封装的接垫图案的俯视图。
附图标号说明
100、100a、100b、100c、100d:半导体封装;
110、110a、110b、110c、110d:重布线结构;
112、112b、112c:第一介电层;
114、114a、114b、114c、114d:接垫图案;
116:第二介电层;
120、120':半导体装置;
121、140:衬底;
122:接触接垫;
123:电端子;
124、170:底部填充胶;
125、125':经包封半导体装置;
126、162:焊接材料;
130、130':包封材料;
142:导电接合件;
150:电连接器;
160:无源装置;
200、300:载体;
210:粘着层;
1121、1121b、1121c、1121d:接垫开口;
1141、1141a、1141b、1141c、1141d:接垫部分;
1142、1142a、1142c、1142d:***部分;
1143、1143a、1143b、1143c、1143d:孔;
1144、1144b:连接部分;
1145c、1145d:切口;
1146d:接垫凹口;
1161:介电插塞;
S1:侧壁。
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同实施例或实例。下文描述组件和布置的特定实例以简化本公开内容。当然,这些只是实例且并不意图为限制性的。举例来说,在以下描述中,第一特征在第二特征上方或上的形成可包含其中第一特征与第二特征直接接触地形成的实施例,且还可包含其中额外特征可形成于第一特征与第二特征之间使得第一特征与第二特征可以不直接接触的实施例。另外,本公开可在各种实例中重复附图标号和/或字母。此重复是出于简化和清楚的目的,且本身并不指示所论述的各种实施例和/或配置之间的关系。
此外,为易于描述,可在本文中使用如“下方”、“以下”、“下部”、“以上”、“上部”等的空间相对术语以描述如图中所说明的一个元件或特征与另一(一些)元件或特征的关系。除了图中所描绘的取向以外,空间相对术语意图涵盖装置在使用或操作中的不同取向。设备可以其它方式定向(旋转90度或处于其它取向),且本文中所使用的空间相对描述词同样可相应地进行解释。
另外,为易于描述,可在本文中使用如“第一”、“第二”、“第三”、“第四”等的术语以描述如图中所说明的类似或不同的一或多个元件或特征,且可取决于存在次序或描述的上下文而互换使用。
图1到图10说明根据本公开的一些示例性实施例的在半导体封装结构的制造中的中间阶段的横截面视图。
应注意,将在特定语境中参照一些实施例来描述本公开,即集成扇出封装结构和其制造方法。然而,还可将本公开中的概念应用于其它半导体封装或电路。根据各种实施例,提供一种可应用于半导体封装的装置(例如重布线结构)、一种半导体封装结构以及形成半导体封装的方法。根据一些实施例说明形成半导体封装的中间阶段,并论述一些实施例的变形。贯穿各种视图以及说明性实施例,相似附图标号用以表示相似元件。
在一些实施例中,形成半导体封装(例如绘示于图10中的半导体封装100)的中间阶段描述如下。参考图1,提供载体200,且粘着层210可设置在载体200上。在一些实施例中,载体200可包含例如玻璃、陶瓷或氧化硅等硅基材料或是如氧化铝等其它材料、这些材料中的任一种的组合或类似物。载体200是平面的,以便适应如半导体装置120(未绘示于图1中但在下文参照图5B和图7说明并论述)的半导体装置的贴附。可将粘着层210放置于载体200上,以便辅助上覆(overlying)结构(例如重布线结构110)的粘附。在一实施例中,粘着层210可包含紫外胶,所述紫外胶在暴露于紫外光下时降低或失去其粘着特性。然而,还可使用其它类型的粘着剂,如压敏粘着剂、辐射可固化粘着剂、光热转换释放涂层(light toheat conversion release coating;LTHC)、环氧树脂、这些粘着剂的组合或类似物。粘着层210可以在压力下可易于变形的半液体或凝胶形式放置于载体200上。
在一些实施例中,重布线结构(例如绘示于图5中的重布线结构110)可形成于载体200上或形成于粘着层210(如果存在)上。重布线结构110的形成包含以下步骤。现参考图1,可通过在载体200上或在粘着层210(如果存在)上初始地形成第一介电层112来形成重布线结构110。在一实施例中,第一介电层112可以是聚苯并恶唑(polybenzoxazole;PBO),但可替代地利用任何合适的材料,如聚酰亚胺(polyimide)或聚酰亚胺衍生物。可使用例如旋涂工艺来放置第一介电层112,但可替代地使用任何合适的方法和厚度。在一些实施例中,第一介电层112包含接垫开口1121。接垫开口1121可通过以下步骤而由第一介电层112形成:移除第一介电层112的部分以暴露下覆(underlying)的载体200或粘着层210(如果存在)的至少一部分。在一些实施例中,可使用合适的光刻掩膜和刻蚀工艺来形成接垫开口1121,但可使用任何合适的工艺。
参考图2,接垫图案114形成于第一介电层112上。在一些实施例中,接垫图案114嵌入于第一介电层112的接垫开口1121中。换句话说,接垫图案114延伸到接垫开口1121中且包含延伸穿过接垫图案114的多个孔1143。在一些实施例中,孔1143可以网(mesh)的形式(例如网孔(mesh hole))来配置。在一些实施例中,接垫图案114可以是形成于第一介电层112上的重布线电路层的图案中的一种,且重布线电路层可包含多于一种接垫图案114。在使用晶种层、图案化光刻胶以及镀覆工艺形成重布线电路层的一实施例中,可简单通过不移除需要孔1143的那些区域中的光刻胶来形成孔1143。以此方式,接垫图案114内的孔1143连同重布线电路层的其余部分一起形成,且不使用额外工艺步骤。
举例来说,可通过由合适的形成工艺(如CVD或溅镀)初始地形成晶种层(未绘示)来形成接垫图案114。在一些实施例中,晶种层可包含Cu、Ti/Cu、TiW/Cu、Ti、CrCu、Ni、Pd或类似物,且可通过例如溅镀来沉积于第一介电层112上方。可形成光刻胶(也未绘示)以覆盖金属层114的一部分,且可随后使光刻胶图案化以暴露金属层114中需要定位至少一个接垫部分1141和***部分1142的那些部分。一旦光刻胶已形成并图案化,那么便可通过如镀覆的沉积工艺在晶种层上形成如铜的导电材料。然而,当所论述的材料和方法适合于形成导电材料时,这些材料仅为示例性的。任何其它合适的材料(如AlCu或Au)以及任何其它合适的形成工艺(如CVD或PVD)都可替代地用以形成接垫图案114。一旦导电材料已形成,那么便可通过合适的移除工艺(如灰化(ashing))移除图案化光刻胶。另外,在移除图案化光刻胶之后,可使用导电材料作为掩膜通过例如合适的刻蚀工艺来移除晶种层的由图案化光刻胶所覆盖的那些部分。然而,上文所描述的工艺仅用于说明。可使用用以形成接垫图案114的任何合适的工艺。
在另一实施例中,第一介电层112上的接垫图案114可形成为固体材料,且可在接垫图案114的剩余部分的形成之后形成孔1143。在这个实施例中,可使用光刻胶掩膜和刻蚀工艺,其中在已形成接垫图案114之后,将光刻胶放置于接垫图案114上方并使之图案化,且使用一或多种刻蚀工艺以移除接垫图案114中需要孔1143的那些部分。可使用任何合适的工艺以形成孔1143。
图11说明根据本公开的一些示例性实施例的半导体封装的接垫图案的俯视图。图12说明根据本公开的一些示例性实施例的半导体封装的重布线结构的一部分的横截面视图。现在鉴于图11和图12而参考图2,在一些实施例中,孔1143围绕(例如环绕)接垫开口1121(绘示于图1中)以定义出接垫部分1141和***部分1142。接垫部分1141延伸到接垫开口1121中,且***部分1142围绕接垫部分1141。在一些实施例中,孔1143设置于***部分1142上且延伸穿过***部分1142,如图11和图12中所绘示。因此,接垫部分1141定位于接垫开口1121处,且因为接垫部分1141和第一介电层112都形成于具有平面顶部表面的载体200上或粘着层210(如果存在)上,所以接垫部分1141的下部表面与第一介电层112的下部表面大体上共面。
参考图3,第二介电层116形成于接垫图案114上,且第二介电层116填充孔1143以形成延伸穿过接垫图案114的多个介电插塞1161。即,第二介电层116包含延伸穿过***部分1142的多个延伸部分1161(即介电插塞1161)。换句话说,用第二介电层116的介电材料来填充孔1143。在一些实施例中,介电插塞1161围绕接垫开口1121并延伸穿过***部分1142。在一些实施例中,***部分1142设置于第一介电层112的上部表面上。接垫部分1141连接到***部分1142,且从第一介电层112的上部表面延伸到第一介电层112的下部表面。在一些实施例中,接垫部分1141与***部分1142为一体成形。即,接垫部分1141直接连接到***部分1142且两者间无交界(borderline)。
利用这种布置,将接垫图案114制造成具有穿过***部分1142的孔1143,以便减小可能在热循环测试、进一步处理或操作期间沿接垫图案114的侧壁(例如绘示于图12中的侧壁S1)积聚的高侧壁剥离应力以及裂痕。换句话说,通过形成具有孔1143(即介电插塞1161/延伸部分)的接垫部分114,接垫部分114能够更好地耐受涉及半导体制造、测试以及操作过程的应力。另外,孔1143可用以减弱或消除可能沿接垫部分114的侧壁出现的分层(delamination)或剥离(peeling)。对分层和剥离的这类减弱或预防将有助于防止瑕疵(defects)并增加半导体封装(例如半导体封装100)的制造工艺的总体良率。应注意,具有孔1143的接垫图案114的布置还可应用于重布线结构110的任何其它层。
在一些实施例中,孔1143的布局面积的和可以是接垫部分1141与***部分1142的布局面积的和的大体上约3%到约60%。本文中,“布局面积”的用语是指从俯视图(例如图11、图14、图16以及图20所示的俯视图)来看,被所关注结构(例如孔1143、接垫部分1141和/或***部分1142)所占据的面积。对于孔1143来说,“布局面积”的用语可以是孔1143的横截面积。在一些实施例中,因为孔1143与接垫图案114的厚度大体上相同或至少类似,所以孔1143的体积的和大体上是接垫部分1141与***部分1142的体积的和的3%到60%。在这种比例下,孔1143能够减小接垫图案114的高侧壁剥离应力,且增加接垫图案114与介电层112、介电层114之间的接触面积,这降低了接垫图案114分层的风险。在一些实施例中,孔1143(即介电插塞1161/延伸部分)中的每一个可呈正方形、矩形、圆形、椭圆形、三角形或不规则形状。可使用任何合适的形状以减小接垫图案114的侧壁剥离应力。
在一个实施例中,接垫开口1121呈圆形形状。在此类实施例中,可将孔1143布置为邻近于接垫图案114的外圆周(例如***部分1142)并以非连续圆的一部分的方式配置。另外,为了确保***部分1142保持以物理和电连接到接垫部分1141,***部分1142的连接部分1144使孔1143彼此分离。
现参考图4,在第二介电层116形成之后,可在载体200上交替地形成一或多个重布线电路层以及一或多个介电层,以使重布线结构110形成于载体200上。在一些实施例中,重布线结构110可通过以下操作来形成:连续沉积导电层;使导电层图案化以形成重布线电路;部分地覆盖重布线电路;以及用介电层填充重布线电路之间的间隙等。重布线电路(包含接垫图案114)的材料可包含金属或金属合金,包含铝、铜、钨和/或其合金。介电层(包含介电层112、介电层116)可由介电材料形成,如氧化物、氮化物、碳化物、碳氮化物、其组合和/或其多个层。然而,介电层的数目和重布线电路层的数目在本公开中不受限制。
在一些实施例中,可在载体200上形成经包封半导体装置(例如绘示于图5B中的经包封半导体装置125'或绘示于图7中的经包封半导体装置125)。在一些实施例中,经包封半导体装置125'/经包封半导体装置125可以是包含由包封材料130包封的多个半导体装置120的重构晶片。利用这种布置,可同时形成多个半导体封装以用于成批生产。出于简洁和清楚起见,在图1到图10中说明半导体封装中的一个(例如半导体封装100)的制造工艺。举例来说,在图5中说明设置于重布线结构110上的半导体装置120中的一个。经包封半导体装置125'/经包封半导体装置125的形成可描述如下。
任选地,可在载体200上设置多个通孔(未绘示),且通孔可围绕待设置半导体装置120/半导体装置120'的至少一个装置区域。在本实施例中,通孔形成于定位于载体200上的重布线结构110上且电连接到所述重布线结构,但本公开不限于此。在其它实施例中,通孔可预先形成,且随后放置于载体200上。
现参考图5,在一些实施例中,可在载体200上以及通孔(如果存在)内或通孔之间设置至少一个半导体装置120'(说明一个半导体装置120',但不限于此)。在一实施例中,如图5中所绘示,半导体封装100可包含一个半导体装置120'。在其它实施例中,半导体封装100可包含多于一个半导体装置作为一组,且通孔可围绕所述一组半导体装置。在一些实施例中,半导体装置120'电连接到重布线结构110。在一实施例中,可通过如导电凸块的多种电端子123以及多种焊接材料126来利用例如表面安装技术将半导体装置120'安装在重布线结构110上,但可替代地使用任何合适的安装方法。
在一些实施例中,半导体装置120'可以是其中包含逻辑电路的逻辑装置管芯。在一些示例性实施例中,半导体装置120'是设计成用于移动装置应用(mobileapplications)的管芯,且可包含例如电源管理集成电路(Power Management IntegratedCircuit;PMIC)管芯和收发器(Transceiver;TRX)管芯。应注意,更多或更少半导体装置120'可放置于重布线结构110上方且彼此齐平。
在一些示例性实施例中,半导体装置120'中的每一个可包含衬底121、多个有源装置(未绘示)以及多个接触接垫122。接触接垫122(如铜接垫)可形成于半导体装置120'的有源表面(例如下部表面)上且电耦合到衬底121上的接触接垫122。衬底121可包含掺杂或未掺杂的块状硅(bulk silicon)或绝缘体上硅(silicon-on-insulator;SOI)衬底的有源层。一般来说,SOI衬底包含半导体材料层,如硅、锗(germanium)、硅锗、SOI、绝缘体上硅锗(silicon germanium on insulator;SGOI)或其组合。可使用的其它衬底包含多层衬底、梯度衬底或混合取向(hybrid orientation)衬底。在一些实施例中,半导体装置120'可以是管芯,所述管芯可含有多个晶体管以及执行多种电气功能的其它有源装置和无源装置。可使用任何合适的方法在衬底121内或者在所述衬底上形成有源装置。
在一些实施例中,随后将如聚合物的材料涂覆在半导体装置120'与重布线结构110之间作为底部填充胶124。底部填充胶124典型地为聚合物,例如环氧树脂。随着向半导体装置120'和/或重布线结构110施加热,可使用毛细作用使底部填充胶124在半导体装置120'与重布线结构110之间流动。当由如聚合物环氧树脂的材料形成时,底部填充胶124随后典型地固化,从而硬化聚合物。经固化底部填充胶124围绕电端子123且用以保护电端子123和半导体装置120'与重布线结构110之间的连接,以及使半导体装置120'支撑于重布线结构110上。
现参考图5A,在一些实施例中,重布线结构110上的半导体装置120'和通孔(如果存在)由包封材料130'包封。换句话说,包封材料130'形成于重布线结构110上以包封半导体装置120'和通孔(如果存在)。在一些实施例中,包封材料130'与重布线结构110接触。包封材料130'可包含模制化合物树脂,如聚酰亚胺、PPS、PEEK、PES、耐热性晶体树脂、这些树脂的组合或类似物。可在模制装置(未绘示)中执行对半导体装置120'和通孔(如果存在)的包封。包封材料130'可放置于模制装置的模腔内,或者可通过注入端口注入到模腔中。
一旦包封材料130'放置到模腔中以使得包封材料130'包封半导体装置120'和通孔(如果存在),便可固化包封材料130'以便硬化包封材料130'以用于最优保护。另外,引发剂和/或催化剂可包含于包封材料130'内从而更好地控制固化工艺。在一些实施例中,包封材料130'的顶部表面可高于半导体装置120'的背部表面。即,包封材料130'覆盖半导体装置120'的背部表面。
现参考图5B,可对包封材料130'执行薄化工艺以显露或薄化半导体装置120'的背部表面。薄化工艺可以是例如机械研磨或CMP工艺,其中化学刻蚀剂和研磨剂用以使包封材料130'与半导体装置120'反应且研磨掉所述包封材料和所述半导体装置。所得结构绘示于图5B中。在执行薄化工艺之后,如图5B中所示,半导体装置120的背部表面与包封材料130的上部表面大体上齐平。然而,虽然上文所描述的CMP工艺作为一个说明性实施例来呈现,但其并不意图为限制性的。可替代地使用任何其它合适的移除工艺以薄化包封材料130和半导体装置120。举例来说,可替代地使用一系列化学刻蚀。可替代地使用这种工艺和任何其它合适的工艺以薄化包封材料130和半导体装置120,且所有这类工艺完全包含在实施例的范围内。
因此,将包含如图5B中所示的半导体装置120、通孔(如果存在)以及包封材料130的所得结构称作经包封半导体装置125',所述经包封半导体装置在工艺中可具有晶片形式。因此,在经包封半导体装置125'中,半导体装置120设置在重布线结构110的管芯区域上,通孔(如果存在)延伸穿过管芯区域外部的经包封半导体装置125',且包封材料130包封半导体装置120和通孔(如果存在)。换句话说,包封材料130包封其中的半导体装置120,且通孔(如果存在)延伸穿过包封材料130。
现参考图6,可替代地,在包封材料130形成于重布线结构110上之前,通过设置在半导体装置120周围的多个导电接合件142将衬底140安装在半导体装置120上方。换句话说,在一替代实施例中,在图5所示的步骤之后,依序执行图6所示的步骤而非执行图5A和图5B所示的步骤。可通过表面安装技术将衬底140安装在重布线结构110上。在一些实施例中,衬底140可以是例如掺杂或未掺杂的硅衬底,或绝缘体上硅(SOI)衬底的有源层,且可充当用作中间衬底的***件。然而,衬底140可替代地是玻璃衬底、陶瓷衬底、聚合物衬底或可提供合适的保护和/或互连功能的任何其它衬底。可替代地将这些材料和任何其它合适的材料用于衬底140。在其它实施例中,衬底140可以是半导体装置、半导体封装、散热片或其任何组合。连接到重布线结构110的导电接合件142可以是例如通过回焊形成的焊球。然而,铜柱或金柱也可通过用焊接材料进行回焊而用作导电接合件142。
现参考图7,在本发明实施例中,包封材料130包封半导体装置120和导电接合件142,并填充半导体装置120与衬底140之间的间隙。包封材料130可包含模制化合物树脂,如聚酰亚胺、PPS、PEEK、PES、耐热性晶体树脂、这些树脂的组合或类似物。在一些实施例中,包封材料130可以是底部填充胶,其典型地为聚合物,例如环氧树脂。
贯穿整个描述,将包含如图7中所示的半导体装置120、衬底140、导电接合件142以及包封材料130的所得结构称作经包封半导体装置125,所述经包封半导体装置在工艺中可具有晶片形式。因此,在经包封半导体装置125中,半导体装置120安装在重布线结构110上,衬底140通过导电接合件142来安装在半导体装置120上方。包封材料130包封半导体装置120和导电接合件142,并填充半导体装置120与衬底140之间的间隙。重布线结构110设置在经包封半导体装置125上方且电连接到半导体装置120。贯穿整个描述,将包含如图7中所示的经包封半导体装置125和重布线结构110的所得结构称作重构晶片。
在一些实施例中,在经包封半导体装置125形成于重布线结构110上之后,可将另一载体300设置在衬底140上。换句话说,载体300和载体200分别设置在重构晶片的两个相对侧上。在一些实施例中,具有载体200的重构晶片可翻转并通过使衬底140附接到载体300而设置在载体300上。承载具有载体200的重构晶片的载体300可进一步包含框架结构(未绘示),所述框架结构可以是意图在依序剥离工艺期间以及之后为结构提供支撑和稳定性的金属环。在一些实施例中,使用例如紫外胶带将具有载体200的重构晶片附接到框架结构,但可替代地使用任何其它合适的粘着剂或附接件。
现参考图8,从载体300上的重构晶片移除(例如剥离)载体200。可使用例如热工艺来剥离载体200以改变粘着层210的粘着特性。在一实施例中,使用如紫外(ultraviolet;UV)激光、二氧化碳(carbon dioxide;CO2)激光或红外(infrared;IR)激光的能量源来辐照并加热粘着层210,直到粘着层210失去其至少一些粘着特性。一旦执行,那么如图8中所示,便可将载体200与粘着层210以物理方式分离并从重构晶片的重布线结构110移除。
在移除载体200之后,显露接垫图案114的下部表面以用于后续的电连接。在一些实施例中,接垫图案114的下部表面与介电层112的下部表面大体上共面。在这种实施例中,接垫图案114的下部表面是接垫部分1141的下部表面,且介电层112的下部表面是远离经包封半导体装置125的表面。
现参考图9,如图9中所示,可随后翻转在移除载体200之后的所得结构。随后,可将至少一个电子元件(例如多个电连接器150和/或至少一个无源装置160)安装在接垫部分1141(现在图9中朝上)的下部表面上。在一些实施例中,电连接器150包含焊料凸块。在一些实施例中,电连接器150可进一步包含金属柱。无源装置160可以是集成无源装置(integrated passive device;IPD)。在本发明实施例中,重布线结构110包含多个接垫图案114。接垫图案114的接垫部分1141中的一些安装有电连接器150,且接垫图案114的接垫部分1141中的至少一个安装有无源装置160。利用这种布置,接垫部分1141可充当凸块下金属(under bump metallurgy;UBM)层,因此可省去额外的UBM层。在一些实施例中,电连接器150的形成可包含在接垫部分1141上放置焊球,且随后回焊所述焊球。在替代实施例中,电连接器150的形成可包含执行镀覆工艺从而在接垫部分1141上形成焊接材料,且随后回焊已镀覆焊接材料。举例来说,电连接器150可以是接触凸块,如微凸块或可控塌陷芯片连接(controlled collapse chip connection;C4)凸块,且可包含如锡的材料或如银或铜的其它适合材料。在其中电连接器150是锡焊料凸块的一实施例中,可通过由任何合适的方法初始地形成锡层来形成电连接器150,所述方法如蒸镀、电镀、印刷、焊料转移、植球等。一旦锡层已形成于所述结构上,便可执行回焊以便使材料形成为所需凸块形状。在一些实施例中,电连接器150可以是金属柱,且金属柱的形成可包含使用光刻胶来进行镀覆。可使用如薄膜处理和光刻处理的标准晶片制造技术来制造无源装置160,且可通过例如倒装芯片接合等来安装在另一接垫部分1141上。
贯穿整个描述,将包含如图9中所示的重布线结构110、经包封半导体装置125、衬底140(如果存在)以及电子元件150/电子元件160的所得结构称作半导体封装,所述半导体封装在工艺中可具有晶片形式。
现参考图10,从半导体封装的衬底140剥离载体300。在一实施例中,通过例如用紫外辐射辐照载体300上的紫外粘着剂来从衬底140剥离载体300,一旦紫外粘着剂已失去或降低其粘着性,那么衬底140便可以物理方式与载体300分离。
在一些实施例中,半导体封装在工艺中是晶片形式。因此,一旦剥离载体300,那么便对呈晶片形式的半导体封装执行单体化工艺以形成多个半导体封装100。在一实施例中,可通过以下操作执行单体化工艺:使用锯片(未绘示)切穿呈晶片形式的半导体封装,进而使一个部分(例如包含一个半导体装置120和一个衬底140)与另一部分分离以形成如图10中所示的半导体封装100。然而,如本领域的普通技术人员将认识到,使用锯片来使半导体封装100单体化仅仅是一个说明性实施例且并不意图为限制性的。可替代地使用用于使半导体封装100单体化的替代方法,如使用一或多种刻蚀来分离半导体封装100。这些方法和任何其它合适的方法可替代地用以使半导体封装100单体化。在本实施例中,半导体封装100中的每一个可以是集成扇出封装。
因此,通过使半导体封装100的重布线结构110的接垫图案114形成为具有如本文中所描述的孔1143,可获得更可靠的装置。具体地说,通过形成如本文中的实施例中的任一个中所描述的孔1143,可以使在测试、制造以及操作过程的热循环期间所造成的接垫图案114的侧壁上的应力减小或使其较不集中。如此,可减弱或消除可能由这些应力以其它方式所导致的分层、剥离以及开裂,从而得到更大的良率以及更可靠的装置。
图13说明根据本公开的一些示例性实施例的半导体封装的横截面视图。图14说明图13中的半导体封装的接垫图案的俯视图。应注意,绘示于图13和图14中的半导体封装100a的接垫图案114a含有与先前参考图2、图11以及图12所公开的半导体封装100的接垫图案114相同或类似的许多特征。出于清楚和简单的目的,可省去对相同或类似特征的细节描述,且相同或类似附图标号指代相同或相似组件。绘示于图13和图14中的半导体封装100a的接垫图案114a与绘示于图2、图11以及图12中的半导体封装100的接垫图案114之间的主要差异描述如下。
在一些实施例中,接垫图案114a呈矩形形状。举例来说,接垫图案114a的接垫部分1141a和***部分1142a都呈矩形形状。另外,孔1143a中的每一个可以是如图14中所示的矩形。在一些替代实施例中,孔1143a可以呈不同形状。因此,接垫开口1121是矩形开口,且矩形接垫部分1141a延伸到待与介电层112的下部表面共面的矩形接垫开口1121中。孔1143a围绕矩形接垫部分1141a且定位在***部分1142a内。在这种实施例中,无源装置160可通过焊接材料162直接安装在矩形接垫部分1141a上。应注意,在本实施例中,接垫部分1141a和***部分1142a都呈矩形形状。然而,在其它实施例中,接垫部分1141a和***部分1142a还可呈正方形、矩形、圆形、椭圆形、三角形或不规则形状。本公开不限于此。在一些实施例中,半导体封装100a可进一步包含底部填充胶170,所述底部填充胶可围绕焊接材料162并填充无源装置160与重布线结构110a之间的间隙,从而增强接合强度、重布热失配负荷且保护焊料连接件。
图15说明根据本公开的一些示例性实施例的半导体封装的横截面视图。图16说明图15中的半导体封装的接垫图案的俯视图。应注意,绘示于图15和图16中的半导体封装100b的接垫图案114b含有与先前结合图13和图14所公开的半导体封装100a的接垫图案114a相同或类似的许多特征。出于清楚和简单的目的,可省去对相同或类似特征的细节描述,且相同或类似附图标号指代相同或相似组件。绘示于图15和图16中的半导体封装100b的接垫图案114b与绘示于图13和图14中的半导体封装100a的接垫图案114a之间的主要差异描述如下。
在一些实施例中,上述的至少一个接垫部分可包含嵌入于第一介电层112b中的多个接垫部分1141b。即,接垫图案114b包含多个(矩形)接垫部分1141b,且介电层112b包含多个(矩形)接垫开口1121b。接垫部分1141b分别延伸到接垫开口1121b中,且(矩形)孔1143b(即介电插塞/延伸部分)围绕接垫部分1141b的***。在本实施例中,在两个相邻接垫部分1141b之间并未设置有分离接垫部分1141b的孔1143b。换句话说,接垫图案114b进一步包含设置在介电层112b的上部表面上的至少一个连接部分1144b。连接部分1144b使延伸到接垫部分1141b的接垫开口1121b中的任何两个相邻接垫部分1141b相连接。如此,接垫部分1141b通过连接部分1144b彼此连接并形成连续金属块。在这种实施例中,可通过焊接材料162将无源装置160安装在接垫部分1141b上。在一些实施例中,半导体封装100b可进一步包含底部填充胶170,所述底部填充胶可围绕焊接材料162并填充无源装置160与重布线结构110b之间的间隙,从而增强接合强度、重新分布热失配负荷(thermal mismatch loading)并保护焊料连接件。
图17说明根据本公开的一些示例性实施例的半导体封装的横截面视图。图18说明图17中的半导体封装的接垫图案的俯视图。应注意,绘示于图17和图18中的半导体封装100c的接垫图案114c含有与先前结合图13和图14所公开的半导体封装100a的接垫图案114a相同或类似的许多特征。出于清楚和简单的目的,可省去对相同或类似特征的细节描述,且相同或类似附图标号指代相同或相似组件。绘示于图17和图18中的半导体封装100c的接垫图案114c与绘示于图13和图14中的半导体封装100a的接垫图案114a之间的主要差异描述如下。
在一些实施例中,上述的至少一个接垫部分可包含嵌入于第一介电层112c中的多个接垫部分1141c。即,接垫图案114c包含多个(矩形)接垫部分1141c(绘示为三个但不限于此),且介电层112c包含多个(矩形)接垫开口1121c(绘示为三个但不限于此)。接垫部分1141c分别延伸到接垫开口1121c中,且(矩形)孔1143c(即介电插塞/延伸部分)围绕接垫部分1141c中的每一个。在本实施例中,孔1143c中的一些设置在两个相邻接垫部分1141c之间以使接垫部分1141c彼此分离。换句话说,***部分1142c围绕接垫部分1141c中的每一个,以使得延伸穿过***部分1142c的孔1143c相应地围绕接垫部分1141c中的每一个。另外,***部分1142c可进一步包含沿***部分1142c的边缘设置且定位在任何两个相邻接垫部分1141c之间的多个切口1145c。在这种实施例中,可通过焊接材料162将无源装置160安装在接垫部分1141c上。在一些实施例中,半导体封装100c可进一步包含底部填充胶170,所述底部填充胶可围绕焊接材料162并填充无源装置160与重布线结构110c之间的间隙,从而增强接合强度、重新分布热失配负荷且保护焊料连接件。
图19说明根据本公开的一些示例性实施例的半导体封装的横截面视图。图20说明图19中的半导体封装的接垫图案的俯视图。应注意,绘示于图19和图20中的半导体封装100d的接垫图案114d含有与先前结合图13和图14所公开的半导体封装100a的接垫图案114a相同或类似的许多特征。出于清楚和简单的目的,可省去对相同或类似特征的细节描述,且相同或类似附图标号指代相同或相似组件。绘示于图19和图20中的半导体封装100d的接垫图案114d与绘示于图13和图14中的半导体封装100a的接垫图案114a之间的主要差异描述如下。
在一些实施例中,(矩形)接垫部分1141d进一步包含延伸穿过接垫部分1141d且设置在(矩形)接垫开口1121d中的多个接垫凹口1146d(绘示为三个,但不限于此)。孔1143d围绕接垫部分1141d的***。接垫部分1141d延伸到接垫开口1121d中且由接垫凹口1146d分成多个连接部分。在本实施例中,(矩形)孔1143c围绕接垫部分1141d的***。另外,***部分1142d可进一步包含沿***部分1142d的边缘设置且对应于接垫凹口1146d设置的多个切口(cut-outs)1145d。在这种实施例中,无源装置160可安装在由接垫凹口1146d所定义出的接垫部分1141c的连接部分上。在一些实施例中,半导体封装100d可进一步包含底部填充胶170,所述底部填充胶可围绕焊接材料162并填充无源装置160与重布线结构110d之间的间隙,从而增强接合强度、重新分布热失配负荷且保护焊料连接件。
通过以如本文中所描述但不限于此的不同布置形成具有孔的接垫图案,可根据产品的实际需求来设计或修改孔的体积与接垫图案的体积的各种比例。进而,可获得更可靠的装置。具体地说,通过形成如本文中的实施例中的任一个中所描述的孔,可以使在测试、制造以及操作过程的热循环期间所造成的接垫图案的侧壁上的应力减小或使其较不集中。如此,可减弱或消除可能由这些应力以其它方式所导致的分层、剥离以及开裂,从而得到更大的良率以及更可靠的装置。另外,可在不形成任何UBM层的情况下将电子装置安装在接垫部分上。
基于以上论述,可见本公开提供各种优势。然而,应理解,并非所有优势都必须在本文中论述,其它实施例可提供不同优势,且对于所有实施例并不需要特定优势。
根据本公开的一些实施例,装置包含第一介电层、接垫图案以及第二介电层。接垫图案设置在第一介电层上且包含接垫部分和***部分。接垫部分嵌入于第一介电层中,其中接垫部分的下部表面与第一介电层的下部表面大体上共面。***部分围绕接垫部分。第二介电层设置在接垫图案上且包含延伸穿过***部分的多个延伸部分。
根据本公开的一些实施例,所述***部分设置在所述第一介电层的上部表面上,且所述至少一个接垫部分连接到所述***部分,并从所述第一介电层的所述上部表面延伸到所述下部表面。
根据本公开的一些实施例,所述至少一个接垫部分与所述***部分为一体成形。
根据本公开的一些实施例,所述多个延伸部分的布局面积的和为所述至少一个接垫部分与所述***部分的布局面积的和的3%到60%。
根据本公开的一些实施例,所述多个延伸部分围绕所述至少一个接垫部分的***。
根据本公开的一些实施例,所述至少一个接垫部分包括嵌入于所述第一介电层中的多个接垫部分,所述***部分围绕所述多个接垫部分,且所述多个延伸部分围绕所述多个接垫部分中的每一个。
根据本公开的一些实施例,所述接垫部分包括延伸穿过所述至少一个接垫部分的多个接垫凹口,且所述多个延伸部分围绕所述至少一个接垫部分的***。
根据本公开的一些实施例,半导体封装包含经包封半导体装置和重布线结构。经包封半导体装置包含由包封材料包封的半导体装置。重布线结构在经包封半导体装置上方延伸且电连接到半导体装置。重布线结构包含介电层、接垫图案以及多个介电插塞。接垫图案设置在介电层上,其中接垫图案包含嵌入于介电层中的至少一个接垫部分,且接垫图案的下部表面与远离经包封半导体装置的介电层的下部表面大体上共面。多个介电插塞延伸穿过接垫图案并围绕接垫部分。
根据本公开的一些实施例,所述接垫图案还包括围绕所述至少一个接垫部分的***部分,以及所述多个介电插塞延伸穿过所述***部分。
根据本公开的一些实施例,所述***部分设置在所述介电层的上部表面上,所述至少一个接垫部分从所述介电层的所述上部表面延伸到所述下部表面,以及所述至少一个接垫部分的下部表面与所述介电层的所述下部表面共面。
根据本公开的一些实施例,所述至少一个接垫部分包括嵌入于所述介电层中的多个接垫部分,且所述多个介电插塞围绕所述多个接垫部分的***。
根据本公开的一些实施例,所述至少一个接垫部分包括多个接垫部分,以及所述多个介电插塞围绕所述多个接垫部分中的每一个。
根据本公开的一些实施例,所述接垫部分包括延伸穿过所述至少一个接垫部分的多个接垫凹口,以及所述多个介电插塞围绕所述至少一个接垫部分的***。
根据本公开的一些实施例,所述的半导体封装还包括安装在所述接垫图案的所述下部表面上的电子元件。
根据本公开的一些实施例,所述电子元件包括电连接器凸块或无源装置。
根据本公开的一些实施例,所述经包封半导体装置还包括:多个导电接合件,设置在所述半导体装置周围;以及衬底,通过所述导电接合件设置在所述半导体装置上方,其中所述包封材料包封所述导电接合件。
根据本公开的一些实施例,制造半导体封装的方法包含以下步骤。在载体上形成重布线结构,其中在载体上形成重布线结构包含以下步骤:在载体上形成第一介电层,其中第一介电层包括接垫开口;在第一介电层上形成接垫图案,其中接垫图案延伸到接垫开口中且包括多个孔;以及在接垫图案上形成第二介电层,其中第二介电层填充所述孔。在重布线结构上形成经包封半导体装置。移除载体以显露接垫图案的下部表面。
根据本公开的一些实施例,所述的制造半导体封装的方法还包括:在所述接垫图案的所述下部表面上安装电子元件。
根据本公开的一些实施例,在所述重布线结构上形成所述经包封半导体装置包括:在所述重布线结构上设置半导体装置;以及在所述重布线结构上形成包封材料以包封所述半导体装置。
根据本公开的一些实施例,在所述重布线结构上形成所述经包封半导体装置包括:在所述包封材料形成于所述重布线结构上之前,通过多个导电接合件安装衬底于所述半导体装置上方,其中所述包封材料包封所述导电接合件。
前文概述若干实施例的特征以使得本领域的技术人员可更好地理解本公开内容的各方面。本领域的技术人员应了解,其可以易于使用本公开作为设计或修改用于进行本文中所介绍的实施例的相同目的和/或获得相同优势的其它工艺和结构的基础。本领域的技术人员还应认识到,这类等效构造并不脱离本公开的精神及范围,且其可在不脱离本公开的精神和范围的情况下在本文中做出各种改变、替代以及更改。
Claims (1)
1.一种装置,包括:
第一介电层;
接垫图案,设置在所述第一介电层上,并包括:
至少一个接垫部分,嵌入于所述第一介电层中,其中所述至少一个接垫部分的下部表面与所述第一介电层的下部表面共面;以及
***部分,围绕所述至少一个接垫部分;以及
第二介电层,设置在所述接垫图案上以及包括延伸穿过所述***部分的多个延伸部分。
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