CN110362460A - A kind of application program capacity data processing method, device and storage medium - Google Patents

A kind of application program capacity data processing method, device and storage medium Download PDF

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Publication number
CN110362460A
CN110362460A CN201910627509.1A CN201910627509A CN110362460A CN 110362460 A CN110362460 A CN 110362460A CN 201910627509 A CN201910627509 A CN 201910627509A CN 110362460 A CN110362460 A CN 110362460A
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Prior art keywords
application program
processor architecture
performance data
performance
data
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CN201910627509.1A
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CN110362460B (en
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郑升
罗章龙
黄斌
严明
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Tencent Technology Shenzhen Co Ltd
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Tencent Technology Shenzhen Co Ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3409Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
    • G06F11/3414Workload generation, e.g. scripts, playback
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/36Preventing errors by testing or debugging software
    • G06F11/3668Software testing
    • G06F11/3672Test management
    • G06F11/3684Test management for test design, e.g. generating new test cases
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/36Preventing errors by testing or debugging software
    • G06F11/3668Software testing
    • G06F11/3672Test management
    • G06F11/3692Test management for test results analysis
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

The present invention relates to field of computer technology, specifically a kind of application program capacity data processing method, device and storage medium, which comprises obtain the first performance data of hardware resource when application program is run under current processor architecture;Obtain the fisrt feature data of the current processor architecture and the second feature data of target processor architecture;The proportionality coefficient between the current processor architecture and the target processor architecture is determined according to the fisrt feature data and the second feature data;Second performance data of hardware resource when determining that the application program is run under the target processor architecture according to the first performance data and the proportionality coefficient;Second performance data is analyzed, the performance test results when application program is run under the target processor architecture are obtained.Hardware performance bottleneck of the application program under different processor framework can be accurately positioned in the present invention, and reduces test job amount, save the testing time.

Description

A kind of application program capacity data processing method, device and storage medium
Technical field
The present invention relates to field of computer technology, in particular to a kind of application program capacity data processing method, device and Storage medium.
Background technique
In process of application development, multiple performance test will do it, the purpose of performance test is to detect exploitation Code out is in current mainstream or armamentarium, if can operate normally.By being tested for the property, developer It can be found that the performance bottleneck of application program, and then carry out relevant Optimization Work.
The configuration of hardware device determines the ability of operation program to a certain extent, and distinct device applies journey to a Sequence, which is tested for the property, may obtain different test results.Height configuration equipment can permit developer develop it is more complicated Software, the continuous renewal iteration of program code also forces hardware device constantly to raise speed, the progress of hardware and software be they mutually It mutually influences, synergistic result.For mobile phone application, performance test not only can reflect application program in different configurations Performance and compatibility issue on mobile phone, while can be by analyzing the performance test data of application program come tutorial program code Exploitation, find some program code defects that can not find from performance.
In the prior art, tester needs to be tested for the property on the mobile phone of different hardware configurations, and passage capacity Detection instrument is monitored performance data, acquire single application program transmission frame number per second (Frames Per Second, FPS), the data such as central processing unit (Central Processing Unit, CPU) utilization rate, memory service condition, pass through FPS Mean value and the performances such as Caton point on confirm the performance bottleneck of application program.However, this test method, which needs to test, to be had not It is time-consuming and laborious with the mobile phone of hardware configuration;Moreover, being limited to the mobile phone quantity of different hardware configurations, tester can only be few Performance test is completed on the mobile phone of number specific configuration, may result in the omission to application program capacity bottleneck;In addition, this survey Method for testing cannot be accurately positioned by frame per second Caton point and arrive question screen.
Summary of the invention
In view of the above problems in the prior art, the purpose of the present invention is to provide a kind of application program capacity data processing sides Hardware performance bottleneck of the application program under different processor framework can be accurately positioned in method, device and storage medium, reduce and survey The workload of examination personnel saves the testing time.
To solve the above-mentioned problems, the present invention provides a kind of application program capacity data processing method, comprising:
Obtain the first performance data of hardware resource when application program is run under current processor architecture;
Obtain the fisrt feature data of the current processor architecture and the second feature data of target processor architecture;
The current processor architecture and the mesh are determined according to the fisrt feature data and the second feature data Mark the proportionality coefficient between processor architecture;
Determine the application program in the target processor frame according to the first performance data and the proportionality coefficient Second performance data of hardware resource when being run under structure;
Second performance data is analyzed, the application program is obtained and is run under the target processor architecture When the performance test results.
Another aspect of the present invention provides a kind of application program capacity data processing equipment, comprising:
First obtains module, for obtaining the primary of hardware resource when application program is run under current processor architecture It can data;
Second obtains module, for obtaining the fisrt feature data and target processor architecture of the current processor architecture Second feature data;
First determining module, for determining the current place according to the fisrt feature data and the second feature data Manage the proportionality coefficient between device framework and the target processor architecture;
Second determining module, for determining that the application program exists according to the first performance data and the proportionality coefficient Second performance data of hardware resource when being run under the target processor architecture;
Analysis module obtains the application program at the target for analyzing second performance data Manage the performance test results when running under device framework.
Another aspect of the present invention provides a kind of terminal, and the terminal includes processor and memory, deposits in the memory Contain at least one instruction, at least a Duan Chengxu, code set or instruction set, at least one instruction, an at least Duan Cheng Sequence, the code set or instruction set are loaded by the processor and are executed to realize such as above-mentioned application program capacity data processing Method.
Another aspect of the present invention provides a kind of computer readable storage medium, is stored at least one in the storage medium Instruction, at least a Duan Chengxu, code set or instruction set, at least one instruction, an at least Duan Chengxu, the code set Or instruction set is loaded by processor and is executed to realize such as above-mentioned application program capacity data processing method.
Due to above-mentioned technical proposal, the invention has the following advantages:
Application program capacity data processing method, device and storage medium of the invention, it is only necessary in a medium-performance Processor architecture under carry out the performance test of application program, the operation number of hardware resource when acquiring a application program operation According to, it can the fortune of hardware resource under other processor architectures is calculated by the proportionality coefficient of characteristic between processor architecture Hardware performance bottleneck of the application program under different processor framework can not only be accurately positioned in row data, additionally it is possible to reduce and survey The workload of examination personnel saves the testing time.
Application program capacity data processing method, device and storage medium of the invention, during performance test in real time Detect hardware resource performance data trip point, and by screenshot obtain and the trip point associated by screen video picture, The affected picture of application program capacity, the convenient original being abnormal to the performance data can fast and accurately be navigated to Because being analyzed.
Detailed description of the invention
It, below will be to required in embodiment or description of the prior art in order to illustrate more clearly of technical solution of the present invention The attached drawing used is briefly described.It should be evident that drawings in the following description are only some embodiments of the invention, it is right For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings Its attached drawing.
Fig. 1 is the flow chart of application program capacity data processing method provided by one embodiment of the present invention;
Fig. 2 is the flow chart for the application program capacity data processing method that another embodiment of the present invention provides;
Fig. 3 is the flow chart for the application program capacity data processing method that another embodiment of the present invention provides;
Fig. 4 is the flow chart for the application program capacity data processing method that another embodiment of the present invention provides;
Fig. 5 is the screen video picture that application program capacity data processing method provided by one embodiment of the present invention is related to Schematic diagram;
Fig. 6 is the block diagram of application program capacity data processing equipment provided by one embodiment of the present invention;
Fig. 7 is the block diagram for the application program capacity data processing equipment that another embodiment of the present invention provides;
Fig. 8 is the block diagram for the application program capacity data processing equipment that another embodiment of the present invention provides;
Fig. 9 is the structural schematic diagram of terminal provided by one embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on Embodiment in the present invention, those of ordinary skill in the art without making creative work it is obtained it is all its His embodiment, shall fall within the protection scope of the present invention.
It should be noted that description and claims of this specification and term " first " in above-mentioned attached drawing, " Two " etc. be to be used to distinguish similar objects, without being used to describe a particular order or precedence order.It should be understood that using in this way Data be interchangeable under appropriate circumstances, so as to the embodiment of the present invention described herein can in addition to illustrating herein or Sequence other than those of description is implemented.In addition, term " includes " and " having " and their any deformation, it is intended that cover Covering non-exclusive includes to be not necessarily limited to for example, containing the process, method of a series of steps or units, device, product or equipment Step or unit those of is clearly listed, but may include be not clearly listed or for these process, methods, product Or other step or units that equipment is intrinsic.
Figure of description 1 is please referred to, it illustrates application program capacity data processings provided by one embodiment of the present invention The process of method.Method provided by the embodiment of the present invention can be applied in terminal device, and the terminal device can be hand Holding equipment, including smart phone, tablet computer, E-book reader etc. are also possible to pocket computer on knee and desk-top Computer etc. computer equipment.The application program that the installing terminal equipment has service provider to be supplied to user.As shown in Figure 1, The application program capacity data processing method may comprise steps of:
S101: the first performance data of hardware resource when application program is run under current processor architecture are obtained.
In the embodiment of the present invention, the application program is the application program for needing to be tested for the property, the application program It can be game class application program or other applications.For example, the application program may include third person shooting trip Play (Third-Personal Shooting Game, TPS), first person shooting game (First-Person Shooting Game, FPS), the online tactics of more people race (Multiplayer Online BattleArena, MOBA) game, more people's gunbattles Any one in class survival game.The embodiment of the present invention is not defined the concrete type of application program.
In the embodiment of the present invention, the application program can be acquired by testing tool and is run under current processor architecture When hardware resource first performance data.Since in application program operational process, the performance data of hardware resource can constantly occur Variation, therefore in order to improve the accuracy of subsequent performance bottleneck detection, in a kind of possible embodiment, transported in application program During row, testing tool performance data of interval acquiring at predetermined time intervals, to obtain multiple property in scheduled duration It can data.
, may be different to the performance requirement of hardware resource under different Run-time scenarios for same application, for example, game In application program, the performance requirement of hardware resource is lower than under game starting scene, game loading scenario, game main interface scene Game carries out the performance requirement under scene to hardware resource.Therefore, in a kind of possible embodiment, testing tool is described When application program is run to object run scene, the step of obtaining hardware resource performance data is executed.
In a possible embodiment, the hardware resource may include central processing unit, the first performance data It may include the clock usage quantity per second of central processing unit core.As shown in Fig. 2, the acquisition application program is currently processed The first performance data of hardware resource may include: when running under device framework
S201: the central processing unit core when application program is run under the current processor architecture is set.
S202: the operation process of the application program and the central processing unit core are bound, so that described answer It is run in the central processing unit core with program.
S203: the clock usage quantity per second of central processing unit core when application program operation is obtained.
In the embodiment of the present invention, since the current processor architecture may possess multiple processor cores, in progressive Before capable of testing, the operation process of the application program can be tied to one of processor core in the heart, performance test Cheng Zhong, application program are only run in the processor core of binding in the heart, and testing tool also only needs to obtain the processor core of binding Clock usage quantity per second.
In one example, by taking mobile phone games performance test as an example, since Android system uses linux kernel, in linux Under provide taskset tool, taskset tool can set the CPU affinity of game process, i.e. game process can operate in On those core cpus.Wherein, the successful use of taskset tool needs taskset and setting process in the same user group Under, set game process if it is Android installation kit, can be used installation kit virtualization engine mechanism starting game and taskset.Specifically, can be used shell-command starting game test process and taskset process, the game test into Journey and taskset process are all under shell user's group, and taskset tool can set the CPU affinity of game process, i.e., Game process is tied on the core cpu of setting.
In a possible embodiment, as shown in figure 3, the central processing when acquisition application program is run The clock usage quantity per second of device core includes:
S2031: it is every to pass through preset time period, obtain what the application program in the preset time period was run in User space First time piece quantity and the second timeslice quantity run in kernel mode.
S2032: the central processing unit core is determined according to the first time piece quantity and the second timeslice quantity The clock usage quantity of the heart.
S2033: central processing unit core is calculated described pre- according to the clock usage quantity of the central processing unit core If the clock usage quantity per second in the period.
In the embodiment of the present invention, the clock usage quantity of the central processing unit core is the central processing unit core Jiffies usage amount.The Jiffies usage amount of the central processing unit core is the first time piece quantity and described second The sum of timeslice quantity, the Jiffies usage amount per second of the central processing unit core are the central processing unit core in institute State average Jiffies usage amount per second in preset time period.Wherein, the timeslice be CPU distribute to each process when Between, each process is assigned a period, referred to as its timeslice, i.e. process time for allowing to run.
In one example, testing tool can first pass through the Process identifier that ps order gets application program (Process Identification, PID), it is then every to pass through preset time period, by executing order " cat/proc/ $ (PID)/stat " obtains the operating condition of process, can obtain timeslice quantity that the application program run in User space with In the timeslice quantity of kernel mode operation, calculate the timeslice quantity in User space operation and previous time period obtains That the application program in current slot is run in User space can be obtained in the difference of the timeslice quantity of User space operation One time the piece number amount;Similarly, the timeslice quantity in kernel mode operation is calculated with previous time period acquisition in core The difference of the timeslice quantity of state operation can be obtained the application program in current slot kernel mode run second when Between piece quantity.Calculating the sum of the first time piece quantity and the second timeslice quantity can be obtained core cpu Jiffies usage amount;Calculate the Jiffies usage amount and the duration of the preset time period ratio can be obtained it is described The Jiffies usage amount per second of core cpu.
In a possible embodiment, in order to reduce calculation amount, the preset time period can be set to 1s, every warp It crosses 1s and obtains the first time piece quantity that the application program is run in User space and the second time the piece number in kernel mode operation Amount, calculating the sum of the first time piece quantity and the second timeslice quantity can be obtained the central processing unit core Jiffies usage amount per second.
In a possible embodiment, the hardware resource may include graphics processor, the first performance data It may include the clock usage quantity per second of graphics processor.When the acquisition application program is run under current processor architecture The first performance data of hardware resource may include:
Obtain the working frequency and utilization rate of the graphics processor.
The clock usage quantity per second of the graphics processor is calculated according to the working frequency and the utilization rate.
In the embodiment of the present invention, the clock usage quantity per second of the graphics processor is the per second of the graphics processor Jiffies usage amount, the Jiffies usage amount per second of the graphics processor are multiplying for the working frequency and the utilization rate Product.In one example, for high pass Adreno graphics processor (Graphics Processing Unit, GPU), test Tool can obtain the work of GPU by executing order " cat/sys/class/kgsl/kgsl-3d0/devfreq/cur_freq " Working frequency obtains GPU usage amount by executing order " cat/sys/class/kgsl/kgsl-3d0/gpubusy ", by holding Line command " cat/sys/class/kgsl/kgsl-3d0/devfreq/gpu_load " obtains GPU total amount, and calculating the GPU makes The utilization rate of the GPU can be obtained in the ratio of dosage and the GPU total amount, calculates the working frequency and the utilization rate The Jiffies usage amount per second of the GPU can be obtained in product.
S102: the fisrt feature data of the current processor architecture and the second feature number of target processor architecture are obtained According to.
In the embodiment of the present invention, the characteristic may include the weight multiplying power of the processor architecture, can basis The current processor architecture information inquires the first weight times for obtaining the current processor architecture from processor architecture table Rate inquires from processor architecture table according to the target processor architecture information and obtains the second of the target processor architecture Weight multiplying power.Wherein, the processor architecture table can be obtained from official website in advance, illustratively, as shown in table 1, institute State processor architecture code name, practical framework, weight multiplying power and the maximum that processor architecture table may include multiple corresponding storages The information such as frequency.
Wherein, the weight multiplying power and the product of the maximum frequency can be used to position corresponding processor architecture Performance, the product of the weight multiplying power and the maximum frequency is bigger, and the performance of the corresponding processor architecture is got over It is good;On the contrary, the weight multiplying power and the product of the maximum frequency are smaller, the performance of the corresponding processor architecture It is poorer.
In practical application, the terminal that can choose the processor architecture with medium-performance carries out the performance survey of application program Other are needed the processor architecture of location hardware bottleneck as target processor architecture by examination.
S103: the current processor architecture and institute are determined according to the fisrt feature data and the second feature data State the proportionality coefficient between target processor architecture.
In the embodiment of the present invention, when the fisrt feature data and target processor frame for getting the current processor architecture After the second feature data of structure, the ratio of the fisrt feature data Yu the second feature data is calculated, can be obtained described Proportionality coefficient between current processor architecture and the target processor architecture.
S104: determine that the application program is handled in the target according to the first performance data and the proportionality coefficient Second performance data of hardware resource when being run under device framework.
In the embodiment of the present invention, the product of the first performance data and the proportionality coefficient is calculated, it is available described Second performance data of application program hardware resource when being run under the target processor architecture.Wherein, described first Performance data and second performance data may include the Jiffies usage amount per second of the central processing unit core, can also To include the Jiffies usage amount per second of the graphics processor.
In a possible embodiment, described to be answered according to the first performance data and proportionality coefficient determination The second performance data of the hardware resource may include: when being run under the target processor architecture with program
Obtain the maximum value of the first performance data;
Second performance data is calculated according to the maximum value and the proportionality coefficient, second performance data is institute State the product of maximum value and the proportionality coefficient.
S105: analyzing second performance data, obtains the application program in the target processor architecture The performance test results when lower operation.
It is described that second performance data is analyzed in the embodiment of the present invention, the application program is obtained described Under target processor architecture run when the performance test results may include:
Obtain the maximum frequency of the hardware resource of the target processor architecture;
Second performance data and the maximum frequency are compared;
If second performance data is greater than the maximum frequency, determine that the application program is handled in the target There are the performance bottlenecks on hardware when running under device framework;
If second performance data is less than or equal to the maximum frequency, determine the application program in the mesh There is no the performance bottlenecks on hardware when running under mark processor architecture.
In the embodiment of the present invention, acquisition can be inquired from processor architecture table according to the target processor architecture information The maximum frequency of the hardware resource of the target processor architecture.The processor architecture table can be obtained from official website in advance Take, the processor architecture table may include the processor architecture code names of multiple corresponding storages, practical framework, weight multiplying power and The information such as maximum frequency.
Specifically, second performance data may include the Jiffies usage amount per second of the core cpu, can also be with Jiffies usage amount per second including the GPU.When the Jiffies usage amount per second of the core cpu is greater than the maximum frequency When rate, when determining that the application program is run under the target processor architecture, bottleneck has been reached on CPU hardware, i.e., it is described Application program operates in the CPU under this processor architecture, and application program capacity will receive influence;It is every when the core cpu When second Jiffies usage amount is less than or equal to the maximum frequency, determine that CPU hardware is not up to bottleneck.It is per second as the GPU When Jiffies usage amount is greater than the maximum frequency, when determining that the application program is run under the target processor architecture, Bottleneck is reached in GPU hardware;When the Jiffies usage amount per second of the GPU core is less than or equal to the maximum frequency, Determine that GPU hardware is not up to bottleneck.
In conclusion application program capacity data processing method of the invention, it is only necessary in the processing of a medium-performance The performance test that application program is carried out under device framework, the operation data of hardware resource when acquiring a application program operation The operation data of hardware resource under other processor architectures is calculated with the proportionality coefficient by characteristic between processor architecture, Hardware performance bottleneck of the application program under different processor framework can not only be accurately positioned, additionally it is possible to reduce tester's Workload saves the testing time.
Figure of description 4 is please referred to, at the application program capacity data provided it illustrates another embodiment of the present invention The process of reason method.As shown in figure 4, the method may include following steps:
S401: the first performance number of hardware resource when the application program is run under the current processor architecture is obtained According to trip point.
In the embodiment of the present invention, the application program can also be acquired by testing tool and is transported under current processor architecture The first performance data of hardware resource when row.In a kind of possible embodiment, in application program operational process or When application program is run to object run scene, testing tool performance data of interval acquiring at predetermined time intervals, and in real time Detect the trip point of the performance data.Wherein, the decision condition of the trip point and specifically define numerical value can be according to reality It is set.
In a possible embodiment, the trip point of performance data described in real-time detection may include: whenever getting When the Jiffies usage amount per second of the hardware resource, the Jiffies usage amount per second and the hardware resource are calculated most The ratio of big frequency;If the ratio is greater than default the ratio upper limit (such as can be set to 80%), it is determined that described per second Jiffies usage amount is a trip point.
In another possible embodiment, the trip point of performance data described in real-time detection can also include: whenever obtaining When getting the Jiffies usage amount per second of the hardware resource, the Jiffies usage amount per second and the hardware resource are calculated Maximum frequency ratio;If the difference of the ratio and the preceding ratio once calculated is greater than the preset threshold (preset threshold It can be set, such as be can be set to 35%) according to the actual situation, it is determined that the Jiffies usage amount per second is one Trip point.
S402: screen video picture associated by the trip point is obtained, with the original being abnormal to the performance data Because being analyzed.
In the embodiment of the present invention, when detecting the trip point of the performance data, testing tool can carry out shot operation Screen video picture associated by the trip point is obtained, performance data fluctuation or performance bottleneck can be more clearly analyzed Producing reason.As shown in figure 5, it illustrates application program capacity data processing method provided in an embodiment of the present invention The screen video picture drawing being related to may include core cpu, the CPU of application program operation in the screen video picture The information such as the Jiffies usage amount of core, the Jiffies usage amount of GPU and current time.
In practical application, since the performance data of hardware resource in application program operational process can constantly change, answer The performance data of hardware resource would also vary from when being run under different scenes with program, and therefore, process shown in Fig. 4 is usual It will not Exactly-once.
In conclusion application program capacity data processing method of the invention, real-time detection is hard during performance test The trip point of part resource performance data, and by screenshot acquisition and screen video picture associated by the trip point, it can be fast It is fast accurately to navigate to the affected picture of application program capacity, the reason of progress conveniently is abnormal to the performance data Analysis.
Figure of description 6 is please referred to, it illustrates application program capacity data processings provided by one embodiment of the present invention The block diagram of device 600.As shown in fig. 6, described device 600 may include:
First obtains module 610, for obtaining the of hardware resource when application program is run under current processor architecture One performance data.
Second obtains module 620, for obtaining the fisrt feature data and target processor of the current processor architecture The second feature data of framework.
First determining module 630, for working as according to the fisrt feature data and second feature data determination Proportionality coefficient between front processor framework and the target processor architecture.
Second determining module 640, it is described using journey for being determined according to the first performance data and the proportionality coefficient Second performance data of sequence hardware resource when being run under the target processor architecture.
Analysis module 650 obtains the application program in the target for analyzing second performance data The performance test results when being run under processor architecture.
In a possible embodiment, described device 600 can also include:
Third obtains module 660, for obtaining hardware when the application program is run under the current processor architecture The trip point of the first performance data of resource.
4th obtains module 670, for obtaining screen video picture associated by the trip point, to the performance number It is analyzed according to the reason of being abnormal.
In a possible embodiment, the hardware resource may include central processing unit, the first performance data It may include the clock usage quantity per second of central processing unit core.As shown in fig. 7, the first acquisition module 610 can wrap It includes:
Setting unit 611, for the centre when application program is run under the current processor architecture to be arranged Manage device core.
Binding unit 612, for the operation process of the application program and the central processing unit core to be bound, So that the application program is run in the central processing unit core.
First acquisition unit 613, when for obtaining the application program operation central processing unit core it is per second when Clock usage quantity.
In a possible embodiment, as shown in figure 8, the analysis module 650 may include:
Second acquisition unit 651, the maximum frequency of the hardware resource for obtaining the target processor architecture.
Comparison unit 652, for comparing second performance data and the maximum frequency.
Analytical unit 653, for determining the application program when second performance data is greater than the maximum frequency There are the performance bottlenecks on hardware when running under the target processor architecture;When second performance data is less than or equal to When the maximum frequency, determine that there is no the performances on hardware when the application program is run under the target processor architecture Bottleneck.
It should be noted that device provided by the above embodiment, when realizing its function, only with above-mentioned each functional module It divides and carries out for example, can according to need in practical application and be completed by different functional modules above-mentioned function distribution, The internal structure of equipment is divided into different functional modules, to complete all or part of the functions described above.
One embodiment of the invention additionally provides a kind of terminal, and the terminal includes processor and memory, the storage Be stored at least one instruction, at least a Duan Chengxu, code set or instruction set in device, at least one instruction, this at least one Duan Chengxu, the code set or instruction set are loaded as the processor and are executed to realize and answer as provided by above method embodiment With program feature data processing method.
In a specific embodiment, as shown in figure 9, it illustrates the structures of terminal provided in an embodiment of the present invention to show It is intended to.The terminal 900 may include one or more computer readable storage mediums memory 910, one or Processor 920, input unit 930, display unit 940, the radio frequency (Radio Frequency, RF) of more than one processing core Circuit 950, Wireless Fidelity (wireless fidelity, WiFi) components such as module 960 and power supply 970.Those skilled in the art Member it is appreciated that terminal structure not structure paired terminal 900 shown in Fig. 9 restriction, may include more or more than illustrating Few component perhaps combines certain components or different component layouts.Wherein:
The memory 910 can be used for storing software program and module, and the processor 920 is deposited by operation or execution The software program and module in the memory 910 are stored up, and calls the data being stored in memory 910, thereby executing Various function application and data processing.The memory 910 can mainly include storing program area and storage data area, wherein Storing program area can application program needed for storage program area, at least one function etc.;Storage data area can be stored according to institute That states terminal uses created data etc..In addition, memory 910 may include high-speed random access memory, can also wrap Include nonvolatile memory, such as hard disk, memory, plug-in type hard disk, intelligent memory card (Smart Media Card, SMC), peace Digital (Secure Digital, SD) card, flash card (Flash Card), at least one disk memory, flush memory device, Or other volatile solid-state parts.Correspondingly, memory 910 can also include Memory Controller, to provide processor The access of 920 pairs of memories 910.
The processor 920 is the control centre of terminal 900, utilizes each of various interfaces and the entire terminal of connection Part by running or execute the software program and/or module that are stored in memory 910, and calls and is stored in memory Data in 910 execute the various functions and processing data of terminal 900, to carry out integral monitoring to terminal 900.The place Reason device 920 can be central processing unit, can also be other general processors, digital signal processor (Digital Signal Processor, DSP), it is specific integrated circuit (Application Specific Integrated Circuit, ASIC), existing At programmable gate array (Field-Programmable GateArray, FPGA) or other programmable logic device, discrete Door or transistor logic, discrete hardware components etc..General processor can be microprocessor or the processor can also To be any conventional processor etc..
The input unit 930 can be used for receiving the number or character information of input, and generate with user setting and The related keyboard of function control, mouse, operating stick, optics or trackball signal input.Specifically, input unit 930 can wrap Include image input device 931 and other input equipments 932.Image input device 931 can be camera, be also possible to photoelectricity Scanning device.In addition to image input device 931, input unit 930 can also include other input equipments 932.Specifically, other Input equipment 932 can include but is not limited to physical keyboard, function key (such as volume control button, switch key etc.), track One of ball, mouse, operating stick etc. are a variety of.
The display unit 940 can be used for showing information input by user or the information and terminal that are supplied to user Various graphical user interface, these graphical user interface can be made of figure, text, icon, video and any combination thereof. Display unit 940 may include display panel 941, optionally, can use liquid crystal display (Liquid Crystal Display, LCD), the forms such as Organic Light Emitting Diode (Organic Light-Emitting Diode, OLED) it is aobvious to configure Show panel 941.
The RF circuit 950 can be used for receiving and sending messages or communication process in, signal sends and receivees, particularly, by base After the downlink information stood receives, one or the processing of more than one processor 920 are transferred to;In addition, the data for being related to uplink are sent out Give base station.In general, RF circuit 950 includes but is not limited to antenna, at least one amplifier, tuner, one or more oscillations Device, subscriber identity module (SIM) card, transceiver, coupler, low-noise amplifier (Low NoiseAmplifier, LNA), Duplexer etc..In addition, RF circuit 950 can also be communicated with network and other equipment by wireless communication.The wireless communication can To use any communication standard or agreement, including but not limited to global system for mobile communications (Global System ofMobile Communication, GSM), general packet radio service (General Packet Radio Service, GPRS), code it is point more Location (Code Division MultipleAccess, CDMA), wideband code division multiple access (Wideband Code Division MultipleAccess, WCDMA), long term evolution (Long Term Evolution, LTE), Email, short message service (ShortMessaging Service, SMS) etc..
WiFi belongs to short range wireless transmission technology, and terminal 900 can help user's transceiver electronics by WiFi module 960 Mail, browsing webpage and access streaming video etc., it provides wireless broadband internet access for user.Although Fig. 9 is shown WiFi module 960, but it is understood that, and it is not belonging to must be configured into for terminal 900, it can according to need completely Do not change in the range of the essence of invention and omits.
The terminal 900 further includes the power supply 970 (such as battery) powered to all parts, it is preferred that power supply can lead to Cross power-supply management system and processor 920 be logically contiguous, thus by power-supply management system realize management charging, electric discharge and The functions such as power managed.Power supply 970 can also include one or more direct current or AC power source, recharging system, electricity The random components such as source fault detection circuit, power adapter or inverter, power supply status indicator.
It should be noted that the terminal 900 can also be including bluetooth module etc., and details are not described herein although being not shown.
One embodiment of the invention additionally provides a kind of computer readable storage medium, be stored in the storage medium to Few an instruction, at least a Duan Chengxu, code set or instruction set, at least one instruction, an at least Duan Chengxu, the code Collection or instruction set can be loaded and be executed as the processor of terminal to realize the application program as provided in above method embodiment Each step of performance data processing method.
Optionally, in embodiments of the present invention, above-mentioned storage medium can include but is not limited to: USB flash disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), mobile hard disk, magnetic disk Or the various media that can store program code such as CD.
It should be understood that embodiments of the present invention sequencing is for illustration only, do not represent the advantages or disadvantages of the embodiments. And above-mentioned this specification specific embodiment is described.Other embodiments are within the scope of the appended claims.One In a little situations, the movement recorded in detail in the claims or step can be executed according to the sequence being different from embodiment and Still desired result may be implemented.In addition, process depicted in the drawing not necessarily requires the particular order shown or company Continuous sequence is just able to achieve desired result.In some embodiments, multitasking and parallel processing it is also possible or It may be advantageous.
All the embodiments in this specification are described in a progressive manner, same and similar portion between each embodiment Dividing may refer to each other, and each embodiment focuses on the differences from other embodiments.Especially for device, For terminal and server embodiment, since it is substantially similar to the method embodiment, so being described relatively simple, related place Illustrate referring to the part of embodiment of the method.
Those of ordinary skill in the art will appreciate that realizing that all or part of the steps of above-described embodiment can pass through hardware It completes, relevant hardware can also be instructed to complete by program, the program can store in a kind of computer-readable In storage medium, storage medium mentioned above can be read-only memory, disk or CD etc..
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.

Claims (10)

1. a kind of application program capacity data processing method characterized by comprising
Obtain the first performance data of hardware resource when application program is run under current processor architecture;
Obtain the fisrt feature data of the current processor architecture and the second feature data of target processor architecture;
It is determined at the current processor architecture and the target according to the fisrt feature data and the second feature data Manage the proportionality coefficient between device framework;
Determine the application program under the target processor architecture according to the first performance data and the proportionality coefficient Second performance data of hardware resource when operation;
Second performance data is analyzed, is obtained when the application program is run under the target processor architecture The performance test results.
2. the method according to claim 1, wherein the method also includes:
Obtain the jump of the first performance data of hardware resource when the application program is run under the current processor architecture Point;
Screen video picture associated by the trip point is obtained, to divide the reason of being abnormal to the performance data Analysis.
3. method according to claim 1 or 2, it is characterised in that:
The hardware resource includes central processing unit, and the first performance data include that the clock per second of central processing unit core makes Use quantity;
The first performance data of hardware resource include: when the acquisition application program is run under current processor architecture
Central processing unit core when the application program is run under the current processor architecture is set;
The operation process of the application program and the central processing unit core are bound, so that the application program is in institute It states and is run in central processing unit core;
Obtain the clock usage quantity per second of central processing unit core when application program operation.
4. according to the method described in claim 3, it is characterized in that, the centre when acquisition application program is run Reason device core clock usage quantity per second include:
It is every to pass through preset time period, obtain the first time piece that the application program is run in User space in the preset time period Quantity and the second timeslice quantity run in kernel mode;
Determine that the clock of the central processing unit core makes according to the first time piece quantity and the second timeslice quantity Use quantity;
Central processing unit core is calculated in the preset time period according to the clock usage quantity of the central processing unit core Clock usage quantity per second.
5. method according to claim 1 or 2, it is characterised in that:
The hardware resource includes graphics processor, and the first performance data include that the clock per second of graphics processor uses number Amount;
The first performance data of hardware resource include: when the acquisition application program is run under current processor architecture
Obtain the working frequency and utilization rate of the graphics processor;
The clock usage quantity per second of the graphics processor is calculated according to the working frequency and the utilization rate.
6. method according to claim 1 or 2, which is characterized in that described according to the first performance data and the ratio Example coefficient determines the second performance data of the hardware resource when application program is run under the target processor architecture Include:
Obtain the maximum value of the first performance data;
Calculate second performance data according to the maximum value and the proportionality coefficient, second performance data be it is described most The product of big value and the proportionality coefficient.
7. method according to claim 1 or 2, which is characterized in that it is described that second performance data is analyzed, it obtains The performance test results when application program being taken to run under the target processor architecture include:
Obtain the maximum frequency of the hardware resource of the target processor architecture;
Second performance data and the maximum frequency are compared;
If second performance data is greater than the maximum frequency, determine the application program in the target processor frame There are the performance bottlenecks on hardware when running under structure;
If second performance data is less than or equal to the maximum frequency, determine the application program at the target There is no the performance bottlenecks on hardware when running under reason device framework.
8. a kind of application program capacity data processing equipment characterized by comprising
First obtains module, for obtaining the first performance number of hardware resource when application program is run under current processor architecture According to;
Second obtains module, for obtain the current processor architecture fisrt feature data and target processor architecture the Two characteristics;
First determining module, for determining the current processor according to the fisrt feature data and the second feature data Proportionality coefficient between framework and the target processor architecture;
Second determining module, for determining the application program described according to the first performance data and the proportionality coefficient Second performance data of hardware resource when being run under target processor architecture;
Analysis module obtains the application program in the target processor for analyzing second performance data The performance test results when being run under framework.
9. device according to claim 8, which is characterized in that described device further include:
Third obtains module, for obtaining the of hardware resource when the application program is run under the current processor architecture The trip point of one performance data;
4th obtains module, for obtaining screen video picture associated by the trip point, the performance data to occur Abnormal reason is analyzed.
10. a kind of computer readable storage medium, which is characterized in that be stored at least one instruction, extremely in the storage medium A few Duan Chengxu, code set or instruction set, at least one instruction, an at least Duan Chengxu, the code set or instruction Collect as processor loads and executes to realize the method as described in claim 1-7 any one.
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