CN110349915B - Semiconductor device preparation method and semiconductor device prepared by same - Google Patents

Semiconductor device preparation method and semiconductor device prepared by same Download PDF

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CN110349915B
CN110349915B CN201910631672.5A CN201910631672A CN110349915B CN 110349915 B CN110349915 B CN 110349915B CN 201910631672 A CN201910631672 A CN 201910631672A CN 110349915 B CN110349915 B CN 110349915B
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layer
forming
semiconductor device
well region
metal layer
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CN110349915A (en
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项金娟
王晓磊
高建峰
李亭亭
李俊峰
赵超
王文武
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

The invention provides a semiconductor device preparation method and a prepared semiconductor device, wherein the method comprises the following steps: providing a semiconductor substrate; forming a back gate groove on a semiconductor substrate; forming an interface oxide layer on the back gate groove; forming a high-k gate dielectric layer on the interface oxide layer; forming a diffusion barrier layer on the high-k gate dielectric layer; forming a functional metal layer on the diffusion barrier layer, wherein the functional metal layer can reduce the thickness of the equivalent oxide layer; forming a work function metal layer above the functional metal layer; and forming a metal filling layer to fill the back gate groove. According to the method for reducing the EOT, provided by the invention, the metal layer with the function of reducing the Equivalent Oxide Thickness (EOT) is used in the gate stack, so that the EOT of the gate stack structure can be reduced, and a solution is provided for improving the performance of a small-size device.

Description

Semiconductor device preparation method and semiconductor device prepared by same
Technical Field
The invention relates to a semiconductor manufacturing process method, in particular to a semiconductor device manufacturing method and a manufactured semiconductor device.
Background
In CMOS devices, SiO is used to suppress short channel effect and improve device performance as the channel length is reduced2The thickness of the gate dielectric layer needs to be reduced accordingly. SiO when the integrated circuit technology is developed to sub-50 nm technology node2The thickness of the gate dielectric needs to be reduced to below 1 nm. For SiO less than 1nm2The technical requirements cannot be met due to unacceptably high leakage currents and high power consumption resulting from significant direct tunneling effects. The high-k material is introduced into the gate stack structure at the 45nm technology node.
After introducing the high-k gate dielectric, it is desirable to maintain the same equivalent SiO2The physical thickness of the gate dielectric is increased in the case of the oxide thickness (EOT), so that the tunneling current can be effectively suppressed. On the premise of ensuring that the leakage current meets the requirements of the device, the smaller the EOT is, the better the device performance can be obtained.
Therefore, developing a method for manufacturing a semiconductor device that can ensure that the leakage current meets the requirements of the device is very important in the field of semiconductor manufacturing.
Disclosure of Invention
The invention aims at least in part to provide a semiconductor device manufacturing method and a semiconductor device manufactured by the same, which can reduce EOT of a gate stack structure and provide a solution for improving the performance of a small-size device.
According to an aspect of the present invention, there is provided a semiconductor device manufacturing method, including: providing a semiconductor substrate; forming a back gate groove on the semiconductor substrate; forming an interface oxide layer on the back gate groove; forming a high-k gate dielectric layer on the interface oxide layer; forming a diffusion barrier layer on the high-k gate dielectric layer; forming a functional metal layer on the diffusion barrier layer, wherein the functional metal layer can reduce the thickness of an equivalent oxide layer; forming a work function metal layer above the functional metal layer; and forming a metal filling layer to fill the back gate groove.
Preferably, the forming of the back gate groove includes: forming a shallow groove isolation region on the semiconductor substrate; forming a P well region and an N well region on the semiconductor substrate, wherein the P well region and the N well region are isolated by the shallow trench isolation region; forming a dummy gate and a source drain region on the P well region and the N well region on the substrate; filling an interlayer dielectric layer above the dummy gate; grinding the interlayer dielectric layer by a CMP (chemical mechanical polishing) process to expose the dummy gate; and removing the dummy gate by a wet etching process to form a back gate groove.
Preferably, the diffusion barrier layer is TiN or TaN or a combination thereof.
Preferably, the functional metal layer is a metal carbide containing Al.
Preferably, the metal carbide containing Al is any one or combination of TiAlC, TaAlC or MoAlC.
Preferably, the Al-containing metal carbide is prepared using a monoatomic layer deposition method in which the Al atomic content is not more than 40%.
Preferably, in the Al-containing metal carbide, Al atoms are present in an Al — Al bond.
Preferably, the thickness of the functional metal layer is 0.5 nm-5 nm.
Preferably, the work function metal layer contains HfN, TiN, TaN, MoN, TiAlN, TaAlN, MoAlN and HfCNx、TiAl、TaAl、HfC、TiC、TaC、TiAlC、TaAlC、Ru、Re、Pt、RuO2、TaRuxAnd HfRu, or a combination thereof.
Preferably, the material of the metal filling layer is a metal material.
According to another aspect of the present invention, there is provided a semiconductor device including: a semiconductor substrate; the shallow trench isolation region isolates the P well region from the N well region; source and drain regions in the P-well region and the N-well region; filling interlayer dielectric layers above the shallow groove isolation region and the source drain region; and an interface oxide layer, a high-k gate dielectric layer, a diffusion barrier layer, a functional metal layer, a work function metal layer and a metal filling layer are sequentially arranged between the interlayer dielectric layers.
Preferably, the metal carbide containing Al is any one or combination of TiAlC, TaAlC or MoAlC.
Preferably, the Al-containing metal carbide is prepared using a monoatomic layer deposition method in which the Al atomic content is not more than 40%.
Preferably, in the Al-containing metal carbide, Al atoms are present in an Al — Al bond.
Preferably, the thickness of the functional metal layer is 0.5 nm-5 nm.
According to the method for reducing the EOT, provided by the invention, in the gate stack, the metal carbide metal containing Al is used as a functional metal layer for reducing the equivalent oxide layer thickness (EOT) by using the monoatomic layer deposition (ALD), so that the EOT of the gate stack structure can be reduced, and a solution is provided for improving the performance of a small-size device.
Drawings
The various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 shows a flow chart of a method of manufacturing a semiconductor device according to the present invention.
Fig. 2 to fig. 8 are schematic cross-sectional structures of a semiconductor device manufacturing method according to an embodiment of the present invention.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are in direct contact, as well as embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact.
Furthermore, spatial relationship terms, such as "below", "lower", "above", "upper", and the like, may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly as such. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
Referring first to fig. 1, fig. 1 shows a flow chart of a method of manufacturing a semiconductor device according to the present invention.
In step S11, the semiconductor substrate 10 is provided. In the present embodiment, the semiconductor substrate 10 includes a silicon substrate, and the semiconductor substrate 10 may further include other elementary semiconductors or compound semiconductors such as Si, Ge, GeSi, GaAs, InP, SiC, diamond, or the like. The semiconductor substrate 10 may include various doping configurations according to design requirements known in the art (e.g., p-type substrate or n-type substrate). Further, the semiconductor substrate 10 may optionally include an epitaxial layer, may be stress altered to enhance performance, and may include a silicon-on-insulator (SOI) structure.
In step S12, a back gate recess is formed on the semiconductor substrate 10.
One specific method of forming the back gate recess can be referred to as follows, and it should be noted that the present embodiment illustrates a CMOS employing a planar structure, but the present invention can be advantageously applied to a CMOS including a FinFET structure.
As shown in fig. 2, shallow trench isolation regions 13 are formed on a semiconductor substrate 10; a P-well region 11 and an N-well region 12 are formed on a semiconductor substrate 10, and a shallow trench isolation region 13 isolates the P-well region 11 from the N-well region 12.
As shown in fig. 3, a P-well region 11 and an N-well region 12 on a substrate 10 form a dummy gate 14 and form source-drain regions 15.
As shown in fig. 4, an interlayer dielectric layer 16 is filled over the dummy gate 14.
As shown in fig. 5, the interlayer dielectric layer 16 is planarized by a CMP process to expose the dummy gate 14.
As shown in fig. 6, the dummy gate 14 is removed by a wet etching process to form a back gate recess 17.
In the CMOS device with the FinFET structure, the back gate groove is located between adjacent semiconductor fins, and the specific phase processing is similar to the back gate groove forming process of the CMOS device with a planar structure, and is not described here again.
In step S13, as shown in fig. 7 and 8, an interfacial oxide layer 18 is formed on the back gate groove 17. The interface oxide layer can be formed in a thermal growth mode, and can also be grown in a wet method mode. In the embodiment of the invention, the interface oxide layer is SiO2And may be an oxynitride layer having a thickness of about 0.3-1 nm.
In step S14, as shown in fig. 7 and 8, a high-k gate dielectric layer 19 is formed on the interfacial oxide layer 18. The high-k gate dielectric layer can be formed by using ALD (atomic layer deposition) technology, for example, the high-k gate dielectric material is HfO2、ZrO2、HfSiOx、HfZrOx、HfLaOx、HfLaONx、LaAlOx、La2O3Of about 1-3nm thick, or a combination thereof.
In step S15, a diffusion barrier layer 20 is formed on the high-k gate dielectric layer 19, as shown in fig. 7 and 8. The diffusion barrier layer may be formed by Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD) or ALD deposition and has a thickness of 0.3-2 nm. The diffusion barrier layer may comprise any one or combination of TiN, TaN, and the like.
In step S16, as shown in fig. 7 and 8, a functional metal layer 21 is formed on the diffusion barrier layer 20, wherein the functional metal layer is capable of reducing the equivalent oxide thickness. The metal layer is a metal carbide containing Al, such as any one of TiAlC, TaAlC, MoAlC and the like. The Al-containing metal carbide may be prepared using a monoatomic layer deposition (ALD) method, and has a thickness of 0.5nm to 5nm and an Al atomic content of not more than 40%. Wherein, in the Al-containing metal carbide, Al atoms exist in an Al-Al bond. Particularly, the thickness value of the equivalent oxide layer can be adjusted by adjusting the growth temperature of the Al-containing metal carbide, adjusting the reduction effect of the equivalent oxide layer thickness and further adjusting the thickness value of the equivalent oxide layer according to the reduction effect of the equivalent oxide layer.
In step S17, as shown in fig. 7 and 8, a work function metal layer 22 is formed over the functional metal layer 21. The work function metal layer22 may include metals, metal compounds, and metal silicides, and combinations thereof. In the embodiment of the invention, the thickness of the work function metal layer is about 1-6 nm, and the material selected for the work function metal layer can comprise HfN, TiN, TaN, MoN, TiAlN, TaAlN, MoAlN and HfCNx、TiAl、TaAl、HfC、TiC、TaC、TiAlC、TaAlC、Ru、Re、Pt、RuO2、TaRuxAnd HfRu, or a combination of a plurality of the same.
In step S18, as shown in fig. 7 and 8, a metal filling layer 23 is formed to fill the back gate groove. The metal filling layer 23 may be grown by PVD, CVD or ALD, and the material of the metal filling layer 23 is a metal material, preferably a low-resistance metal material, such as W, Al.
According to the method for reducing the EOT, the thickness of an equivalent oxide layer can be reduced to be 0.7nm or below, and meanwhile, the filling capacity in a small-size device can be effectively improved, so that the performance of the device is improved. Meanwhile, the EOT of the gate stack structure can be reduced, and a solution is provided for improving the performance of a small-size device.
Further, on the basis of the above embodiments, the present invention still further provides a semiconductor device.
As shown in fig. 7, the semiconductor device includes: the substrate 10, in this embodiment, the semiconductor substrate 10 includes a silicon substrate, and the semiconductor substrate 10 may further include other elementary semiconductors or compound semiconductors, such as Si, Ge, GeSi, GaAs, InP, SiC, diamond, or the like. The semiconductor substrate 10 may include various doping configurations according to design requirements known in the art (e.g., p-type substrate or n-type substrate). Further, the semiconductor substrate 10 may optionally include an epitaxial layer, may be stress altered to enhance performance, and may include a silicon-on-insulator (SOI) structure.
As shown in fig. 7, the semiconductor device further includes: shallow trench isolation region 13, P-well region 11 and N-well region 12 in semiconductor substrate 10, shallow trench isolation region 13 separates P-well region 11 and N-well region 12. P-well region 11 and source-drain regions 15 in N-well region 12. And an interlayer dielectric layer 16 filled above the shallow trench isolation region 13 and the source drain region 15. And as shown in fig. 7 and 8, a back gate groove 17 is formed between the interlayer dielectric layers 16, and an interface oxide layer 18, a high-k gate dielectric layer 19, a diffusion barrier layer 20, a functional metal layer 21, a work function metal layer 22, and a metal filling layer 23 are sequentially arranged in the back gate groove 17.
The functional metal layer 21 is a metal carbide containing Al, such as any one of TiAlC, TaAlC, and MoAlC, or a combination thereof. The Al-containing metal carbide may be prepared using a monoatomic layer deposition (ALD) method, and has a thickness of 0.5nm to 5nm and an Al atomic content of not more than 40%. Wherein, in the Al-containing metal carbide, Al atoms exist in an Al-Al bond. Particularly, the thickness value of the equivalent oxide layer can be adjusted by adjusting the growth temperature of the Al-containing metal carbide, adjusting the reduction effect of the equivalent oxide layer thickness and further adjusting the thickness value of the equivalent oxide layer according to the reduction effect of the equivalent oxide layer.
According to the semiconductor device provided by the invention, the metal carbide metal containing Al is used as the functional metal layer for reducing the Equivalent Oxide Thickness (EOT) in the gate stack layer by using the monoatomic layer deposition (ALD), so that the EOT of the gate stack layer structure can be reduced, and a solution is provided for improving the performance of a small-size device.
The components of several embodiments are discussed above so that those skilled in the art may better understand the various aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (11)

1. A semiconductor device fabrication method, the method comprising: providing a semiconductor substrate; forming a back gate groove on the semiconductor substrate; forming an interface oxide layer on the back gate groove; forming a high-k gate dielectric layer on the interface oxide layer; forming a diffusion barrier layer on the high-k gate dielectric layer; forming a functional metal layer on the diffusion barrier layer, wherein the functional metal layer is a metal carbide containing aluminum, and the aluminum atoms exist in an Al-Al bond mode, so that the thickness of an equivalent oxide layer can be reduced; forming a work function metal layer above the functional metal layer; and forming a metal filling layer to fill the back gate groove.
2. The method of manufacturing a semiconductor device according to claim 1, wherein forming the back gate recess comprises: forming a shallow groove isolation region on the semiconductor substrate; forming a P well region and an N well region on the semiconductor substrate, wherein the P well region and the N well region are isolated by the shallow trench isolation region; forming a dummy gate and a source drain region on the P well region and the N well region on the substrate; filling an interlayer dielectric layer above the dummy gate; grinding the interlayer dielectric layer by a CMP (chemical mechanical polishing) process to expose the dummy gate; and removing the dummy gate by a wet etching process to form a back gate groove.
3. The method of manufacturing a semiconductor device according to claim 1, wherein the diffusion barrier layer is TiN or TaN or a combination thereof.
4. The method for manufacturing a semiconductor device according to claim 1, wherein the metal carbide containing Al is any one or a combination of TiAlC, TaAlC or MoAlC.
5. A semiconductor device production method according to any one of claim 1 and claim 2, wherein the Al-containing metal carbide is produced using a monoatomic layer deposition method in which the Al atomic content is not more than 40%.
6. The method for manufacturing a semiconductor device according to any one of claims 1 and 2, wherein the thickness of the functional metal layer is 0.5nm to 5 nm.
7. The method for manufacturing a semiconductor device according to claim 1, wherein the work function metal layer contains HfN, TiN, TaN, MoN, TiAlN, TaAlN, MoAlN, HfCNx、TiAl、TaAl、HfC、TiC、TaC、TiAlC、TaAlC、Ru、Re、Pt、RuO2、TaRuxAnd HfRu, or a combination thereof.
8. A semiconductor device, comprising: a semiconductor substrate; the shallow trench isolation region isolates the P well region from the N well region; source and drain regions in the P-well region and the N-well region; an interlayer dielectric layer above the shallow trench isolation region and the source drain region; the interface oxide layer, the high-k gate dielectric layer, the diffusion barrier layer, the functional metal layer, the work function metal layer and the metal filling layer are sequentially arranged between the interlayer dielectric layers, wherein the functional metal layer is a metal carbide containing aluminum, and the existence mode of aluminum atoms is an Al-Al bond.
9. The semiconductor device according to claim 8, wherein the Al-containing metal carbide is any one of TiAlC, TaAlC or MoAlC, or a combination thereof.
10. The semiconductor device according to claim 8, wherein the Al-containing metal carbide is produced using a monoatomic layer deposition method in which an Al atomic content is not more than 40%.
11. The semiconductor device according to claim 8, wherein the thickness of the functional metal layer is 0.5nm to 5 nm.
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