CN1103496C

CN1103496C - Method of forming shielding wire adjacement to signal wire

Info

Publication number: CN1103496C
Application number: CN 98121451
Authority: CN
Inventors: 季明华
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 1998-09-14
Filing date: 1998-10-30
Publication date: 2003-03-19
Anticipated expiration: 2018-10-30
Also published as: CN1248064A; TW379432B

Abstract

The present invention relates to a manufacturing method of forming a shielding wire which is adjacent to a signal wire in an integrated circuit, which comprises the following steps: a silicon oxide layer is formed on the signal wire; the silicon oxide layer is back-etched to form a clearance wall on the side wall of the signal wire; a metal layer is deposited on the signal wire and the silicon oxide layer; the top end part of the metal layer is removed to make the upper surface of the residual metal layer lower than that of the signal wire; the residual metal layer is formed a shielding wire; the clearance wall is removed.

Description

Formation is adjacent to the method for the shielding conductor of holding wire

Technical field

The present invention relates to the shielded signal wire in the integrated circuit,, particularly relate to a kind of method that forms the shielding conductor of ground connection on the holding wire next door to prevent noise jamming.

Background technology

The ultra-large type integrated circuit (Very Large Scale Integration, VLSI) in, metal interconnecting (metal interconnect) structure is a crucial part.Metal interconnecting structure generally includes plain conductor and interlayer hole (via).The purposes of interlayer hole is for connecting double layer of metal lead up and down.Complicated integrated circuit can comprise the structure of multiple layer metal intraconnections.The plain conductor of VLSI is commonly used to transmitting digital signals, analog signal or grid bias power supply (bias power).

The metal wire that carries signal is referred to as holding wire.Because at VLSI and very big type integrated circuit (Ultra Large Scale Integration, ULSI) in, space between the holding wire is very little, so the capacitive coupling between the adjacent wires (capacitive coupling) can produce some noises or interfere with each other (cross-talk) signal.When the size of integrated circuit descends always, critical size (criticaldimension) also and then diminishes, and then the problem of capacitive coupling between the adjacent signals line and noise is also just serious more.

A kind of shielded signal wire that is used for is to provide shielding conductor in the both sides of holding wire with the existing method that prevents noise jamming.Shielding conductor is normally finished when the deposition etch metal interconnecting simultaneously with holding wire.Yet shielding conductor is and direct voltage (V _SSOr V _CC) join, so compare with faint AC signal, shielding conductor is " ground connection ", promptly exchanges ground connection (AC grounded).Therefore, any semiconductor element that inputs or outputs usefulness of shielding conductor discord connects.In this prior art, every signal line needs two shielding conductors with the holding wire insulation could realize the purpose of noise insulation, therefore needs very big area.Required insulating space size between holding wire and the shielding conductor mainly is the resolution that is subject to photoetching process.For example, in CMOS (CMOS) technology of 0.25 μ m, the about 0.3 μ m of the spacing distance between holding wire and the shielding conductor.And because the capacitive coupling between the shielding conductor of holding wire and ground connection, so electric capacity between the two also reduce and increase along with size of component, especially in requiring circuit at a high speed, dislike especially and ground wire between capacitive coupling.

Fig. 1 illustrates the schematic perspective view of existing screen method.The semiconductor-based end 101 can be following combination: silicon base, transistor unit, logic element, capacity cell or any semiconductor element.These elements need to be electrically connected mutually with other semiconductor elements or output/input circuit.In the prior art, dielectric layer 103 is the semiconductor circuits that are used for isolating different layers.Dielectric layer 103 be generally interlayer dielectric layer (interlayer dielectric, ILD) or metal intermetallic dielectric layer (intermetal dielectric, IMD).Dielectric layer 103 can be by boron-phosphorosilicate glass (BPSG), constituted by individual layer materials such as silica that source of the gas deposited, phosphorosilicate glass (PSG), silicon dioxide, spin-on glasses (SOG), silicon nitride, aluminium oxide, tantalum oxide with tetraethyl orthosilicate (TEOS), or the combination in any of these material layers.For purposes of the invention, dielectric layer 103 is commonly referred to as silica.

Be the structure of metal interconnecting on dielectric layer 103, material is conductive metal, for example aluminium, tungsten, polysilicon or copper.Internal connection-wire structure comprises networking and the interlayer hole that plain conductor is formed, and these intraconnections are via being connected semiconductor element with contact hole in its lower floor.

In the prior art, metal interconnecting comprises holding wire 105 and shielding conductor 107 at least.Shielding conductor 107 is the mode ground connection via alternating current, and holding wire 105 then carries the ditch power on signal between the element.As previously discussed, shielding conductor 107 and holding wire 105 are adjacent one another are.Usually the space between shielding conductor 107 and the holding wire 105 can be more slightly bigger than the critical size of photoetching.And after the structure fabrication of metal interconnecting is finished, above shielding conductor 107 and holding wire 105, also has the silicon oxide layer of one deck insulation usefulness.Therefore the space between shielding conductor 107 and the holding wire 105 is that oxidized silicon fills up.

Summary of the invention

Therefore the object of the present invention is to provide a kind of manufacture method of shielding conductor, make the shielding conductor can be more close, and have lower capacitive coupling with holding wire.

For achieving the above object, the present invention proposes the manufacture method of the shielding conductor of close holding wire in a kind of semiconductor element.This method is included in deposition one deck silicon oxide layer on the holding wire, eat-backs silicon oxide layer, at the sidewall formation silica clearance wall of holding wire.Above holding wire and clearance wall, deposit layer of metal, remove the head portion of metal level, make remaining layer on surface of metal be lower than the upper surface of holding wire.Remaining metal level forms shielding conductor, removes the silica clearance wall again.

The present invention also provides a kind of method that forms adjacent to a shielding conductor of a holding wire in integrated circuit, this method comprises: form a clearance wall on the sidewall of this holding wire; Deposition layer of metal layer above this holding wire; Remove the head portion of this metal level, make the upper surface of remaining this metal level be lower than the upper surface of this holding wire, remaining this metal level forms a shielding conductor; And remove this clearance wall.

Brief description of drawings

For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. elaborates.In the accompanying drawing:

Fig. 1 illustrates the technology of the shielded signal wire in existing a kind of integrated circuit;

Fig. 2～7 illustrate a preferred embodiment of the present invention, the manufacturing process profile of the shielding conductor in a kind of semiconductor integrated circuit.

Detailed description of the preferred embodiment

Please refer to Fig. 2～7, it illustrates a preferred embodiment of the present invention, the manufacturing process profile of the shielding conductor in a kind of semiconductor integrated circuit.Please refer to Fig. 2, on substrate 201, form the silicon oxide layer 203 of insulation.Substrate 201 can comprise semiconductor element miscellaneous, and element needs mutual electrical connection each other, and similar with the substrate 101 of above-mentioned Fig. 1 in fact.Same, silicon oxide layer 203 is used for completely cutting off different plain conductors for what insulate in integrated circuit.

Above silicon oxide layer 203, form the layer of metal layer, utilize existing lithography corrosion process to form holding wire 205 again.For example, the manufacture method of holding wire 205 can deposit layer of aluminum, tungsten or copper earlier above silicon oxide layer 203, at the photoresist layer that forms one deck patterning above the metal level again (not shown on the figure), be that mask carries out etched step with this photoresist layer.As the known situation of prior art, this layer metal level also can fill up the interlayer hole opening in the silicon oxide layer 203 (not shown on the figure), the semiconductor element electricity that allows holding wire 205 and be positioned at its below links to each other.And holding wire 205 materials own comprise aluminium, tungsten, polysilicon or copper.

Then, please refer to Fig. 3, utilize plasma reinforced chemical vapour deposition method (PECVD), at the thick boron-phosphorosilicate glass 207 of about 2000 dusts of 400 deposit one decks.(rapidthermal process RTP) comes densification boron-phosphorosilicate glass 207 can to re-use quick thermal treatment process.

Then, please refer to Fig. 4, carry out dry etching steps, the structure of formation clearance wall 209 on the sidewall of every signal line 205 207.(reactiveion etching RIE) carries out for example available reactive ion-etching of dry etching steps.But, just know the personnel of this technology, not all holding wire 205 all needs shielding.In such cases, can utilize the mask protection not need the holding wire 205 that shields, just can on the sidewall of these holding wires 205, not form boron-phosphorosilicate glass clearance wall 209.Therefore, Fig. 4 shows the zone that needs shielded signal wire 205 in the integrated circuit.

Please refer to Fig. 5, depositing metal layers 211 above total.It is thick that metal level 211 is preferably about 5000 dusts, and still the holding wire 205 that will and need shield at least is of uniform thickness.In addition, the material of metal level 211 is preferably tungsten, but also can use other conductive material.Formation method as for metal level 211, because chemical vapour deposition technique is good for the ditch ability of filling out of slight void than other method, as physical vaporous deposition, utilize chemical vapour deposition technique to carry out conformal (conformal) deposition so be preferably, and tungsten is for wherein filling out the very high a kind of material of ditch ability.

Then, please refer to Fig. 6, metal level 211 is carried out chemical mechanical milling method (chemicalmechanical polishing, CMP), and had a few etching a little, and stop again to the top of clearance wall 209, make the surface of metal level 211 be lower than the upper surface of holding wire 205.If holding wire 205 and metal level 211 are made up of different conductive material, the grinding rate of the two some difference a little then.Can guarantee that like this clearance wall 209 comes out, in order to it is removed fully when follow-up desire is removed clearance wall 209.So this grinding steps is most important is the upper end that exposes clearance wall 209.In the middle of subsequent step, will understand that, clearance wall 209 could be removed fully only so.

After grinding steps was finished, the shielding conductor 211 of formation and holding wire 205 were mutual insulating each other.And shielding conductor 211 and holding wire 205 are separated with clearance wall 209 each other.

Please refer to Fig. 7, utilize the engraving method that boron-phosphorosilicate glass is had high selectivity, remove clearance wall 209.The engraving method of this high selectivity is preferably the clearance wall 209 that utilizes low pressure HF gas to come the etching boron-phosphorosilicate glass to constitute, the method compares up to about about 1000 the selection of boron-phosphorosilicate glass clearance wall 209 and silicon oxide layer 203, please refer to " Gas Phase Selective Etching of NativeOxide " (Mike et al.IEEE Electron Device, 37 (1), p.107-115,1990).So boron-phosphorosilicate glass clearance wall 209 can remove it under the situation that silicon oxide layer 203, holding wire 205 and shielding conductor 211 are not destroyed fully.The details of this low pressure HF etching technique has discussion in " A New CylindricalCapacitor Using Hemispherical Grain Si (HSG-Si) for 256 MbDRAMs " (Watanabe et al.IEDM 92-259,1992).

211 mode ground connection of shielding conductor via the general alternating current of prior art, and be the also low air of ratio silicon oxide dielectric coefficient between holding wire 205 and the shielding conductor 211, the capacitive coupling degree of holding wire 205 and shielding conductor 211 is reduced significantly.

At last, as situation, above holding wire 205 and shielding conductor 211 deposition one layer insulating, for example silicon nitride or silica.Form the method for this layer insulating, must select to fill out the relatively poor method of ditch ability, in order to avoid the air irrigation canals and ditches 213 between holding wire 205 and the shielding conductor 211 are filled up.

By the invention described above preferred embodiment as can be known, use the present invention and have following advantage.The first, shielding conductor 211 does not need the photoetching technique with any advanced person for being aligned to holding wire 205 automatically.The second, the interval between holding wire 205 and the shielding conductor 211 is very little.Three, air irrigation canals and ditches 213 provide low-down electric capacity, make that the capacitive coupling between holding wire 205 and the shielding conductor 211 is minimized.

The material of holding wire can among the CMOS the normal electric conducting material that uses, for example polysilicon, metal silicide, tungsten, aluminium, copper or the like.The material of shielding conductor is general, and also the material with holding wire is identical, just generally can be subject to the formed material of easy use chemical vapour deposition technique, as polysilicon, tungsten, copper etc.Last method of the present invention can be applicable on the technology of multi-metal intra-connection, provides more screen effect to metal interconnecting.

Though the present invention discloses as above in conjunction with a preferred embodiment; but it is not in order to limit the present invention; those skilled in the art can make various changes and retouching without departing from the spirit and scope of the present invention, so protection scope of the present invention should be defined by accompanying Claim.

Claims

1. method that in integrated circuit, forms adjacent to a shielding conductor of a holding wire, this method comprises:

Above this holding wire, form one silica layer;

Eat-back this silicon oxide layer, on the sidewall of this holding wire, to form a clearance wall;

Deposition layer of metal layer above this holding wire and this silicon oxide layer;

Remove the head portion of this metal level, make the upper surface of remaining this metal level be lower than the upper surface of this holding wire, remaining this metal level forms a shielding conductor; And

Remove this clearance wall.

2. the method for claim 1, wherein this silicon oxide layer comprises the boron-phosphorosilicate glass that utilizes the plasma reinforced chemical vapour deposition method to be deposited.

3. the method for claim 1, wherein this metal level comprises the tungsten that utilizes chemical vapour deposition technique to deposit.

4. the method for claim 1 also comprises allowing this shielding conductor ground connection.

5. the method for claim 1 also comprised before the etch-back silicon oxide layer this silicon oxide layer is carried out a quick thermal treatment process.

6. the method for claim 1, the method for wherein removing this clearance wall comprise uses low pressure HF gas.

7. method that in integrated circuit, forms adjacent to a shielding conductor of a holding wire, this method comprises:

On the sidewall of this holding wire, form a clearance wall;

Deposition layer of metal layer above this holding wire;

Remove this clearance wall.

8. method as claimed in claim 7, wherein this silicon oxide layer comprises the boron-phosphorosilicate glass that utilizes the plasma reinforced chemical vapour deposition method to be deposited.

9. method as claimed in claim 7, wherein this metal level comprises the tungsten that utilizes chemical vapour deposition technique to deposit.

10. method as claimed in claim 7 also comprises allowing this shielding conductor ground connection.

11. method as claimed in claim 7 also comprised before eat-backing this silicon oxide layer this silicon oxide layer is carried out a quick thermal treatment process.

12. comprising, the method for claim 1, the method for wherein removing this clearance wall use low pressure HF gas.