CN110324114B - Method and device for quickly and adaptively locking frame header of satellite-borne code stream - Google Patents
Method and device for quickly and adaptively locking frame header of satellite-borne code stream Download PDFInfo
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- H—ELECTRICITY
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Abstract
A method for quickly and adaptively locking frame headers of satellite-borne code streams includes carrying out quick frame header matching on code streams, and when 1ACFFC1D appears in code streams, the data may be a true frame header or a false frame header, namely 1ACFFC1D appears in an effective data area. And screening by taking the condition that the distance between two adjacent frame headers is a fixed length. The method has low resource occupancy rate and is easy to realize by adopting FPGA or ASIC. The method can ensure the correct subsequent processing and the frame deviation prevention, and improve the transmission correctness and the anti-interference performance.
Description
Technical Field
The invention relates to a method and a device for quickly and adaptively locking a frame header of a satellite code stream, belonging to the technical field of satellite data transmission.
Background
With the high-speed development of satellite remote sensing technology and the intellectualization of on-board processing tasks, a data transmission system needs to complete the non-loss transmission and correct processing of effective load data of a front-end load in various working modes in real time or quasi-real time, and needs to adapt to code stream burstiness and randomness caused by flexible on-off of the load, so that the design of a method for quickly and adaptively locking a frame header on the satellite is developed.
The use of traditional satellite loads is limited and inflexible. Such as: the power on and off sequence of the front-end equipment and the back-end equipment must be fixed. An explicit startup and shutdown sequence needs to be agreed between the front-end payload sending and the back-end data processor receiving processing: when the computer is started, the data processor is required to be powered on firstly, then the front-end load is powered on, and the load and the data processor start to work normally only after the data processor and the front-end load are powered on stably for a period of time; when the power is off, the load is in an inoperative state, the data processor is powered off first, and then the load is powered off. Meanwhile, when the working mode is switched, the power-off switching is required, the power-on arbitrary switching is not supported, and otherwise, the back-end processing is disordered. And the front-end equipment can not switch the working mode in the working process, because the code stream changes once the front-end equipment is switched, and the rear-end equipment can not perform self-adaptive judgment, the code stream is deviated from frames or wrong frames.
With the increasing of the number of loads on a new generation satellite and the wide application of on-orbit intelligent processing, the satellite loads are subjected to maneuvering detection aiming at important targets, and the front-end loads are subjected to flexible startup and shutdown and dynamic switching of working modes according to the requirements of tasks from the perspective of energy saving of the whole satellite. The traditional method can increase the operation complexity of the whole satellite, thus inevitably leading to the timeliness of the satellite for acquiring data to be greatly reduced.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the method for quickly and adaptively locking the frame header of the satellite-borne code stream overcomes the defects of the prior art, firstly, the code stream is quickly matched with the frame header, and when the code stream has 1ACFFC1D, the data can be true frame headers or false frame headers, namely 1ACFFC1D appears in an effective data area. And screening by taking the condition that the distance between two adjacent frame headers is a fixed length. The method has low resource occupancy rate and is easy to realize by adopting FPGA or ASIC. The method can ensure the correct subsequent processing and the frame deviation prevention, and improve the transmission correctness and the anti-interference performance.
The purpose of the invention is realized by the following technical scheme:
a method for quickly and adaptively locking frame headers of satellite-borne code streams writes the code streams into a shift register, and comprises the following steps:
s1, sequentially comparing the data in the shift register with the frame header data until the data in the shift register is consistent with the frame header data, generating a first frame header identifier FLAG1 by using a controller, and simultaneously starting counting by using a first counter CNT 1; then, the process proceeds to S2;
s2, writing data in the shift register behind the first frame header identifier FLAG1 into a first FIFO memory 1, sequentially comparing the data in the first FIFO memory 1 with frame header data, and when the data in the first FIFO memory FIFO1 is consistent with the frame header data, generating a second frame header identifier FLAG 2by using a controller and starting counting by using a second counter CNT 2; then writing the data in the shift register after the second frame header FLAG2 into a second FIFO memory FIFO 2; judging whether the result of the first counter CNT1 is one frame length, if so, generating an event Y1 by the controller, otherwise, generating an event N1 by the controller; then, the process proceeds to S3;
s3, sequentially comparing the data in the second FIFO memory FIFO2 with the frame header data, and when the data in the second FIFO memory FIFO2 are consistent with the frame header data, generating a third frame header identifier FLAG 3by using a controller, and simultaneously counting by using a third counter CNT 3; if the result of the second counter CNT2 is a frame length, the controller generates an event Y21; if the result of the first counter CNT1 is one frame long, the controller generates an event Y22; if the result of the second counter CNT2 does not equal one frame length and the result of the first counter CNT1 does not equal one frame length, the controller generates an event N2;
when the event Y1 and the event Y21 are generated, the controller generates a frame header locking identifier LOCK1, and then the step is switched to S5, otherwise the step is switched to S4;
s4, comparing the data in the second FIFO memory 2 behind the third frame header FLAG3 with the frame header data in sequence, and when the data in the second FIFO memory 2 is consistent with the frame header data; if the result of the third counter CNT3 is a frame length, the controller generates an event Y31; if the result of the second counter CNT2 is one frame long, the controller generates an event Y32; if the result of the third counter CNT3 is not equal to one frame length and the result of the second counter CNT2 is not equal to one frame length, go to S1 to restart the alignment;
when the event N1, the event Y21 and the event Y31 are generated, the controller generates a frame header locking identifier LOCK2 and then switches to S5; when the event N1, the event Y22 and the event Y31 are generated, the controller generates a frame header locking identifier LOCK3 and then switches to S5; when the event Y1, the event N2 and the event Y32 are generated, the controller generates a frame header locking identifier LOCK4 and then switches to S5;
and S5, completing frame header locking.
After S5, when the mark of frame head locking is LOCK1, the code stream is output to the external rear end and starts from the first frame head mark FLAG 1; when the mark of frame header locking is LOCK2, the code stream is output to the external rear end, and the code stream starts from a second frame header mark FLAG 2; when the mark of frame header locking is LOCK3, the code stream is output to the external rear end, and the code stream starts from a first frame header mark FLAG 1; when the mark of frame header locking is LOCK4, the code stream is output to the external back end, starting from the first frame header mark FLAG 1.
According to the method for quickly and adaptively locking the frame header of the satellite-borne code stream, after S5, whether the frame header appears in the shift register is judged at intervals of one frame length, if so, the controller generates a frame header identifier FLAG, data in the shift register after the frame header identifier FLAG is written into a second FIFO memory FIFO2, and if not, the step is switched to S1 to restart comparison.
According to the method for quickly and adaptively locking the frame head of the satellite-borne code stream, a frame counter is arranged in each frame of data, after the controller generates a frame head identifier FLAG, whether the frame counting of the frame counter in two continuous frames is continuous or not is judged, if the frame counting is continuous, the data in the shift register behind the frame head identifier FLAG is written into a second FIFO memory FIFO2, and if not, the comparison is started again after S1.
According to the method for quickly and adaptively locking the frame header of the satellite-borne code stream, CRC check bits are arranged in each frame of data, after the controller generates a frame header identifier FLAG, whether the CRC check bits in any frame of data are consistent with the calculation result of the data frame is judged, if so, the data in the shift register behind the frame header identifier FLAG are written into a second FIFO memory FIFO2, and otherwise, S1 is switched to restart the comparison.
A satellite-borne code stream fast self-adaptive frame header locking device comprises a controller, a shift register, a frame header frame length definition module, a first counter CNT1, a second counter CNT2, a third counter CNT3, a first FIFO memory FIFO1 and a second FIFO memory FIFO 2;
the frame header and frame length definition module is used for interacting with the outside to define and store the frame header and the frame length; the controller is used for controlling the shift register, the frame header frame length defining module, the first counter CNT1, the second counter CNT2, the third counter CNT3, the first FIFO memory FIFO1 and the second FIFO memory FIFO 2; the controller is used for comparing code stream data with frame header data and judging an event result;
and performing frame header locking by adopting the method for quickly and adaptively locking the frame header of the satellite-borne code stream.
The satellite-borne code stream fast self-adaptive frame header locking device also comprises a parallel-serial conversion module; and the parallel-serial conversion module is used for converting the parallel code stream into a serial code stream and then outputting the serial code stream to the shift register.
According to the satellite-borne code stream fast self-adaptive frame header locking device, the controller is further used for receiving an external channel associated gating signal, and when the channel associated gating signal is effective, the external satellite-borne code stream is written into the parallel-serial conversion module.
After S5, when the mark of frame head locking is LOCK1, the satellite-borne code stream fast self-adaptive locking frame head device outputs the code stream to the external rear end, and starts from a first frame head mark FLAG 1; when the mark of frame header locking is LOCK2, the code stream is output to the external rear end, and the code stream starts from a second frame header mark FLAG 2; when the mark of frame header locking is LOCK3, the code stream is output to the external rear end, and the code stream starts from a first frame header mark FLAG 1; when the mark of frame header locking is LOCK4, the code stream is output to the external back end, starting from the first frame header mark FLAG 1.
After S5, the fast self-adaptive frame header locking device for the satellite-borne code stream judges whether a frame header appears in the shift register at intervals of one frame length, if so, the controller generates a frame header identifier FLAG, and writes data in the shift register after the frame header identifier FLAG into a second FIFO memory FIFO2, otherwise, the device is switched to S1 to restart comparison.
Compared with the prior art, the invention has the following beneficial effects:
(1) the invention carries on the fast frame head match to the code stream first, when the code stream appears 1ACFFC1D, then the data may be the true frame head, also may be the false frame head, namely 1ACFFC1D appears in the effective data area; screening by taking the condition that the distance between two adjacent frame headers is a fixed length;
(2) the method has low resource occupancy rate and is easy to realize by adopting an FPGA or an ASIC; by simply changing parameters, the correct receiving of code streams with different frame headers and different frame lengths can be realized, and the data can be cut off or started by the former-stage equipment at will, so that the method can ensure the correct and unbiased frame subsequent processing, and the transmission correctness and the anti-interference performance are improved;
(3) the method has extremely wide application in efficient and correct transmission between equipment, and has no requirement on the on-off sequence of the equipment;
(4) the method of the invention utilizes double FIFO to carry out ping-pong decision, and the cycle is carried out in sequence, on one hand, invalid signals are filtered out, and on the other hand, valid signals are retained.
Drawings
FIG. 1 is a flow chart of steps of a method for rapidly and adaptively locking a frame header of a satellite-borne code stream according to the present invention;
FIG. 2 is a schematic diagram of the apparatus of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
A method for quickly and adaptively locking a frame header of a satellite-borne code stream writes the code stream into a shift register, and comprises the following steps as shown in figure 1.
S1, sequentially comparing the data in the shift register with the frame header data until the data in the shift register is consistent with the frame header data, generating a first frame header identifier FLAG1 by using a controller, and simultaneously starting counting by using a first counter CNT 1; then, the process proceeds to S2;
s2, writing data in the shift register behind the first frame header identifier FLAG1 into a first FIFO memory 1, sequentially comparing the data in the first FIFO memory 1 with frame header data, and when the data in the first FIFO memory FIFO1 is consistent with the frame header data, generating a second frame header identifier FLAG 2by using a controller and starting counting by using a second counter CNT 2; then writing the data in the shift register after the second frame header FLAG2 into a second FIFO memory FIFO 2; judging whether the result of the first counter CNT1 is one frame length, if so, generating an event Y1 by the controller, otherwise, generating an event N1 by the controller; then, the process proceeds to S3;
s3, sequentially comparing the data in the second FIFO memory FIFO2 with the frame header data, and when the data in the second FIFO memory FIFO2 are consistent with the frame header data, generating a third frame header identifier FLAG 3by using a controller, and simultaneously counting by using a third counter CNT 3; if the result of the second counter CNT2 is a frame length, the controller generates an event Y21; if the result of the first counter CNT1 is one frame long, the controller generates an event Y22; if the result of the second counter CNT2 does not equal one frame length and the result of the first counter CNT1 does not equal one frame length, the controller generates an event N2;
when the event Y1 and the event Y21 are generated (three consecutive events are true), the controller generates a frame header locking identifier LOCK1, and then the step goes to S5, otherwise, the step goes to S4;
s4, comparing the data in the second FIFO memory 2 behind the third frame header FLAG3 with the frame header data in sequence, and when the data in the second FIFO memory 2 is consistent with the frame header data; if the result of the third counter CNT3 is a frame length, the controller generates an event Y31; if the result of the second counter CNT2 is one frame long, the controller generates an event Y32; if the result of the third counter CNT3 is not equal to one frame length and the result of the second counter CNT2 is not equal to one frame length, go to S1 to restart the alignment;
when the event N1, the event Y21 and the event Y31 are generated (the first is a dummy frame header), the controller generates a frame header locking identifier LOCK2, and then goes to S5; when the event N1, the event Y22 and the event Y31 are generated (the second is a dummy frame header), the controller generates a frame header locking identifier LOCK3, and then goes to S5; when the event Y1, the event N2 and the event Y32 are generated (the third is a false frame header), the controller generates a frame header locking identifier LOCK4, and then the operation goes to S5;
s5, completing frame header locking; when the mark of frame header locking is LOCK1, the code stream is output to the external rear end, and the code stream starts from a first frame header mark FLAG 1; when the mark of frame header locking is LOCK2, the code stream is output to the external rear end, and the code stream starts from a second frame header mark FLAG 2; when the mark of frame header locking is LOCK3, the code stream is output to the external rear end, and the code stream starts from a first frame header mark FLAG 1; when the mark of frame header locking is LOCK4, the code stream is output to the external rear end, and the code stream starts from a first frame header mark FLAG 1;
s6, judging whether a frame header appears in the shift register every other frame length, if so, generating a frame header identifier FLAG by the controller, writing data in the shift register behind the frame header identifier FLAG into a second FIFO memory FIFO2, and otherwise, turning to S1 to restart the comparison.
A satellite-borne code stream fast self-adaptive frame header locking device comprises a controller, a shift register, a frame header frame length definition module, a first counter CNT1, a second counter CNT2, a third counter CNT3, a first FIFO memory FIFO1, a second FIFO memory FIFO2 and a parallel-serial conversion module; as shown in fig. 2.
The parallel-serial conversion module is used for converting the parallel code stream into a serial code stream and then outputting the serial code stream to the shift register; the frame header and frame length definition module is used for interacting with the outside to define and store the frame header and the frame length; the controller is used for controlling the shift register, the frame header frame length defining module, the first counter CNT1, the second counter CNT2, the third counter CNT3, the first FIFO memory FIFO1 and the second FIFO memory FIFO 2; the controller is used for comparing code stream data with frame header data and judging an event result; the controller is also used for receiving an external channel associated gating signal, and when the channel associated gating signal is effective, the external satellite-borne code stream is written into the parallel-serial conversion module.
And performing frame header locking by adopting the method for quickly and adaptively locking the frame header of the satellite-borne code stream.
Example 1:
the invention provides a method for adaptively locking frame headers in continuous code streams, which can be used for eliminating abnormal data such as false frame headers, half-frame data and the like. 1ACFFC1D is the most commonly used frame header in the CCSDS protocol, and this example uses 1ACFFC1D as the frame header for analysis. In the operations of scrambling of on-satellite codes and descrambling of ground codes, the frame header is the only reference for processing all data, and the correct locking of the frame header can ensure that the code stream is continuously and uninterruptedly output according to frames without losing. The code stream is subjected to fast frame header matching, and when 1ACFFC1D appears in the code stream, the data may be a true frame header or a false frame header, that is, 1ACFFC1D appears in the valid data area. And screening by taking the condition that the distance between two adjacent frame headers is a fixed length. In order to improve the accuracy of screening without losing correct data, when 3 consecutive 1ACFFC1D satisfy the interval of fixed length at the same time, then these 3 frame headers must be true frame headers, otherwise, discard. When the frame head is locked, the method can adapt to the condition that any position in 3 frames of data contains false frame heads, and can adapt to the condition that effective data in one frame contains any number of false frame heads after the frame head is locked. The method has low resource occupancy rate and is easy to realize by adopting FPGA or ASIC. The method can ensure the correct and unbiased frame of the subsequent processing, improves the correctness and the anti-interference performance of transmission, has wide application range of high-efficiency correct transmission between equipment and has no requirement on the on-off sequence of the equipment.
First, a frame header is defined, and the frame header and the frame length are input into a frame header and frame length defining module, where the frame header is 1ACFFC1D and the frame length is 1024 in this embodiment. When the channel gate control is effective, the channel associated clock input by the front end load writes channel associated data (bit width D-0 is applicable, D is a natural number) into the controller, then performs parallel-serial conversion on the data, if D is 0, it indicates that the input is a serial code stream, and does not perform the operation. The serial code stream is then written into the shift register and compared one by one with 1ACFFC 1D. If there is a match, an identification signal FLAG1 is generated, otherwise the received data is discarded. To ensure that valid data is not lost, all data from the generated FLAG1 is written into the FIFO1, while the counter CNT1 begins counting. When the next 1ACFFC1D was searched, CNT1 just reached 1024, indicating that FLAG1 may be a true frame header, while FLAG1 and CNT2 were generated. The frame header is locked only if the frame header interval that satisfies 3 consecutive frames is 1024. In order to ensure that the valid signal is not lost, the embodiment adopts double FIFOs to perform ping-pong decision, and the two decisions are circulated in sequence, so that on one hand, invalid signals are filtered out, and on the other hand, valid signals are retained.
The specific design method is as follows: according to the input data bit width D of the interface and the agreed frame head and frame length, the data bit width of the two cache FIFOs is set to be D, the FIFO cache depth is set to be L, and the L is required to be larger than N (so as to ensure that the cache is not full when data is written in). The gated active level is defined as forward, and the gated inactive level is defined as backward, where backward can be 0 up to T. The maximum back-off is agreed to ensure that the receiving state machine can jump to an IDLE state when the receiving state machine cannot receive data for a long time, and the self-recovery of the state machine is effectively ensured.
The control flow of the method for quickly and adaptively locking the frame head of the satellite-borne code stream is as follows:
step one, detecting whether a channel associated gating isyn is effective or not by utilizing a channel associated clock iclk input by a front end load, carrying out parallel-serial conversion on corresponding idata [ D..0] when the gating is detected to be effective, converting the idata into a serial code stream, and then switching to step two;
and step two, the link writes the serial code stream sent in the step one into a shift register, then compares the numerical value in the shift register with 1ACFFC1D one by one, and filters out invalid data. When the matching is consistent, the controller generates a frame header FLAG1, and the counter CNT1 starts counting;
step three, writing the data from the time when the FLAG1 is generated in step two into the FIFO1, and further searching for the next 1ACFFC 1D;
step four, repeating the action of step two, when 1ACFFC1D is searched, generating the frame header FLAG2 and the frame counter CNT2, and simultaneously writing the data into the FIFO 2. In this step it is determined whether CNT1 equals 1024, if the condition is fulfilled, event Y1 is generated, otherwise event N1 is generated;
step five, repeating the action of the step two, when 1ACFFC1D is searched, generating a frame header identification FLAG3 and a frame counter CNT3, judging whether CNT2 is equal to 1024, if the condition is met, generating an event Y21, judging whether CNT1 is equal to 1024, if the condition is met, generating an event Y22, and if the CNT2 is not equal to 1024 and the CNT1 is not equal to 1024, generating an event N2 by the controller;
when an event Y1 and an event Y21 are generated, the controller generates a frame head locking identifier LOCK1, then frame head locking is completed, otherwise, frame head searching is continued, when 1ACFFC1D is searched, whether CNT3 is equal to 1024 is judged, and if the condition is met, an event Y31 is generated; determining whether CNT2 equals 1024, if the condition is satisfied, generating event Y33; if the CNT3 is not equal to 1024 and the CNT2 is not equal to 1024, the step two is carried out to continue searching the frame header;
when the event N1, the event Y21 and the event Y31 are all generated (the first is a false frame header), the controller generates a frame header locking identifier LOCK2 and then completes frame header locking; when the event N1, the event Y22 and the event Y31 are generated (the second is a false frame header), the controller generates a frame header locking identifier LOCK3 and then completes frame header locking; when the event Y1, the event N2 and the event Y32 are generated (the third is a false frame header), the controller generates a frame header locking identifier LOCK4 and then completes frame header locking;
and step six, after the frame header is locked, in order to ensure that the subsequent code stream does not generate frame offset and frame error, the controller still continues to search the frame header, at the moment, only judges whether 1ACFFC1D appears in the code stream at intervals of fixed length 1024, and if the frame header is matched with the code stream, continues to generate an identifier FLAG of the frame header, and writes the data into FIFO 2. If not, the step two is carried out to restart the search for the frame header.
Preferably, in the sixth step, after the FLAG of the frame header is generated, the system may automatically detect the check bit of each frame or the frame counter; each frame of data contains a frame counter of 3 bytes for indicating whether the frame is continuous, and a CRC check bit of 2 bytes for checking whether an error exists in data transmission. Two criteria of a frame counter and a CRC check bit are added in the controller.
The valid data controller will automatically detect the frame counter and CRC check bits every 1024 (frames length of one frame). If the frame count is not continuous or the received CRC check bit is inconsistent with the actual calculation, the locking is considered to be abnormal, and the step two needs to be carried out to restart the search of the frame head; the method can adapt to the condition that no CRC check bit exists in other self-defined protocols. If the false frame header interval of each frame is also 1024 and is just locked to the false frame header, the abnormal condition can be identified by adopting a preferred method.
It should be noted that, in the sixth step, after the FLAG of the frame header is generated, the check bit and the frame counter may also be used as the criterion at the same time, and when the check bit and the frame counter are judged at the same time, since the check bit may cover the whole frame, the check bit is preferentially judged, and then the frame counter is judged, so as to improve the locking efficiency.
The adaptive locking method of the frame header in the code stream can quickly and accurately lock the frame header, ensure effective data not to lose and receive and ensure the correctness of subsequent transmission processing. The method can adapt to the condition of continuous or discontinuous code streams, has low resource occupancy rate, and saves the system and hardware circuit modification to improve the required higher cost.
Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.
Claims (7)
1. A method for quickly and adaptively locking a frame header of a satellite-borne code stream writes the code stream into a shift register, and is characterized by comprising the following steps of:
s1, sequentially comparing the data in the shift register with the frame header data until the data in the shift register is consistent with the frame header data, generating a first frame header identifier FLAG1 by using a controller, and simultaneously starting counting by using a first counter CNT 1; then, the process proceeds to S2;
s2, writing data in the shift register behind the first frame header identifier FLAG1 into a first FIFO memory 1, sequentially comparing the data in the first FIFO memory 1 with frame header data, and when the data in the first FIFO memory FIFO1 is consistent with the frame header data, generating a second frame header identifier FLAG 2by using a controller and starting counting by using a second counter CNT 2; then writing the data in the shift register after the second frame header FLAG2 into a second FIFO memory FIFO 2; judging whether the result of the first counter CNT1 is one frame length, if so, generating an event Y1 by the controller, otherwise, generating an event N1 by the controller; then, the process proceeds to S3;
s3, sequentially comparing the data in the second FIFO memory FIFO2 with the frame header data, and when the data in the second FIFO memory FIFO2 are consistent with the frame header data, generating a third frame header identifier FLAG 3by using a controller, and simultaneously counting by using a third counter CNT 3; if the result of the second counter CNT2 is a frame length, the controller generates an event Y21; if the result of the first counter CNT1 is one frame long, the controller generates an event Y22; if the result of the second counter CNT2 does not equal one frame length and the result of the first counter CNT1 does not equal one frame length, the controller generates an event N2;
when the event Y1 and the event Y21 are generated, the controller generates a frame header locking identifier LOCK1, and then the step is switched to S5, otherwise the step is switched to S4;
s4, comparing the data in the second FIFO memory 2 behind the third frame header FLAG3 with the frame header data in sequence, and when the data in the second FIFO memory 2 is consistent with the frame header data; if the result of the third counter CNT3 is a frame length, the controller generates an event Y31; if the result of the second counter CNT2 is one frame long, the controller generates an event Y32; if the result of the third counter CNT3 is not equal to one frame length and the result of the second counter CNT2 is not equal to one frame length, go to S1 to restart the alignment;
when the event N1, the event Y21 and the event Y31 are generated, the controller generates a frame header locking identifier LOCK2 and then switches to S5; when the event N1, the event Y22 and the event Y31 are generated, the controller generates a frame header locking identifier LOCK3 and then switches to S5; when the event Y1, the event N2 and the event Y32 are generated, the controller generates a frame header locking identifier LOCK4 and then switches to S5;
s5, completing frame header locking;
after S5, judging whether a frame header appears in the shift register at intervals of one frame length, if so, generating a frame header identifier FLAG by the controller, writing data in the shift register behind the frame header identifier FLAG into a second FIFO memory FIFO2, and otherwise, turning to S1 to restart comparison;
after the controller generates a frame header identifier FLAG, whether the frame counting of the frame counters in two continuous frames is continuous is judged, if so, the data in the shift register behind the frame header identifier FLAG is written into the second FIFO memory FIFO2, otherwise, the comparison is started again in S1; and CRC check bits are arranged in each frame of data, after the controller generates a frame header identifier FLAG, whether the CRC check bits in any frame of data are consistent with the calculation result of the frame is judged, if so, the data in the shift register behind the frame header identifier FLAG are written into the second FIFO memory 2, and if not, the comparison is started again by switching to S1.
2. The method according to claim 1, wherein after S5, when the mark of frame header locking is LOCK1, the output of the code stream to the external back end starts from the first frame header mark FLAG 1; when the mark of frame header locking is LOCK2, the code stream is output to the external rear end, and the code stream starts from a second frame header mark FLAG 2; when the mark of frame header locking is LOCK3, the code stream is output to the external rear end, and the code stream starts from a first frame header mark FLAG 1; when the mark of frame header locking is LOCK4, the code stream is output to the external back end, starting from the first frame header mark FLAG 1.
3. A satellite-borne code stream fast self-adaptive frame header locking device is characterized by comprising a controller, a shift register, a frame header frame length definition module, a first counter CNT1, a second counter CNT2, a third counter CNT3, a first FIFO memory FIFO1 and a second FIFO memory FIFO 2;
the frame header and frame length definition module is used for interacting with the outside to define and store the frame header and the frame length; the controller is used for controlling the shift register, the frame header frame length defining module, the first counter CNT1, the second counter CNT2, the third counter CNT3, the first FIFO memory FIFO1 and the second FIFO memory FIFO 2; the controller is used for comparing code stream data with frame header data and judging an event result;
frame header locking is performed by the method of claim 1.
4. The apparatus according to claim 3, further comprising a parallel-to-serial conversion module; and the parallel-serial conversion module is used for converting the parallel code stream into a serial code stream and then outputting the serial code stream to the shift register.
5. The apparatus as claimed in claim 4, wherein the controller is further configured to receive an external channel associated gating signal, and write the external satellite code stream into the parallel-to-serial conversion module when the channel associated gating signal is valid.
6. The apparatus of claim 3, wherein after S5, when the mark of frame header LOCK is LOCK1, the output of the code stream to the external back end starts from the first frame header mark FLAG 1; when the mark of frame header locking is LOCK2, the code stream is output to the external rear end, and the code stream starts from a second frame header mark FLAG 2; when the mark of frame header locking is LOCK3, the code stream is output to the external rear end, and the code stream starts from a first frame header mark FLAG 1; when the mark of frame header locking is LOCK4, the code stream is output to the external back end, starting from the first frame header mark FLAG 1.
7. The apparatus according to claim 3, wherein after S5, it is determined whether a frame header occurs in the shift register every other frame length, and if so, the controller generates a frame header FLAG, and writes data in the shift register after the frame header FLAG into the second FIFO memory FIFO2, otherwise, proceeds to S1 to restart the comparison.
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