CN110323061B - 具有多种烧制模式的三维模组 - Google Patents
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- 239000000919 ceramic Substances 0.000 claims description 75
- 239000000758 substrate Substances 0.000 claims description 27
- 229910010293 ceramic material Inorganic materials 0.000 claims description 22
- 239000003985 ceramic capacitor Substances 0.000 claims description 4
- 239000003989 dielectric material Substances 0.000 abstract description 35
- 238000010344 co-firing Methods 0.000 abstract description 11
- 239000010410 layer Substances 0.000 description 133
- 239000003990 capacitor Substances 0.000 description 70
- 239000011229 interlayer Substances 0.000 description 13
- 239000000463 material Substances 0.000 description 11
- 238000000034 method Methods 0.000 description 10
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- 229910052751 metal Inorganic materials 0.000 description 9
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- 239000007772 electrode material Substances 0.000 description 6
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- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
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- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
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- 239000010949 copper Substances 0.000 description 4
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Abstract
本发明披露了一种具有多种烧制模式的三维模组(多模三维模组)。它含有多个器件层,每个器件层包括多个无源元件,无源元件含有至少一层具有高介电常数的介质材料。器件层被互连层分隔。每个互连层包括至少一层具有低介电常数的介质材料。通过对单个器件层中的无源元件进行共同烧制(共烧),可减少无源元件的安装时间与安装成本;通过分别烧制(分烧)不同器件层和不同互连层,多模三维模组具有更好的电学性能。
Description
技术领域
本发明涉及多层模组领域,更确切地说,涉及具有多种烧制模式的的多层模组。
背景技术
MLCC电容(片式多层陶瓷电容)被广泛应用到模组中。图1A表示一种现有技术中应用MLCC电容集群的模组80。它含有一模组衬底30、至少一芯片50、以及多个MLCC电容(包括大电容10和小电容20)。模组衬底30中含有对芯片50和电容10、20实现电连接的电路(在此为简便计,在此没有画出)。在实际应用中,电容10、20等的电容值范围很大,如从数十pF到数百nF,甚至uF。一般说来,最大电容是最小电容的至少10倍;在某些情形下,最大电容是最小电容的至少100倍;在极端情况下,最大电容甚至是最小电容的1000倍以上。
图1B是大电容10的截面图。其厚度为t1,尺寸为w1。它还含有一陶瓷体16,该陶瓷体16含有多层具有高介电常数的介质材料、一对覆盖该陶瓷体16的外部电极15、17、两组将介质材料分隔的内部电极12、14。其中,第一组内部电极12相对于第二组内部电极14向左偏置。第一组内部电极12包括四个左内部电极12a-12d;第二组内部电极14包括四个右内部电极14a-14d;第一组内部电极12与第二组内部电极14相互交错。第一外部电极15与第一组内部电极12中的所有内部电极12a-12d电连接;第二外部电极17与第二组内部电极14中的所有内部电极14a-14d电连接。
图1C是小电容20的截面图。其厚度为t2,尺寸为w2。它含有一陶瓷体26、以及两组内部电极25、27。由于其电容比大电容10小,小电容20的第一组内部电极组22仅包括两个左内部电极22a-22b;第二组内部电极24仅包括两个右内部电极24a-24b。
MLCC电容10、20被称为一体化电容(monolithic capacitor)。所谓一体化,是指在烧制时所有的介质材料和内部电极通过一次高温烧制制造完成。即使如此,电容10和20仍然是分立器件。在安装时,每个这些分立电容需要用机械臂拾取,对准并安装在模组30的预设位置上。由于模组80中电容数量众多,这种安装过程相当费时费钱。
传统模组80采用预制的、通用电容10、20。对于电容值为数十pF到数个nF的小电容20,其厚度t2一般为亚毫米级,这对于移动应用来说尚属合理。然而,对于数个uF的大电容10,其内部电极和介质材料多达数百层,这导致其厚度t1达到毫米级(如~5毫米),这远远大于芯片50的厚度t3。这么厚的大电容10对于移动设备来说太厚了。
为了减少模组的面积,一种解决方案是将多个无源元件(如电阻、电容、电感或其它)集成在一个多层模组当中。LTCC(低温共烧陶瓷)正是为了满足这种需求而问世。它将多个无源元件一体烧制成型。由于LTCC技术需要同时形成电容、电阻、电感等多种无源元件,它需要形成多种陶瓷材料及金属电极材料。这些陶瓷材料和金属电极对烧制条件(如烧制温度)有不同要求。对一种陶瓷材料(或,金属电极)优化的烧制条件不一定能对另一种陶瓷材料(或,金属电极)优化。此外,虽然低温共烧使金属电极可以使用高导电金属材料(如铝、铜、银、金等)。但是,低温烧制形成的陶瓷材料的介电常数不高,一般仅为20左右。
发明内容
本发明的主要目的是制造一种紧凑的高性能模组。
本发明的另一目的是减少无源元件的安装时间与安装成本。
本发明的另一目的是减小包含无源元件的模组厚度。
本发明的另一目的是改善无源元件中介电材料的质量。
本发明的另一目的是提高无源元件的互连速度。
本发明的另一目的是增加三维模组中MLCC电容的容值范围。
根据本发明的以上目的,本发明披露了一种具有多种烧制模式的三维模组(多模三维模组)。多模三维模组含有多个器件层,这些器件层被多个互连层分隔。每个器件层包括多个无源元件,该无源元件含有至少一层具有高介电常数的介质材料,一般为陶瓷材料。每个互连层包括至少一层具有低介电常数的介质材料,一般为有机材料。通过对单个器件层中的无源元件进行共同烧制(共烧),可减少无源元件的安装时间与安装成本;通过分别烧制(分烧)不同器件层和不同互连层,多模三维模组比低温共烧陶瓷(LTCC)和高温共烧陶瓷(HTCC)具有更好的电学性能。
多模三维模组1000的烧制过程包括单层共烧(共同烧制)模式和多层分烧(分别烧制)模式。这与LTCC(或,HTCC)不同。LTCC(或,HTCC)仅使用多层共烧,即所有的器件层和互连层在一次烧制步骤中整体烧制完成。但在本发明中,虽然单个器件层中的多个无源元件为共烧;不同器件层和不同互连层为分烧,器件层和互连层之间也是分烧。
通过器件层和互连层之间的分烧,具有高介电常数的介质材料(如陶瓷材料)可以在较高烧制温度(如~1500℃)下烧制,故多模三维模组的无源元件比LTCC具有更大的介电常数和更好的品质因数;同时,具有低介电常数的介质(如有机材料)可以在较低烧制温度(如~200℃)下烧制,故多模三维模组的互连层可以使用具有高电导率的导电材料(如铝,铜,银,金或其合金),从而比HTCC的互连层具有更快的速度。
另一方面,单个器件层中的无源元件为共烧,即它们在单一烧制步骤中一体化烧制。在共烧前,这些无源元件所需的陶瓷胶带层(ceramic tape,也被称为green tape)和电极材料层预先形成在陶瓷基板上的预定位置。在共烧后,陶瓷胶带层和电极材料层在预定位置形成无源元件。由于这些无源元件固定在陶瓷基板上,位置相对固定,故它们后期可以整体安装到模组上。由于不需要单独安装无源元件,可以减少无源元件的安装时间和安装成本。在单个器件层中,共烧的MLCC电容集群含有具有相同高介电常数的介质材料;此外,这些介质材料具有相同的厚度,其上表面和下表面分别是共面的。
相应地,本发明提出一种具有多种烧制模式的三维模组(多模三维模组)(1000),其特征在于含有:第一器件层(110),所述第一器件层(110)含有多个共同烧制的第一无源元件(110x、110y),所述第一无源元件(110x)含有至少一层具有高介电常数的第一介质材料(160x);第一互连层(170),所述第一互连层(170)位于第一器件层(110)上并耦合所述无源元件(110x、110y),所述第一互连层(170)含有至少一层具有低介电常数的第二介质材料(172)和一层导电材料(174);第二器件层(210),所述第二器件层(210)含有多个共同烧制的第二无源元件(210x、210y),所述第二无源元件(210x)含有至少一层具有高介电常数的第三介质材料(260x);层间连接(290),所述层间连接(290)将所述第一和第二器件层(110、210)进行耦合;其中,所述第一和第三介电材料(160x、260x)分别烧制;所述第一和第三介电材料(160x、260x)的烧制温度高于所述第二介电材料(172)的烧制温度。
本发明还提出一种具有多种烧制模式的三维模组(多模三维模组)(1000),其特征在于含有:第一器件层(110),所述第一器件层(110)含有电容值相差至少10倍的第一和第二电容(110x、110y),所述第一和第二电容(110x、110y)含有相同的、具有高介电常数的第一介质材料(160x、160y)并具有相同厚度(Dx1、Dy1);第一互连层(170),所述第一互连层(170)位于第一器件层(110)上并耦合所述第一和第二电容(110x、110y),所述第一互连层(170)含有至少一层具有低介电常数的第二介质材料(172)和一层导电材料(174);第二器件层(210),所述第二器件层(210)含有多个第二无源元件(210x、210y),所述第二无源元件(210x)含有至少一层具有高介电常数的第三介质材料(260x);层间连接(290),所述层间连接(290)将所述第一和第二器件层(110、210)进行耦合;其中,所述第一和第三介电材料(160x、260x)分别烧制,所述第一和第三介电材料(160x、260x)的烧制温度高于所述第二介电材料(172)的烧制温度。
为了增加每个器件层中MLCC电容的电容范围(即最大和最小电容值之间的电容比),除了改变电容的物理尺寸外,还可以改变电容的内部电极数量。例如,具有最大电容值的MLCC电容可以含有全套内部电极,即其内部电极的数量是其陶瓷体最多允许的内部电极数量。另一方面,具有最小电容值的MLCC电容不含有全套内部电极,即其内部电极的数量小于其陶瓷体最多允许的内部电极数量。从另一个角度看,陶瓷体包括有效部分和无效部分:有效部分的陶瓷材料含有内电极;无效部分的陶瓷材料并不含内部电极。
相应地,本发明提出一种多层陶瓷电容(MLCC)(110y`),其特征在于含有:一陶瓷体(160y),所述陶瓷体(160y)含有具有高介电常数的一介质材料;第一和第二外部电极(140y、150y),所述第一和第二电极(140y、150y)位于所述陶瓷体(160y)的外表面;多个内部电极(120y、130y),所述内部电极(120y、130y)以交错的方式从所述第一和第二外部电极(140y、150y)延伸到所述陶瓷体(160y)内部;所述陶瓷体(160y)包括有效部分(160y1)和无效部分(160y2、160y4),所述有效部分(160y1)含有内部电极(120y、130y),所述无效部分(160y2、160y4)不含内部电极,所述无效部分(160y2)的厚度(Td)至少是所述有效部分(160y1)中相邻内电极之间最大距离(Se)的两倍。
附图说明
图1A是一种传统模组(现有技术)的截面图;图1B是一种大电容10(现有技术)的截面图;图1C是是一种小电容20(现有技术)的截面图。
图2是第一种多模三维模组1000的截面图。
图3A-图3D是图2中四个MLCC电容110x、110y、210x、210y的截面图。
图4A-图4H是实现第一种多模三维模组1000时多个工艺步骤的截面图。
图5是第二种多模三维模组1000的截面图。
图6是第三种多模三维模组1000的截面图。
图7A是第一种器件层110的截面图,它含有两个电容值相差极大的电容110x、110y`;图7B是含有第一种无效部分160y2电容110y`的截面图。
图8A是第二种器件层110的截面图,它含有两个电容值相差极大的电容110x、110y`;图8B是含有第二种无效部分160y4电容110y`的截面图。
注意到,这些附图仅是概要图,它们不按比例绘图。为了显眼和方便起见,图中的部分尺寸和结构可能做了放大或缩小。在不同实施例中,数字后面的字母后缀表示同一类结构的不同实例;相同的数字前缀表示相同或类似的结构。陶瓷体及其中具有高介电常数的介质材料使用同一标号,如160x既表示陶瓷体,也表示其中所含的介质材料。“/”表示“和”或“或”的关系。
在本说明书中,“烧制”是指最终形成介质材料的高温工艺步骤。在陶瓷材料制造中,“烧制”又被称为烧结,它指在陶瓷材料成形过程中,在陶瓷材料上施加热或压力,使陶瓷材料中的物质相互溶解在一起,以增强其机械和电学性能的过程。“烧制温度”是陶瓷材料加工时的最高加工温度。在有机材料制造中,“烧制”又被称为固化,它指高分子材料因外部因素导致高分子交联而导致的韧化和硬化现象。“烧制温度”是有机材料固化时的最高加工温度。
具体实施方式
本发明披露了一种多模三维模组。它含有多个器件层,这些器件层被多个互连层分隔。每个器件层包括多个无源元件,该无源元件含有至少一层具有高介电常数的介质材料(一般为陶瓷材料)。每个互连层包括至少一层具有低介电常数的介质材料(一般为有机材料)。通过对单个器件层中的无源元件共同烧制(共烧),可减少无源元件的安装时间与安装成本。另一方面,通过分别烧制(分烧)不同器件层和不同互连层,多模三维模组比低温共烧陶瓷(LTCC)和高温共烧陶瓷(HTCC)具有更好的电学性能。
图2披露了第一种多模三维模组1000,它包括两个垂直堆叠的子模组100、200。第一子模组100包括第一器件层110和第一互连层170。第一器件层110包括多个器件,如两个MLCC电容110x,110y和芯片190。这些器件被第一结构材料112包围以实现机械连接。第一互连层170位于第一器件层110上,它包括多个第一介电层172、多个第一金属层174、以及多个用于电耦合第一金属层174的第一层间通孔176。
类似地,第二子模组200包括第二器件层210和第二互连层270。第二器件层210包括多个元件,如两个MLCC电容210x,210y。这些器件210x,210y被第二结构材料212包围以实现机械连接。第二器件层210上的第二互连层270包括多个第二介电层272、多个第二金属层274和多个第二层间通孔176。
第一和第二子模组100、200通过层间连接290连接。层间连接290类似于硅通孔(TSV)。硅通孔可在堆叠的多个芯片之间实现电互连。
图3A-图3D披露了图2中四个MLCC电容110x、110y、210x、210y的更多细节,包括第一器件层100中的两个MLCC电容110x,110y和第二器件层200中的两个MLCC电容210x,210y。例如,MLCC电容110x(图3C)包括陶瓷体160x,两组内部电极120x、120y和一对外部电极140x、140y。陶瓷体160x具有下表面160xb(与电容110x的底表面110s重合)和上表面160xt。陶瓷体160x的厚度为Dx1。第一组内部电极120x整体相对于第二组内部电极130x向左移位,它包括两个内部电极120x1,120x2,它们彼此平行并和第一外部电极140x电学连接。类似地,第二组内部电极130x的两个内部电极130x1、130x2分别连接到第二外部电极150x。MLCC电容110x厚度为Tx1、尺寸为Wx1。
图4A-4H披露了制造多模三维模组1000的工艺流程。首先,在第一陶瓷基板180上以交替的方式层叠多个陶瓷胶带层(ceramic tapes,或green tapes)160a-160e和内部电极层120a-120d,以形成叠层126(图4A)。内部电极层120a-120d在MLCC电容110x的位置处包含了内部电极120x1、120x2;120y1、120y2(图3C)的图案。第一陶瓷基板180是一种刚性衬底,它在经历了陶瓷烧结过程后不会变形。
之后,叠层126连同MLCC电容110x、110y一同被刻蚀从而形成的电容堆110xs、110ys(图4B)。然后,将堆叠在陶瓷基板180上的电容堆110xs、110ys共烧,即在单个烧结步骤中,将形成电容110x、110y的陶瓷胶带层160a-160e和内部电极层120a-120d、与第一陶瓷衬底180作为一个实体,一起进行共同烧结。因为的电容堆110xs、110ys和陶瓷基板180仅包含高温陶瓷材料,其烧结温度可高达~1500℃,所以烧结的陶瓷材料可具有大的介电常数和良好的品质因数。由于陶瓷基底180在烧制期间不变形,且烧结时电容堆110xs、110ys固定在陶瓷基地180上,故烧结后电容110x、110y的相对位置固定。这将有助于未来器件层110和互连层170之间的对准,以及子模组100、200之间的对准。
在烧结步骤之后,在电容堆110xs上形成第一对外部电极140x、150x,在电容叠层110ys上形成第二对外部电极140y、150y(图4C)。含有触点190c的芯片190也安装在陶瓷基板180的表面上(图4D)。在电容110x,110y和芯片190周围淀积结构材料112,以使电容110x、110y的顶表面110xt、110yt与芯片190的顶表面190t和结构材料112的顶表面112t共面(图4E)。一般说来,结构材料112是具有低介电常数的介质材料。在形成结构材料112后,第一器件层110的工艺步骤结束。
接着,在第一器件层110上形成第一互连层170(图4F)。第一互连层170包括多个第一介电层172、多个第一金属层174和多个第一层通孔层176。第一介电层172中含有具有低介电常数的介质材料,一般是有机材料。有机材料需要在其材料形成之前经历固化过程。由于有机材料的固化温度可低至约200℃,金属层174可以使用高导电材料,例如铝,铜,银,金或合金。由于互连层170中有机材料的固化和器件层110中陶瓷材料的烧结是两个单独的步骤,因此互连层170和器件层110的制造在本发明中被称为“分烧”。
由于结构材料112与MLCC电容110x,110y及芯片190机械互联,因此不再需要陶瓷基板180来提供机械支撑以固定这些器件的相对位置。所以这时可以除去第一陶瓷基板180,将器件层110的下表面110s暴露(图4G)。
在制造第一子模组100的同时,可以独立地制造第二子模组200(图4H)。类似图4A-图4B,在第二陶瓷基板280上同时形成MLCC电容210x、210y的陶瓷胶带层和内部电极层并进行共烧。在上述过程中,MLCC电容110x、110y及其陶瓷基板180作为第一实体共烧,MLCC电容210x、210y及其陶瓷基板280作为第二实体共烧。烧结时,第一实体和第二实体可以放在同一个炉子中一起烧结。注意到,尽管在同一炉子中烧结,第一实体和第二实体是作为两个分离的实体烧结的(烧结时,它们没有粘结在一起,而是物理分离的)。之后,形成结构材料212,这时可以除去第二陶瓷基板280。
最后,第一和第二子模组100、200通过胶层282垂直堆叠(图2)。它们之间通过层间连接290互联。在本发明中,层间连接290是层间通孔(如TSV)。对于熟悉本技术的专业人士来说,还可以采用其它形式的层间连接。
多模三维模组1000的烧制过程包括单层共烧(共同烧制)模式和多层分烧(分别烧制)模式。这与LTCC(或,HTCC)不同。LTCC(或,HTCC)仅使用多层共烧,即所有的器件层和互连层在一次烧制步骤中整体烧制完成。但在本发明中,虽然单个器件层(如110)中的多个无源元件(如电容110x、110y)为共烧;不同器件层(如110与210)和不同互连层(如170与270)为分烧,器件层(如110)和互连层(如170)之间也是分烧。
通过器件层110和互连层170之间的分烧,具有高介电常数的介质材料(如陶瓷材料)160x、160y可以在较高烧制温度(如~1500℃)下烧制,故多模三维模组1000的无源元件110x、110y比LTCC具有更大的介电常数和更好的品质因数;同时,具有低介电常数的介质(如有机材料)172可以在较低烧制温度(如~200℃)下烧制,故多模三维模组1000的互连层170可以使用具有高电导率的导电材料(如铝,铜,银,金或其合金),从而比HTCC的互连层具有更快的速度。
另一方面,单个器件层110中的无源元件110x、110y为共烧,即它们在单一烧制步骤中一体化烧制。在共烧前,这些无源元件所需的陶瓷胶带层(ceramic tape,也被称为green tape)160a-160e和电极材料层120a-120d预先形成在陶瓷基板180上的预定位置。在共烧后,陶瓷胶带层160a-160e和电极材料层120a-120d在预定位置形成无源元件110x、110y。由于这些无源元件110x、110y固定在陶瓷基板180上,位置相对固定,故它们后期可以整体安装到模组上。由于不需要单独安装无源元件,可以减少无源元件的安装时间和安装成本。在单个器件层110中,共烧的MLCC电容集群110x、110y含有具有相同高介电常数的介质材料160x、160y;此外,这些介质材料160x、160y具有相同的厚度Dx1、Dx2,其上表面160xt、160yt和下表面160xb、160yb分别是共面的。
图5披露了第二多模三维模组1000。在该实施例中,器件层110、210的第一和第二陶瓷基板180、280被保留在子模组100、200中。第一和第二陶瓷基板180、280可以防止器件层110、210在烧结时的变形,以固定每个陶瓷基板(如180)上各个电容110x、110y的相对位置。
图6披露了第三多模三维模组1000。在该实施例中,第二子模组200被翻转并且面对面地与第一子模组100接触。凸块bump(如微凸块micro-bump)290为第一和第二子模组100、200之间提供层间连接。
为了增加每个器件层110中MLCC电容110x、110y的电容范围(即最大和最小电容值之间的电容比),除了改变电容的物理尺寸外,还可以改变电容的内部电极数量。例如,具有最大电容值的MLCC电容110x可以含有全套内部电极120a-120d,即其内部电极120a-120d的数量是其陶瓷体160x最多允许的内部电极数量。另一方面,具有最小电容值的MLCC电容110y不含有全套内部电极,即其内部电极的数量小于其陶瓷体160y最多允许的内部电极数量。从另一个角度看,陶瓷体包括有效部分和无效部分:有效部分的陶瓷材料含有内电极;无效部分的陶瓷材料并不含内部电极。
图7A-图7B披露了一器件层110,其上有两个电容值相差极大的电容110x、110y`(图7A)。尽管大电容110x包含全套内部电极,但小电容110y'不含全套内部电极(图7B)。相比之下,图2中的两个电容110x,110y都包括全套内部电极。
在该实施例中,小电容110y'的陶瓷体160y包括两个有效部分160y1、160y3和一个无效部分160y2。有效部分160y1、160y3均含有两个内部电极120y、130y,因此起到电容的作用。无效部分160y2不含内部电极,因此不起电容的作用。无效部分160y2的厚度Td至少是相邻内部电极120y、130y之间间隔Se的两倍。
图8A-8B披露了另一器件层110,其上有两个电容值相差极大的电容110x、110y``(图8A)。在该实施例中,小电容110y``的陶瓷体160y包含有效部分160y1和无效部分160y4。有效部分160y1含有两个内部电极120y、130y,因此起到电容的作用。无效部分160y4不含内部电极,因此不起电容的作用。无效部分160y4的厚度Td大于有效部分160y1的厚度Tc。
应该了解,在不远离本发明的精神和范围的前提下,可以对本发明的形式和细节进行改动,这并不妨碍它们应用本发明的精神。例如说,模组可以是印刷电路板或封装的一部分。此外,模组中的电阻集群或电感集群也可以一体化。因此,除了根据附加的权利要求书的精神,本发明不应受到任何限制。
Claims (3)
1.一种多层陶瓷电容MLCC,包括位于同一基板(180)上的第一MLCC(110y`)和第二MLCC(110x),其特征在于:
所述第一MLCC(110y`)含有第一陶瓷体(160y)、第一对外部电极(140y,150y)、多个第一内部电极(120y,130y),所述第一内部电极(120y,130y)以第一交错的方式从所述第一对外部电极(140y,150y)延伸到所述第一陶瓷体(160y)内部;其中,所述第一陶瓷体(160y)包括至少一有效部分(160y1)和至少一无效部分(160y2),所述有效部分(160y1)含有至少部分所述第一内部电极(120y,130y),所述无效部分(160y2)不含任何所述第一内部电极;
所述第二MLCC(110x)含有第二陶瓷体(160x)、第二对外部电极(140x,150x)、多个第二内部电极(120x,130x),所述第二内部电极(120x,130x)以第二交错的方式从所述第二对外部电极(140x,150x)延伸到所述第二陶瓷体(160x)内部;其中,所述第二陶瓷体(160x)不含无效部分;
所述第一和第二陶瓷体(160y,160x)含有相同陶瓷材料,所述第一MLCC(110y`)的电容值小于所述第二MLCC(110x)。
2.一种多层陶瓷电容MLCC,包括位于同一基板(180)上的第一MLCC(110y`)和第二MLCC(110x),其特征在于:
所述第一MLCC(110y`)含有第一陶瓷体(160y)、第一对外部电极(140y,150y)、多个第一内部电极(120y,130y),所述第一内部电极(120y,130y)以第一交错的方式从所述第一对外部电极(140y,150y)延伸到所述第一陶瓷体(160y)内部;其中,所述第一陶瓷体(160y)包括至少一有效部分(160y1)和至少一无效部分(160y2),所述有效部分(160y1)含有至少部分所述第一内部电极(120y,130y),所述无效部分(160y2)不含任何所述第一内部电极;
所述第二MLCC(110x)含有第二陶瓷体(160x)、第二对外部电极(140x,150x)、多个第二内部电极(120x,130x),所述第二内部电极(120x,130x)以第二交错的方式从所述第二对外部电极(140x,150x)延伸到所述第二陶瓷体(160x)内部;其中,所述第二陶瓷体(160x)不含无效部分;
所述第一和第二陶瓷体(160y,160x)含有相同陶瓷材料,所述第一MLCC(110y`)的电容值小于所述第二MLCC(110x);
所述第一陶瓷体(160y)的所述第一内部电极(120y,130y)中的每个第一内部电极与所述第二陶瓷体(160x)的所述第二内部电极(120x,130x)中的一个第二内部电极在同一平面。
3.根据权利要求1或2所述的MLCC,其特征还在于:所述有效部分(160y1)比所述无效部分(160y2)更接近所述基板(180)。
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