CN110320962B - Reference circuit and integrated circuit - Google Patents
Reference circuit and integrated circuit Download PDFInfo
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- CN110320962B CN110320962B CN201910620247.6A CN201910620247A CN110320962B CN 110320962 B CN110320962 B CN 110320962B CN 201910620247 A CN201910620247 A CN 201910620247A CN 110320962 B CN110320962 B CN 110320962B
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- 239000000758 substrate Substances 0.000 claims description 3
- 238000005265 energy consumption Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
- G05F3/262—Current mirrors using field-effect transistors only
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Control Of Electrical Variables (AREA)
- Logic Circuits (AREA)
Abstract
A reference circuit comprising: the power supply end of the mirror circuit is used for being connected with a power supply, the input end of the mirror circuit is connected with bias current, and the output ends of the mirror circuit respectively output reference current; and a bias circuit including a first transistor and a first load that are turned on near zero or negative voltage, the bias circuit being self-conducting to form the bias current at an input of the mirror circuit. By means of the characteristic that the threshold voltage of the first transistor is close to zero or negative, the bias current can be formed at the input end of the mirror circuit by self-conduction, the mirror circuit replicates according to the bias current and generates the reference current, the reference circuit is simple in structure, a starting circuit is not needed, energy consumption is low, and the generated reference current is irrelevant to the power supply voltage.
Description
Technical Field
The application belongs to the technical field of CMOS integrated circuit design, and particularly relates to a reference circuit and an integrated circuit.
Background
Analog circuits broadly include a reference current and a reference voltage. For example, the bias current of a differential pair must be generated from the reference current because it affects the voltage gain and noise of the circuit. In systems like analog to digital converters and digital to analog converters, a reference voltage is also required to determine the full range of its input or output. The purpose of the reference is to establish a constant current or voltage.
The traditional reference circuit generally comprises a self-bias current mirror, a resistor and a starting circuit, and has a degenerate bias point irrelevant to a power supply, and can be stabilized in a zero working state that each tube is turned off or in a normal working state under the condition of adding power supply voltage. Since the circuit can be stabilized in either of the two operating states, a starting circuit is required to generate a starting voltage to get rid of the zero operating state where each tube is turned off, so that the circuit structure is more complex, and the starting circuit also brings additional power consumption.
Disclosure of Invention
The purpose of the application is to provide a reference circuit and an integrated circuit, and aims to solve the problems that a circuit structure is complex and power consumption is high due to the fact that a starting circuit is needed in a traditional reference circuit.
A first aspect of an embodiment of the present application provides a reference circuit, comprising:
the power supply terminal is used for being connected with a power supply;
a common potential terminal for connecting a common potential;
the power end of the mirror circuit is connected with the power terminal, the input end of the mirror circuit is connected with the bias current, and the mirror circuit mirrors the bias current to output reference currents at the output ends respectively;
the bias circuit comprises a first transistor and a first load, wherein the first transistor is conducted near zero voltage or negative voltage, a first conducting end of the first transistor is connected with an input end of the mirror circuit, a second conducting end of the first transistor is connected with a first end of the first load, a second end of the first load, a grid electrode of the first transistor and a substrate of the transistor are connected with a common potential terminal, and the bias circuit can conduct automatically to form the bias current at the input end of the mirror circuit.
In one embodiment, the first transistor is a Native NMOS transistor, a drain of the Native NMOS transistor is used as the first conducting terminal, and a source of the Native NMOS transistor is used as the second conducting terminal.
In one embodiment, the mirror circuit includes a second transistor and a third transistor with the same attribute, a first conductive terminal of the second transistor and a first conductive terminal of the third transistor are used as a power supply terminal of the mirror circuit, a second conductive terminal of the second transistor is used as an input terminal of the mirror circuit, a second conductive terminal of the third transistor is used as an output terminal of the mirror circuit, and a gate of the second transistor and a gate of the third transistor are commonly connected with the second conductive terminal of the second transistor.
In one embodiment, the second transistor and the third transistor are PMOS transistors, a source of the PMOS transistor is used as the first conducting terminal, and a drain of the PMOS transistor is used as the second conducting terminal.
In one embodiment, the circuit further comprises a second load connected between the output end of the mirror circuit and the common potential terminal, and the output end of the mirror circuit outputs a reference voltage.
In one embodiment, the second load comprises a fourth transistor, which is connected in a diode-connected manner between the output of the mirror circuit and a common potential terminal.
In one embodiment, the second load further includes a fifth transistor having a different attribute than the fourth transistor, the fifth transistor being diode-connected between the fourth transistor and the output of the mirror circuit.
In one embodiment, the fourth transistor is an NMOS transistor.
In one embodiment, the fifth transistor is a PMOS transistor.
A second aspect of embodiments of the present application provides an integrated circuit comprising the above reference circuit.
The reference circuit enables self-conduction to form the bias current at the input end of the mirror circuit by means of the characteristic that the threshold voltage of the first transistor is close to zero or negative, and the mirror circuit replicates and generates the reference current according to the bias current.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required for the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic circuit diagram of a reference circuit according to an embodiment of the present disclosure;
FIG. 2 is an exemplary schematic circuit diagram of a reference circuit providing a reference current provided by a first embodiment of the present application;
FIG. 3 is a schematic diagram of an exemplary circuit for providing a reference voltage to a reference circuit provided in a second embodiment of the present application;
fig. 4 is a schematic diagram of an exemplary circuit for providing a reference voltage by a reference circuit according to a third embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
Fig. 1 shows that a reference circuit, which may be integrated in an integrated circuit, preferably includes a power supply terminal VCC, a common potential terminal VSS, a mirror circuit 100, and a bias circuit 200. The power supply terminal VCC is for switching on a power supply, and the common potential terminal VSS is for connecting a common potential such as the ground. The power supply terminal of the mirror circuit 100 is connected to the power supply terminal VCC, the input terminal of the mirror circuit 100 is connected to the bias current Iq, and the mirror circuit 100 mirrors the bias current Iq to output the reference current I/u at the output terminal REF The method comprises the steps of carrying out a first treatment on the surface of the The bias circuit 200 includes a first transistor 201 and a first load 202 that are turned on near zero voltage or negative voltage, a first conductive terminal of the first transistor 201 is connected to an input terminal of the mirror circuit 100, a second conductive terminal of the first transistor 201 is connected to a first terminal of the first load 202, a second terminal of the first load 202, a gate of the first transistor 201, and a substrate of the transistor are connected to a common potential terminal VSS, and the bias circuit 200 is capable of self-turn on to form a bias current Iq at the input terminal of the mirror circuit 100. Therefore, under the condition that the power VCC is added to the reference circuit, the reference circuit can only be stabilized in a normal working state, and the reference circuit has no degenerate bias point, does not need a starting circuit and has low energy consumption.
In one embodiment, the first transistor 201 is a Native NMOS transistor NB0, and the drain of the Native NMOS transistor NB0 is used as the first transistor 201A source of the Native NMOS transistor NB0 is used as a second conduction terminal of the first transistor 201, and a threshold voltage VT of the Native NMOS transistor NB0 Native NMOS The reference circuit is connected with a power supply to be directly conducted when the positive voltage or the negative voltage is close to zero, and the starting circuit is not needed to drive. In other embodiments, the first transistor 201 may be other self-turn-on devices. The first load 202 may be an active impedance or a passive impedance, and in this example, the passive impedance resistor RB0 is used as an example. In other embodiments, the first load 202 may be at least one of a resistor, a capacitor, an inductor, a transistor, and the like.
In one embodiment, the mirror circuit 100 includes a second transistor 101 and a third transistor 102 of the same property, the first conductive terminal of the second transistor 101 and the first conductive terminal of the third transistor 102 are used as the power source terminal of the mirror circuit 100, the second conductive terminal of the second transistor 101 is used as the input terminal of the mirror circuit 100, the second conductive terminal of the third transistor 102 is used as the output terminal of the mirror circuit 100, and the gate of the second transistor 101 and the gate of the third transistor 102 are commonly connected with the second conductive terminal of the second transistor 101. For example, the second transistor 101 and the third transistor 102 constitute a bipolar basic current mirror, a MOS transistor basic current mirror, or a cascode current mirror.
Referring to fig. 2, in one embodiment, the second transistor 101 and the third transistor 102 are PMOS transistors PB0 and PB1, the sources of the PMOS transistors PB0 and PB1 are used as the first conducting terminal, and the drains of the PMOS transistors PB0 and PB1 are used as the second conducting terminal.
The reference circuit acts on the resistor RB0 through the source end of the Native NMOS tube NB0 with the grounded gate, and utilizes the threshold voltage VT of the Native NMOS tube NB0 Native NMOS The near zero or negative characteristic produces a bias current Iq. Generating different reference currents I/u through the mirror image bias current Iq of the PMOS tube PB1 REF ，I_ REF =n×iq (n=1, 2,3 …), specifically, bias current Iq and reference current I/u REF The formulas of (a) are as follows:
referring to fig. 3, the reference circuit further includes a second load 302, the second load 302 is connected between the output terminal of the mirror circuit 100 and the common potential terminal VSS, and the output terminal of the mirror circuit 100 outputs the reference voltage V REF . The first load 202 may be an active impedance or a passive impedance.
In this example, the second load 302 is an active resistor, and includes a fourth transistor, which is connected between the output terminal of the mirror circuit 100 and the common potential terminal VSS in a diode connection manner. Specifically, the first conductive terminal and the gate of the fourth transistor are connected to the output terminal of the mirror circuit 100, and the second conductive terminal of the fourth transistor is connected to the common potential terminal VSS. For example, the fourth transistor is an NMOS transistor NB1, the drain of the NMOS transistor NB1 is the first conductive terminal of the fourth transistor, and the source of the NMOS transistor NB1 is the second conductive terminal of the fourth transistor. In other embodiments, the second load 302 may be at least one of a resistor, a capacitor, an inductor, other forms of transistors, and the like.
Taking the second load 302 as an NMOS transistor as an example, the mirror bias current n×iq (n=1, 2,3, …) passing through the PMOS transistor PB2 acts on the diode-connected NMOS transistor NB1 to generate the reference voltage V REF The calculation formula is as follows:
wherein KP NB1 The device process parameters of the NMOS tube NB 1;the device width-to-length ratio of the NMOS tube NB 1; VT (VT) NB1 Device threshold voltage of NMOS tube NB 1.
In another embodiment, referring to FIG. 4, the second load 302 further includes a fourth transistor having a different propertyFive transistors, the fifth transistor is connected in a diode connection between the fourth transistor and the output terminal of the mirror circuit 101. Even if the second load 302 includes two transistors with different properties, as described above, the fourth transistor is the NMOS transistor NB1, and then the fifth transistor should be the PMOS transistor PB3, where the gate and the drain of the PMOS transistor PB3 and the gate and the drain of the NMOS transistor NB1 are commonly connected, and the source of the PMOS transistor PB3 is connected to the output terminal of the mirror circuit 101. In this example, reference voltage V REF The calculation formula of (2) is as follows:
wherein KP PB3 The device process parameters of the PMOS tube PB 3;the width-to-length ratio of the device of the PMOS tube PB 3; VT (VT) PB3 The threshold voltage of the device of the PMOS tube PB 3.
The reference circuit is characterized in that the threshold voltage of the first transistor 201 is close to zero or negative, so that the reference circuit can be self-conducted to form the bias current Iq at the input end of the mirror circuit 100, and the mirror circuit 100 replicates and generates the reference current according to the bias current Iq. As can be seen from the above formulas, the reference current and the reference voltage generated by the reference circuit are independent of the power supply voltage.
The foregoing description of the preferred embodiments of the present application is not intended to be limiting, but is intended to cover any and all modifications, equivalents, and alternatives falling within the spirit and principles of the present application.
Claims (8)
1. A reference circuit, comprising:
the power supply terminal is used for being connected with a power supply;
a common potential terminal for connecting a common potential;
the power end of the mirror circuit is connected with the power terminal, the input end of the mirror circuit is connected with the bias current, and the mirror circuit mirrors the bias current to output a reference current at the output end;
the bias circuit comprises a first transistor and a first load, wherein the first transistor is conducted near zero voltage or negative voltage, a first conducting end of the first transistor is connected with an input end of the mirror circuit, a second conducting end of the first transistor is connected with a first end of the first load, a second end of the first load, a grid electrode of the first transistor and a substrate of the transistor are connected with a common potential terminal, and the bias circuit can conduct automatically to form the bias current at the input end of the mirror circuit;
the first transistor is a Native NMOS transistor, a drain electrode of the Native NMOS transistor is used as the first conducting end, and a source electrode of the Native NMOS transistor is used as the second conducting end;
the mirror circuit comprises a second transistor and a third transistor which are identical in property, a first conducting end of the second transistor and a first conducting end of the third transistor are used as power supply ends of the mirror circuit, a second conducting end of the second transistor is used as an input end of the mirror circuit, a second conducting end of the third transistor is used as an output end of the mirror circuit, and a grid electrode of the second transistor and a grid electrode of the third transistor are connected with a second conducting end of the second transistor in a sharing mode.
2. The reference circuit of claim 1, wherein the second transistor and the third transistor are PMOS transistors, a source of the PMOS transistor being the first pass terminal, and a drain of the PMOS transistor being the second pass terminal.
3. The reference circuit according to claim 1 or 2, further comprising a second load connected between an output of the mirror circuit and a common potential terminal, the output of the mirror circuit outputting a reference voltage.
4. A reference circuit as claimed in claim 3, wherein the second load comprises a fourth transistor connected in a diode connection between the output of the mirror circuit and a common potential terminal.
5. The reference circuit of claim 4 wherein the second load further comprises a fifth transistor having a different attribute than the fourth transistor, the fifth transistor being diode connected between the fourth transistor and the output of the mirror circuit.
6. The reference circuit of claim 4 wherein said fourth transistor is an NMOS transistor.
7. The reference circuit of claim 5 wherein the fifth transistor is a PMOS transistor.
8. An integrated circuit comprising the reference circuit of any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910620247.6A CN110320962B (en) | 2019-07-10 | 2019-07-10 | Reference circuit and integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910620247.6A CN110320962B (en) | 2019-07-10 | 2019-07-10 | Reference circuit and integrated circuit |
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| CN110320962A CN110320962A (en) | 2019-10-11 |
| CN110320962B true CN110320962B (en) | 2024-02-09 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000001595A (en) * | 1998-06-12 | 2000-01-15 | 김영환 | Negative voltage reset circuit |
| CN101071978A (en) * | 2006-05-09 | 2007-11-14 | 罗姆股份有限公司 | Start-up circuit and start-up method |
| JP2015065735A (en) * | 2013-09-24 | 2015-04-09 | ルネサスエレクトロニクス株式会社 | Soft-start circuit and semiconductor device including the same |
| CN210534616U (en) * | 2019-07-10 | 2020-05-15 | 深圳市锐能微科技有限公司 | Reference circuit and integrated circuit |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8415928B2 (en) * | 2006-06-30 | 2013-04-09 | System General Corp. | Power circuit |
| JP6212225B2 (en) * | 2013-12-05 | 2017-10-11 | テキサス インスツルメンツ インコーポレイテッド | Power converter soft start circuit |
| CN105807834B (en) * | 2014-12-29 | 2018-05-08 | 意法半导体(中国)投资有限公司 | Inputted with the N-channel of soft start and current limit circuit to voltage regulator |
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2019
- 2019-07-10 CN CN201910620247.6A patent/CN110320962B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000001595A (en) * | 1998-06-12 | 2000-01-15 | 김영환 | Negative voltage reset circuit |
| CN101071978A (en) * | 2006-05-09 | 2007-11-14 | 罗姆股份有限公司 | Start-up circuit and start-up method |
| JP2015065735A (en) * | 2013-09-24 | 2015-04-09 | ルネサスエレクトロニクス株式会社 | Soft-start circuit and semiconductor device including the same |
| CN210534616U (en) * | 2019-07-10 | 2020-05-15 | 深圳市锐能微科技有限公司 | Reference circuit and integrated circuit |
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| CN110320962A (en) | 2019-10-11 |
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