CN110310944B - High-power semiconductor device with failure open circuit characteristic - Google Patents
High-power semiconductor device with failure open circuit characteristic Download PDFInfo
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- CN110310944B CN110310944B CN201910714323.XA CN201910714323A CN110310944B CN 110310944 B CN110310944 B CN 110310944B CN 201910714323 A CN201910714323 A CN 201910714323A CN 110310944 B CN110310944 B CN 110310944B
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- semiconductor device
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- power semiconductor
- welding material
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000003466 welding Methods 0.000 claims abstract description 41
- 239000000463 material Substances 0.000 claims abstract description 34
- 229910045601 alloy Inorganic materials 0.000 claims description 23
- 239000000956 alloy Substances 0.000 claims description 23
- 229910000679 solder Inorganic materials 0.000 claims description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 230000004907 flux Effects 0.000 claims 1
- 230000008018 melting Effects 0.000 abstract description 3
- 238000002844 melting Methods 0.000 abstract description 3
- 239000000155 melt Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 15
- 238000002788 crimping Methods 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 206010033799 Paralysis Diseases 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/62—Protection against overvoltage, e.g. fuses, shunts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thyristors (AREA)
- Die Bonding (AREA)
Abstract
The invention relates to the technical field of power electronic devices, and discloses a high-power semiconductor device with a failure open circuit characteristic. When the high-power semiconductor device is in failure or failure induced by failure, the temperature of the device can be increased rapidly, and when the temperature is increased to the melting point of the preset columnar low-temperature conductive welding material, the welding material melts and fills the air gap to cause the open circuit between the cathode inner lead and the chip, so that the device is in failure or open circuit before failure, and the driving circuit of the device is protected.
Description
Technical Field
The invention relates to the technical field of power electronic devices, in particular to a high-power semiconductor device with a failure open circuit characteristic.
Background
The power semiconductor device is also called as a power electronic device and is mainly used as a high-power electronic device in the aspect of electric energy conversion and control circuits of power equipment, and the power device comprises a power diode, a thyristor, a GTR, a GTO, a power MOSFET, an IGBT and the like.
In practical applications, if a load short-circuit fault occurs, excessive current will flow through the power device chip until the overheat fails, which is one of the common failure modes of the power semiconductor device. The final failure phenomenon is short-circuit failure, so that the drive load is damaged (such as a motor is burnt out), the power grid system is paralyzed, and even serious problems such as electric fire are caused.
Therefore, it is desirable to be able to shut off the current flowing through the device when it becomes too hot and before the device fails. However, to limit costs, it is desirable to implement such a circuit with as few additional components as possible.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides the high-power semiconductor device with the failure open-circuit characteristic, the device is opened by heat generated in the failure process, and the device is ensured to have the advantages of high reliability and good safety, and the dangerous situations of short-circuit failure mode, burst and the like are avoided.
In order to achieve the above purpose, the present invention provides the following technical solutions: the utility model provides a high-power semiconductor device with inefficacy open circuit characteristic, includes three terminal high-power chip, positive pole outer lead, negative pole outer lead and control utmost point outer lead to and negative pole inner lead, control utmost point inner lead, insulating liner, low Wen Zhuzhuang conductive welding material and insulating liner and the air gap between the column conductive welding material, insulating liner prefabricates on negative pole inner lead, positive pole outer lead links to each other with the positive pole of three terminal high-power chip, the negative pole of three terminal high-power chip links to each other with the insulating liner and the low temperature column conductive welding material of negative pole inner lead, the leading-out terminal of negative pole inner lead links to each other with the negative pole outer lead, the one end of control utmost point inner lead links to each other with the control utmost point of three terminal high-power chip, and the other end links to each other with the control utmost point outer lead.
Preferably, the insulating liner is alumina or aluminum nitride or other high temperature resistant insulating material.
Preferably, the minimum thickness of the insulating pad is 1.5mm, and a sufficient creepage distance is ensured after the low-temperature columnar conductive welding material is melted.
Preferably, the low Wen Zhuzhuang conductive welding material is selected by combining the following conditions when selecting a specific solder alloy;
(A) The highest working junction temperature of the high-power semiconductor device;
(B) Solidus temperature of the solder alloy;
(C) The liquidus temperature of the solder alloy;
(D) The solidus temperature of the solder alloy is higher than the normal working temperature of the high-power semiconductor device;
(E) The liquidus temperature of the solder alloy is below the maximum operating junction temperature of the high power semiconductor device.
Preferably, the low Wen Zhuzhuang conductive welding material is a low-temperature alloy, the alloy composition is determined according to the junction temperature of the device, and the silicon device with the junction temperature of 125 ℃ is preferably In52Sn48 low-temperature eutectic welding material.
Preferably, the shape of the low Wen Zhuzhuang conductive solder can be cylindrical, oval, square, etc.
Preferably, the air gap should ensure that the distance between the highest point of the solder and the lowest point of the lead in the cathode should meet the creepage distance of the working voltage of the device after the low-temperature columnar conductive welding material is melted, and the distance should be no less than 1.1mm under the power supply condition that the application voltage is 380V and 50 HZ.
The invention provides a high-power semiconductor device with failure open circuit characteristics, which has the beneficial effects that:
1. when the load short circuit failure or PN junction degradation failure process of the device does not occur, and when the energy of the current flowing through the device reaches the preset melting temperature of the columnar low-temperature welding material, the columnar low Wen Hancai is melted, the molten solder fills the air gap between the pad and the columnar low-temperature welding material, so that the columnar low-temperature welding material is separated from the cathode inner lead to cause the cathode inner lead to be open-circuited with the cathode of the three-terminal high-power chip, and therefore, the failure mode of the high-power semiconductor device is always open-circuited, and the dangerous situations of short circuit failure mode or burst and the like of the traditional high-power semiconductor device are effectively avoided;
2. compared with the common prior high-power semiconductor device, the high-power semiconductor device with the failure open circuit characteristic can not increase the circuit volume and the number of circuit elements while improving the reliability, and has strong practicability and high safety.
Drawings
FIG. 1 is a schematic diagram of the structure of the present invention;
FIG. 2 is a schematic diagram of a failed open circuit condition of the present invention;
FIG. 3 is a top view of a prefabricated cathode lead according to the present invention;
fig. 4 is a left side view of a prefabricated cathode lead according to the present invention.
In the figure: 1. three-terminal high-power chip, 2, anode outer lead, 3, cathode outer lead, 4, control electrode outer lead, 5, cathode inner lead, 6, an insulating liner, 7, a low Wen Zhuzhuang conductive welding material, 8, an air gap, 9 and a control electrode inner lead.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1-4, the present invention provides a technical solution: the high-power semiconductor device with the failure open circuit characteristic comprises a three-terminal high-power chip 1, an anode outer lead 2, a cathode outer lead 3, a control electrode outer lead 4, a cathode inner lead 5, a control electrode inner lead 9, an insulating gasket 6, a low Wen Zhuzhuang conductive welding material 7 and an air gap 8 between the insulating gasket 6 and a columnar conductive welding material 7, wherein the insulating gasket 6 is prefabricated on the cathode inner lead 5;
the anode outer lead 2 is connected with the anode of the three-terminal high-power chip 1, and the process method can be used for crimping or welding;
the cathode of the three-terminal high-power chip 1 is connected with an insulating liner 6 of an inner lead of the cathode and a low-temperature columnar conductive welding material 7, and the technological method can be used for crimping or welding;
the leading-out end of the cathode inner lead 3 is connected with the cathode outer lead 4, and the process method can be crimping or welding;
one end of the inner lead 9 of the control electrode is connected with the control electrode of the three-terminal high-power chip 1, and the other end of the inner lead is connected with the outer lead 4 of the control electrode, and the process method can be used for crimping or welding.
In this embodiment, the power semiconductor chip adopts a three-terminal high-power chip (including SCR, TRACS, power MOSFET, IGBT, power transistor, GTR, GTO, etc.), and the power semiconductor device may also adopt a two-terminal high-power device (including power diode, TVS, TSS, MOV, etc.);
at the moment, the anode outer lead is connected with the anode of the double-end high-power chip, and the process method can be used for crimping or welding;
the cathode of the double-end high-power chip is connected with the insulating liner 6 of the cathode inner lead 5 and the low-temperature columnar conductive welding material 7, and the process method can be used for crimping or welding;
the leading-out end of the cathode inner lead 3 is connected with the cathode outer lead 4, and the process method can be crimping or welding;
in this embodiment, the low Wen Zhuzhuang conductive solder material 7 is a low melting point and low specific heat capacity solder alloy, and the solder alloy is selected by combining the following conditions
(A) The highest working junction temperature of the high-power semiconductor device;
(B) Solidus temperature of the solder alloy;
(C) The liquidus temperature of the solder alloy;
the solidus temperature of the solder alloy is higher than the normal working temperature of the high-power semiconductor device;
the liquidus temperature of the solder alloy is below the maximum operating junction temperature of the high power semiconductor device.
When the embodiment is implemented, when the high-power semiconductor device is in a normal working state, the working temperature of the high-power semiconductor device is lower than the solidus temperature of the solder alloy, at the moment, the temperature of the low Wen Zhuzhuang conductive welding material 7 is lower than the solidus temperature, the low Wen Zhuzhuang conductive welding material is connected with the cathode inner lead 3 and the cathode of the high-power semiconductor chip 1, the cathode outer lead 3 of the device and the anode outer lead 2 of the high-power semiconductor chip 1 are in a passage state, and the high-power semiconductor device is in a normal working state.
When the embodiment is implemented, when the high-power semiconductor device is in a working state of fault short circuit or PN junction degradation failure, the high-power semiconductor device rapidly gathers and heats, the junction temperature of the high-power semiconductor device is higher than the liquidus temperature of the solder alloy, the temperature of the low-Wen Zhuzhuang conductive welding material 7 is higher than the liquidus temperature of the solder alloy, meanwhile, the low-Wen Zhuzhuang conductive welding material 7 is converted into a liquid phase from a solid phase, the low-temperature conductive welding material 7 is influenced by liquid tension and gravity, an air gap 8 between the insulating pads 6 is filled, the low-temperature conductive welding material is disconnected with the cathode inner lead 3, the creepage distance between the highest point of the low-temperature welding material and the lowest point distance 10 of the cathode inner lead is ensured to meet the working voltage of the device, and the creepage distance is ensured to be not less than 1.1mm under 380V and 50HZ working power sources of the device.
In summary, compared with the common existing high-power semiconductor device, the high-power semiconductor device provided in this embodiment can automatically switch to an open circuit state in a fault operation state, rather than a short circuit state common to the existing high-power semiconductor device, thereby protecting loads and power sources, improving reliability without increasing circuit volume and increasing the number of circuit elements, and has strong practicability and high safety.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (6)
1. A high power semiconductor device having an open-circuit failure feature, characterized by: the three-terminal high-power chip comprises a three-terminal high-power chip (1), an anode outer lead (2), a cathode outer lead (3) and a control electrode outer lead (4), as well as a cathode inner lead (5), a control electrode inner lead (9), an insulating gasket (6), a low Wen Zhuzhuang conductive welding material (7) and an air gap (8) between the insulating gasket (6) and a columnar conductive welding material (7), wherein the insulating gasket (6) is prefabricated on the cathode inner lead (5), the anode outer lead (2) is connected with the anode of the three-terminal high-power chip (1), the cathode of the three-terminal high-power chip (1) is connected with the insulating gasket (6) of the cathode inner lead and the low-temperature columnar conductive welding material (7), the leading-out end of the cathode inner lead (3) is connected with the cathode outer lead (4), one end of the control electrode inner lead (9) is connected with the control electrode of the three-terminal high-power chip (1), and the other end of the control electrode inner lead is connected with the control electrode outer lead (4);
the low Wen Zhuzhuang conductive welding material (7) needs to be selected by combining the following conditions when selecting a specific solder alloy;
(A) The highest working junction temperature of the high-power semiconductor device;
(B) Solidus temperature of the solder alloy;
(C) The liquidus temperature of the solder alloy;
(D) The solidus temperature of the solder alloy is higher than the normal working temperature of the high-power semiconductor device;
(E) The liquidus temperature of the solder alloy is below the maximum operating junction temperature of the high power semiconductor device.
2. A high power semiconductor device having an open-circuit-disabled feature as in claim 1, wherein: the insulating liner (6) is alumina or aluminum nitride.
3. A high power semiconductor device having an open-circuit-disabled feature as in claim 2, wherein: the minimum thickness of the insulating liner (6) is 1.5mm, and a sufficient creepage distance is ensured after the low-temperature columnar conductive welding material (5) is melted.
4. A high power semiconductor device having an open-circuit-disabled feature as in claim 3, wherein: the low Wen Zhuzhuang conductive welding material (7) is a low-temperature alloy, the alloy composition is determined according to the junction temperature of the device, and the junction temperature is 125 ℃ of the silicon device.
5. A high power semiconductor device having an open-circuit-disabled feature as in claim 4, wherein: the low Wen Zhuzhuang conductive welding material (7) is cylindrical, elliptic or square in shape.
6. A high power semiconductor device having an open-circuit-disabled feature as in claim 5, wherein: after the low-temperature columnar conductive welding material (7) is melted, the distance between the highest point of the welding flux and the lowest point of the cathode inner lead (5) is required to meet the creepage distance of the working voltage of the device, and the creepage distance is required to be not less than 1.1mm under the power supply condition that the application voltage is 380V and 50 HZ.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910714323.XA CN110310944B (en) | 2019-08-03 | 2019-08-03 | High-power semiconductor device with failure open circuit characteristic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910714323.XA CN110310944B (en) | 2019-08-03 | 2019-08-03 | High-power semiconductor device with failure open circuit characteristic |
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| Publication Number | Publication Date |
|---|---|
| CN110310944A CN110310944A (en) | 2019-10-08 |
| CN110310944B true CN110310944B (en) | 2024-04-09 |
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| CN201910714323.XA Active CN110310944B (en) | 2019-08-03 | 2019-08-03 | High-power semiconductor device with failure open circuit characteristic |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112992834B (en) * | 2021-02-09 | 2022-02-18 | 捷捷微电(上海)科技有限公司 | Advanced diode packaging structure with indirect electrical connection of source and grid |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108336059A (en) * | 2016-12-30 | 2018-07-27 | 德州仪器公司 | Method and apparatus for ic failure protection fuse encapsulation |
| CN210349831U (en) * | 2019-08-03 | 2020-04-17 | 捷捷半导体有限公司 | High-power semiconductor device with failure open circuit characteristic |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7999363B2 (en) * | 2007-01-25 | 2011-08-16 | Alpha & Omega Semiconductor, Ltd | Structure and method for self protection of power device |
| US9082737B2 (en) * | 2012-11-15 | 2015-07-14 | Infineon Technologies Ag | System and method for an electronic package with a fail-open mechanism |
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- 2019-08-03 CN CN201910714323.XA patent/CN110310944B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108336059A (en) * | 2016-12-30 | 2018-07-27 | 德州仪器公司 | Method and apparatus for ic failure protection fuse encapsulation |
| CN210349831U (en) * | 2019-08-03 | 2020-04-17 | 捷捷半导体有限公司 | High-power semiconductor device with failure open circuit characteristic |
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| CN110310944A (en) | 2019-10-08 |
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