CN110299294A - 一种三维***级集成硅基扇出型封装方法及结构 - Google Patents

一种三维***级集成硅基扇出型封装方法及结构 Download PDF

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CN110299294A
CN110299294A CN201910703380.8A CN201910703380A CN110299294A CN 110299294 A CN110299294 A CN 110299294A CN 201910703380 A CN201910703380 A CN 201910703380A CN 110299294 A CN110299294 A CN 110299294A
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silicon substrate
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王成迁
明雪飞
吉勇
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CETC 58 Research Institute
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Abstract

本发明公开一种三维***级集成硅基扇出型封装方法及结构，属于三维***级集成电路封装技术领域。首先提供硅基，将其与玻璃载板键合；在所述硅基背面刻蚀出凹槽和TSV通孔，在TSV通孔中制作背面第一层重布线，在凹槽中埋入桥芯片；然后用干膜材料填充所述硅基和所述桥芯片间的空隙；在所述桥芯片的焊盘和所述背面第一层重布线的焊盘处开口并制作背面第二层重布线；接着将高密度I/O异质芯片通过微凸点与所述背面第二层重布线的焊盘焊接；塑封所述硅基背面，拆解所述玻璃载板并在所述TSV通孔处开口；制作正面重布线、阻焊层和凸点，切成单颗封装芯片，完成封装。

Description

一种三维***级集成硅基扇出型封装方法及结构
技术领域
本发明涉及集成电路封装技术领域，特别涉及一种三维***级集成硅基扇出型封装方法及结构。
背景技术
随着芯片制造水平的不断提高，产业界一直公认的“摩尔定律”走到尽头：一方面，晶圆制造工艺节点越往下发展制造成本以数倍甚至数百倍增加；另外一方面，“摩尔定律”终究会到达物理极限。那么“摩尔定律（Moore Law）”终结之后芯片器件性能如何提升已经成为近年来讨论的热点。
2016年苹果公司推出iPhone 7，其A10处理器所采用的InFO晶圆级封装技术惊艳全球，自此各个封装厂甚至晶圆厂将研发重点瞄准扇出型封装技术。同时，基于扇出型封装技术的三维异质集成，将不同制程和功能芯片集成到一起，能够大大提高产品性能，自此也进入到了“More Moore”时代。
InFO晶圆级封装采用塑封方式重构晶圆，这种封装往往翘曲大，使得流片难度增加，散热性也较差。申请号为201610098740.2的专利中使用硅基重构晶圆并扇出晶圆级封装，同时也实现了三维集成封装。但先重构晶圆后制作TSV盲孔，之后在正面临时键合背面利用化学机械抛光（CMP）技术露出TSV盲孔的铜柱，这种方式工艺复杂，并且化学机械抛光（CMP）是晶圆厂工艺，成本高昂。
发明内容
本发明的目的在于提供一种三维***级集成硅基扇出型封装方法及结构，以解决现有的晶圆封装方式复杂、成本高，且生产出的封装结构集成度和可靠性较差的问题。
为解决上述技术问题，本发明提供一种三维***级集成硅基扇出型封装方法，包括：
提供硅基，将其与玻璃载板键合；
在所述硅基背面刻蚀出凹槽和TSV通孔，在TSV通孔中制作背面第一层重布线，在凹槽中埋入桥芯片；
用干膜材料填充所述硅基和所述桥芯片间的空隙；
在所述桥芯片的焊盘和所述背面第一层重布线的焊盘处开口并制作背面第二层重布线；
将高密度I/O异质芯片通过微凸点与所述背面第二层重布线的焊盘焊接；
塑封所述硅基背面，拆解所述玻璃载板并在所述TSV通孔处开口；
制作正面重布线、阻焊层和凸点，切成单颗封装芯片，完成封装。
可选的，所述硅基正面沉积有截止层，所述截止层与所述玻璃载板键合。
可选的，所述玻璃载板包括键合玻璃和形成在所述键合玻璃上的临时键合激光反应层；所述临时键合激光反应层通过临时键合胶与所述截止层键合；其中，
所述键合玻璃的厚度不小于100μm；所述临时键合胶的厚度不小于1μm，所述临时键合激光反应层的厚度不小于0.1μm。
可选的，所述截止层的材质为无机材料的一种或多种，或金属材料的一种或多种，其厚度不小于0.1μm，
所述无机材料包括SiO2、SiC和SiN；
所述金属材料包括Al、Cu、Ni、Sn和Au。
可选的，在所述硅基背面刻蚀出凹槽和TSV通孔包括：
通过研磨或刻蚀的方法将所述硅基背面减薄到目标厚度；
使用干法刻蚀在减薄的硅基背面刻蚀凹槽和TSV通孔；其中，
所述凹槽大小根据埋入芯片尺寸决定，其深度至少为10μm；所述TSV通孔深度与所述凹槽一致，所述凹槽和所述TSV通孔数量均在一个以上。
可选的，所述桥芯片通过粘合胶埋入凹槽，所述凹槽中埋入一颗或多颗桥芯片；所述桥芯片的焊盘朝外，埋入桥芯片后所述桥芯片形成的高度与所述硅基平面的高度误差不超过5μm。
可选的，所述干膜材料为包括树脂类和聚酰亚胺类在内的聚合物材质。
可选的，通过塑封材料塑封所述硅基背面，所述塑封材料是包括树脂类和聚酰亚胺类在内的聚合物。
本发明还提供了一种三维***级集成硅基扇出型封装结构，通过上述的三维***级集成硅基扇出型封装方法制备而成。
在本发明中提供了一种三维***级集成硅基扇出型封装方法及结构，首先提供硅基，将其与玻璃载板键合；在所述硅基背面刻蚀出凹槽和TSV通孔，在TSV通孔中制作背面第一层重布线，在凹槽中埋入桥芯片；然后用干膜材料填充所述硅基和所述桥芯片间的空隙；在所述桥芯片的焊盘和所述背面第一层重布线的焊盘处开口并制作背面第二层重布线；接着将高密度I/O异质芯片通过微凸点与所述背面第二层重布线的焊盘焊接；塑封所述硅基背面，拆解所述玻璃载板并在所述TSV通孔处开口；制作正面重布线、阻焊层和凸点，切成单颗封装芯片，完成封装。
本发明提供的三维***级集成硅基扇出型封装方法及结构具有以下有益效果：
（1）将TSV通孔和凹槽同时在硅基上刻蚀出来，并引入桥芯片，实现高效率、高集成度、高性能和高可靠性三维***级封装集成；
（2）通过使用硅基和桥芯片扇出，硅基和TSV通孔同时完成，塑封和阻焊层将芯片六面包封，完成高密度I/O异质芯片三维集成，其封装效率、集成度、性能和可靠性高，适合大规模量产使用。
附图说明
图1是本发明提供的三维***级集成硅基扇出型封装方法流程示意图；
图2是在硅基正面沉积截止层的示意图；
图3是玻璃载板的示意图；
图4是将玻璃载板与硅基键合后示意图；
图5是硅基背面刻蚀后凹槽和TSV通孔示意图；
图6是在TSV通孔中制作背面第一层重布线和在凹槽中埋入桥芯片的示意图；
图7是填满干膜材料并开口的示意图；
图8是将高密度I/O异质芯片倒装焊接到硅基上示意图；
图9是塑封材料塑封硅基背面示意图；
图10拆解玻璃载板清洗临时键合胶后刻蚀出TSV通孔焊盘的示意图；
图11形成正面重布线示意图；
图12在硅基正面制作阻焊层和凸点并切割完成最终封装示意图。
具体实施方式
以下结合附图和具体实施例对本发明提出的一种三维***级集成硅基扇出型封装方法及结构作进一步详细说明。根据下面说明和权利要求书，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
实施例一
本发明提供了一种三维***级集成硅基扇出型封装方法，其流程如图1所示，包括如下步骤：
步骤S11、提供硅基，将其与玻璃载板键合；
步骤S12、在所述硅基背面刻蚀出凹槽和TSV通孔，在TSV通孔中制作背面第一层重布线，在凹槽中埋入桥芯片；
步骤S13、用干膜材料填充所述硅基和所述桥芯片间的空隙；
步骤S14、在所述桥芯片的焊盘和所述背面第一层重布线的焊盘处开口并制作背面第二层重布线；
步骤S15、将高密度I/O异质芯片通过微凸点与所述背面第二层重布线的焊盘焊接；
步骤S16、塑封所述硅基背面，拆解所述玻璃载板并在所述TSV通孔处开口；
步骤S17、制作正面重布线、阻焊层和凸点，切成单颗封装芯片，完成封装。
具体的，首先如图2所示，提供硅基101，所述硅基101正面沉积有截止层102。所述所述截止层102的材质为无机材料的一种或多种，或金属材料的一种或多种，其厚度不小于0.1μm；其中，所述无机材料包括SiO2、SiC和SiN；所述金属材料包括Al、Cu、Ni、Sn和Au。
提供如图3所示的玻璃载板，包括键合玻璃201和形成在所述键合玻璃201上的临时键合激光反应层202；优选的，所述键合玻璃201的厚度不小于100μm；所述临时键合胶203的厚度不小于1μm，所述临时键合激光反应层202的厚度不小于0.1μm。接着如图4，所述临时键合激光反应层202通过临时键合胶203与所述截止层102键合。
然后通过研磨或刻蚀的方法将所述硅基101背面减薄到目标厚度，再使用干法刻蚀在减薄的硅基背面刻蚀出TSV通孔103和凹槽104，请参阅图5，所述凹槽104和所述TSV通孔103刻蚀至所述截止层102。具体的，所述凹槽104的大小根据待埋入的芯片尺寸决定，其深度至少为10μm；所述TSV通孔103深度与所述凹槽104一致，所述凹槽104和所述TSV通孔103数量均在一个以上。
如图6，通过重布线技术在所述TSV通孔103中制作背面第一层重布线105，所述背面第一层重布线105实现所述TSV通孔103和所述硅基101背面互连。在所述凹槽103中通过粘合胶303埋入桥芯片301，所述桥芯片301的焊盘302朝外；请继续参阅图6，埋入桥芯片301后，所述桥芯片301和所述粘合胶303共同形成的高度与所述硅基101平面的高度误差不超过5μm。进一步的，所述桥芯片的数量可以为一个或者多个，每个凹槽中可以埋入一个桥芯片，也可以埋入多个桥芯片。
使用真空压膜技术将所述硅基101和所述桥芯片301间的空隙用干膜材料106填满，并将表面制作平整。之后利用光刻技术在所述桥芯片301焊盘和所述背面第一层重布线105的焊盘开口，开口的宽度和深度在1μm以上，如图7所示。其中，所述干膜材料106为包括树脂类和聚酰亚胺类在内的聚合物材质。
如图8所示，在开口处制作背面第二层重布线107，利用倒装焊技术将高密度I/O异质芯片304和高密度I/O异质芯片305通过微凸点306与所述背面第二层重布线107露出的焊盘焊接。在本实施例一中，焊接了两个高密度I/O异质芯片（高密度I/O异质芯片304和高密度I/O异质芯片305），在实际操作时可根据实际情况需要焊接更多芯片。
如图9，通过塑封材料108塑封所述硅基101背面，使其完全包裹所述高密度I/O异质芯片304和所述高密度I/O异质芯片305，以提高封装可靠性。所述塑封材料108是包括树脂类和聚酰亚胺类在内的聚合物。
如图10，拆解所述玻璃载板，并清洗干净所述临时键合胶203，使所述截止层102露出；通过刻蚀技术在所述TSV通孔处103开口，露出所述第一层重布线105的焊盘，该焊盘也可称为TSV通孔焊盘109。
如图11，利用再布线技术制作正面重布线110；最后制作阻焊层111和凸点112，切成单颗封装芯片，完成封装，如图12所示。
实施例二
本发明提供了一种三维***级集成硅基扇出型封装结构，其结构如图12所示，包括硅基101，所述硅基101的第一面沉积有截止层102。优选的，所述截止层102的材质为无机材料的一种或多种，或金属材料的一种或多种，其厚度不小于0.1μm；其中，所述无机材料包括SiO2、SiC和SiN；所述金属材料包括Al、Cu、Ni、Sn和Au。
所述硅基101的第二面刻蚀有TSV通孔和凹槽，所述凹槽大小根据埋入芯片尺寸决定，其深度至少为10μm；所述TSV通孔深度与所述凹槽一致，所述凹槽和所述TSV通孔数量均在一个以上。所述TSV通孔中制作有背面第一层重布线105，所述凹槽中埋有桥芯片301。其中，所述桥芯片301通过粘合胶303埋入凹槽，所述凹槽中可以埋入一颗或多颗桥芯片；所述桥芯片301的焊盘朝外，埋入桥芯片301后所述桥芯片301形成的高度与所述硅基101平面的高度误差不超过5μm。
具体的，所述硅基101和所述桥芯片301之间填充有干膜材料106；所述干膜材料106为包括树脂类和聚酰亚胺类在内的聚合物材质。
所述背面第一层重布线105依次通过背面第二层重布线107和微凸点306与高密度I/O异质芯片焊接。请继续参阅图1，在本实施例一中，高密度I/O异质芯片有两个，分别为高密度I/O异质芯片304和高密度I/O异质芯片305，在实际操作时可根据实际情况需要焊接更多芯片。
所述硅基101的第二面塑封有塑封材料108，所述塑封材料108包裹所述第二层重布线107、所述微凸点306和所述高密度I/O异质芯片，以提高封装可靠性。所述塑封材料108是包括树脂类和聚酰亚胺类在内的聚合物。
所述硅基101的第一面依次形成有正面重布线110、阻焊层111和凸点112，所述正面重布线110与所述背面第一层重布线105连接。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。

Claims (9)

1.一种三维***级集成硅基扇出型封装方法，其特征在于，包括：
提供硅基，将其与玻璃载板键合；
在所述硅基背面刻蚀出凹槽和TSV通孔，在TSV通孔中制作背面第一层重布线，在凹槽中埋入桥芯片；
用干膜材料填充所述硅基和所述桥芯片间的空隙；
在所述桥芯片的焊盘和所述背面第一层重布线的焊盘处开口并制作背面第二层重布线；
将高密度I/O异质芯片通过微凸点与所述背面第二层重布线的焊盘焊接；
塑封所述硅基背面，拆解所述玻璃载板并在所述TSV通孔处开口；
制作正面重布线、阻焊层和凸点，切成单颗封装芯片，完成封装。
2.如权利要求1所述的三维***级集成硅基扇出型封装方法，其特征在于，所述硅基正面沉积有截止层，所述截止层与所述玻璃载板键合。
3.如权利要求2所述的三维***级集成硅基扇出型封装方法，其特征在于，所述玻璃载板包括键合玻璃和形成在所述键合玻璃上的临时键合激光反应层；所述临时键合激光反应层通过临时键合胶与所述截止层键合；其中，
所述键合玻璃的厚度不小于100μm；所述临时键合胶的厚度不小于1μm，所述临时键合激光反应层的厚度不小于0.1μm。
4.如权利要求2所述的三维***级集成硅基扇出型封装方法，其特征在于，所述截止层的材质为无机材料的一种或多种，或金属材料的一种或多种，其厚度不小于0.1μm，
所述无机材料包括SiO2、SiC和SiN；
所述金属材料包括Al、Cu、Ni、Sn和Au。
5.如权利要求1所述的三维***级集成硅基扇出型封装方法，其特征在于，在所述硅基背面刻蚀出凹槽和TSV通孔包括：
通过研磨或刻蚀的方法将所述硅基背面减薄到目标厚度；
使用干法刻蚀在减薄的硅基背面刻蚀凹槽和TSV通孔；其中，
所述凹槽大小根据埋入芯片尺寸决定，其深度至少为10μm；所述TSV通孔深度与所述凹槽一致，所述凹槽和所述TSV通孔数量均在一个以上。
6.如权利要求1所述的三维***级集成硅基扇出型封装方法，其特征在于，所述桥芯片通过粘合胶埋入凹槽，所述凹槽中埋入一颗或多颗桥芯片；所述桥芯片的焊盘朝外，埋入桥芯片后所述桥芯片形成的高度与所述硅基平面的高度误差不超过5μm。
7.如权利要求1所述的三维***级集成硅基扇出型封装方法，其特征在于，所述干膜材料为包括树脂类和聚酰亚胺类在内的聚合物材质。
8.如权利要求1所述的三维***级集成硅基扇出型封装方法，其特征在于，通过塑封材料塑封所述硅基背面，所述塑封材料是包括树脂类和聚酰亚胺类在内的聚合物。
9.一种三维***级集成硅基扇出型封装结构，其特征在于，通过权利要求1-8任一所述的三维***级集成硅基扇出型封装方法制备而成。
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