CN110298202B - Intelligent diagnosis method for hardware backdoor based on time-space characteristics of chip temperature field - Google Patents

Intelligent diagnosis method for hardware backdoor based on time-space characteristics of chip temperature field Download PDF

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CN110298202B
CN110298202B CN201910602131.XA CN201910602131A CN110298202B CN 110298202 B CN110298202 B CN 110298202B CN 201910602131 A CN201910602131 A CN 201910602131A CN 110298202 B CN110298202 B CN 110298202B
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王坚
李雄
杨鍊
李桓
陈哲
郭世泽
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Abstract

The invention discloses a hardware backdoor intelligent diagnosis method based on time-space characteristics of a chip temperature field, which selects steady-state temperature trigger time characteristics of the chip temperature field as the basis of backdoor detection, extracts classification characteristics according to the steady-state temperature trigger time characteristics, and finally performs classification detection on samples by utilizing an SOM autonomous classification network. According to the method, gold sample data is not needed to be used as a classification reference basis, and the threshold of engineering use is lowered. In addition, the temperature difference is mapped into the time difference to amplify the physical difference brought by the back door, so that the influence of process deviation and measurement noise can be weakened to a certain extent, the detection capability is improved, and the implantation position of the back door can be simply judged.

Description

Intelligent diagnosis method for hardware backdoor based on time-space characteristics of chip temperature field
Technical Field
The invention belongs to the technical field of hardware safety, and particularly relates to a hardware backdoor intelligent diagnosis method based on time-space characteristics of a chip temperature field.
Background
The hardware back door can be defined as a malicious logic circuit for realizing malicious behaviors, and the malicious logic circuit can realize the function destruction or reveal internal confidential information under the triggering and activating conditions of characteristics. Since the back door attack designed for the chip hardware is often very harmful and difficult to detect due to certain concealment, the hardware back door problem is considered as a security problem that must be considered as important.
In recent years, a great deal of research is carried out on the detection technology of the hardware backdoor in the industry and academia at home and abroad, and the main detection methods can be summarized into destructive detection and non-destructive detection. Destructive detection technology is used for observing the internal structure of the chip package through destruction, and then back door detection is carried out by utilizing a reverse analysis means. Although the method has a relatively ideal detection result, the detection cost is relatively high, and the chip is irrecoverably damaged, so that the chip can not be used after detection. In non-destructive testing, document [1] monitors key nodes in a circuit by using a self-test module and a boundary scan chain built in a chip in a factory based on a preventive testing technology to form a fixed "signature" as a basis for back-gate testing. Document [2] uses a functional detection technique, i.e. an exhaustive test of all signal outputs of the chip is performed, in order to compare them with standard signal outputs and to determine whether or not the back door is implanted. The two methods have the defects of high production cost, large detection time consumption, huge test workload and the like.
Currently, the detection technology based on analysis of bypass signals is widely researched and used. On the basis of the electromagnetic information detection direction, one method is to divide the surface of the chip into regions and project the high-dimensional bypass signals of the chip to the low dimension by using a projection tracing technology so as to obtain the distribution characteristics of original data, and then perform hardware backdoor detection by characteristic extraction and identification.
Another direction for studying physical field information is back door detection technology based on chip power consumption and heat. Some researchers currently conduct back door testing studies from their caloric profiles. One method is to use the temperature data in the obtained chip temperature chart to carry out 2-DPCA processing, and then use the gold sample data to set the threshold of detection threshold, thus realizing the supervised back door detection. In addition, the obtained temperature heat map is converted into a corresponding power consumption distribution map, appropriate features are selected, and classification is performed by using a classification algorithm of a neural network, so that back door detection is realized. Another method is to use the temperature difference caused by the back door to perform direct judgment and detection, and requires a golden sample as a detection reference, which is easily affected by noise and Process Variation (Process Variation). Yet another approach is to track chip temperature changes for back door detection. The former realizes detection by using a curve fitting method after obtaining a temperature change curve, and the latter tracks temperature change through a Kalman filter, sets some assumed previous conditions and detects by using knowledge of assumed inspection. Both methods take the process deviation into consideration, but have certain preconditions and assumptions, and require a gold sample to provide safety data for comparison and judgment, but in reality, the gold sample with safety guarantee is difficult to obtain, which brings difficulties to engineering practice.
Disclosure of Invention
Aiming at the defects in the prior art, the intelligent diagnosis method for the hardware backdoor based on the time-space characteristics of the chip temperature field provided by the invention solves the problems in the background art.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that: a hardware backdoor intelligent diagnosis method based on chip temperature field time-space characteristics comprises the following steps:
s1, dividing all the integrated circuit samples x to be tested into the same area, so that each integrated circuit sample has a plurality of the same circuit areas (i, j);
s2, starting each circuit region (i, j) to operate under the same environment and operating condition, extracting temperature data of each circuit region (i, j) in a time period from starting to reaching a steady-state temperature, and constructing a steady-state temperature matrix Tx；
S3 according to the steady-state temperature matrix TxDetermining a temperature trigger threshold H for each circuit region (i, j)i,jConstructing a temperature trigger threshold matrix H;
s4, triggering H in threshold matrix H according to temperaturei,jDetermining a trigger time matrix t for each integrated circuit sample xxAnd mathematical features of the integrated circuit sample x
Figure GDA0002791592710000031
S5 mathematical characterization of all IC samples x
Figure GDA0002791592710000032
Carrying out normalization and disorder processing to obtain a training sample sequence and a test sample sequence;
s6, training the SOM neural network through a training sample sequence;
s7, inputting the test sample sequence into the trained SOM neural network to obtain two sample sets, performing statistical analysis on the characteristics in the two sample sets, determining the sample set of the implanted hardware back door, and realizing hardware back door detection.
Further, the steady state temperature in step S2 is that the circuit region (i, j) reaches the steady state t0Average of temperature data over time;
construction of the Steady-State temperature matrix TxThe method comprises the following steps:
a1, let circuit region (i, j) in IC sample x reach steady state t0The temperature data sequence in time is { w }1,w2,...,wsAt steady state temperature
Figure GDA0002791592710000033
Comprises the following steps:
Figure GDA0002791592710000034
wherein s is the total number of temperature data;
a2, constructing a steady-state temperature matrix T of all integrated circuit samples according to the steady-state temperature of each circuit region (i, j) in each integrated circuit sample x;
Figure GDA0002791592710000035
in the formula,
Figure GDA0002791592710000036
i,j＝1,2,...,m，x＝1,2,...,n，
Figure GDA0002791592710000037
the steady-state temperature of a circuit region (i, j) in an integrated circuit sample x is obtained, m is the number of regions in a single row or a single column after the integrated circuit sample is divided, i, j is a coordinate variable corresponding to the number of the circuit region (i, j), and n is the number of the integrated circuit sample.
Further, the step S3 is specifically:
steady state temperature matrix T according to n integrated circuit samplesxDetermining steady state temperatures of the same circuit region (i, j) in different integrated circuit samples x, and determining the minimum steady state temperature
Figure GDA0002791592710000041
As temperature trigger threshold H for all circuit regions (i, j)i,jConstructing a temperature trigger threshold matrix H according to the temperature trigger threshold of each circuit area;
wherein the temperature of the circuit region (i, j) triggers the threshold Hi,jComprises the following steps:
Figure GDA0002791592710000042
in the formula, min {. cndot } is the minimum value;
the temperature trigger threshold matrix H is:
Figure GDA0002791592710000043
further, the step S4 is specifically:
s41, setting the temperature value of the integrated circuit sample x at any time k in the temperature data change process of the circuit area (i, j) as temk；
S42, temperature value temkA first arrival of the temperature trigger threshold H at the circuit region (i, j)i,jThe time k is taken as the trigger time of the integrated circuit sample x in the circuit region (i, j)
Figure GDA0002791592710000044
S43, obtaining a temperature trigger time matrix t of each integrated circuit sample according to the trigger time of each integrated circuit sample in each circuit areax；
Wherein the temperature trigger time matrix txComprises the following steps:
Figure GDA0002791592710000051
s44, triggering time matrix t of integrated circuit sample xxMinimum time to trigger
Figure GDA0002791592710000052
As a mathematical characteristic of the integrated circuit sample x;
wherein the mathematical characteristics
Figure GDA0002791592710000053
Comprises the following steps:
Figure GDA0002791592710000054
correspondingly, n features corresponding to n integrated circuit samples are obtained as
Figure GDA0002791592710000055
Further, the step S5 is specifically:
mathematical characterization of all integrated circuit samples
Figure GDA0002791592710000056
Normalized to the interval [0, 1] by the standard]In the interior, normalized mathematical characteristics are obtained
Figure GDA0002791592710000057
Randomly scrambling the original sequence of the n mathematical characteristics, and randomly extracting A% of the scrambled n mathematical characteristicsThe mathematical characteristics of the integrated circuit sample are used as a training sample sequence of the SOM neural network, and the mathematical characteristics of the rest 1-A% of the integrated circuit sample are used as a test sample sequence.
Further, the step S6 is specifically:
s61, initializing the SOM neural network;
s62, recording the mathematical characteristics of each integrated circuit sample X as an input vector X, and normalizing the input vector to obtain a normalized input vector
Figure GDA0002791592710000058
S63, inputting the current vector
Figure GDA00027915927100000511
Inputting the vector into the initialized SOM neural network, and calculating the input vector
Figure GDA0002791592710000059
And the weight vector of each output layer neuron in the SOM neural network
Figure GDA00027915927100000510
Similarity of (2)J；
S64, according to similarity SJDetermining a winning output layer neuron corresponding to the input vector;
s65, adjusting the corresponding output value and weight vector weight of the neuron of the winning output layer;
s66, judging whether the Konen learning rate alpha of the adjusted SOM neural network is less than 0;
if so, finishing the training of the SOM neural network;
if not, the process returns to step S63 to use the next input vector
Figure GDA0002791592710000061
The weight vectors for the winning output layer neurons are adjusted.
Further, the input vector after the normalization processing in step S62
Figure GDA0002791592710000062
Comprises the following steps:
Figure GDA0002791592710000063
in the formula, | | | | | is the modulo operation of the vector;
similarity degree S in the step S63JThe calculation formula of (2) is as follows:
Figure GDA0002791592710000064
in the formula,
Figure GDA0002791592710000065
normalizing the weight vector of the output layer neuron in the initialized SOM neural network;
in step S64, the method for determining the winning output layer neuron corresponding to the input vector specifically includes:
when a certain output layer neuron J*When the judgment formula of the winning output layer neuron is satisfied, judging the output layer neuron to be the winning output layer neuron J*；
Wherein, the winning output layer neuron decision formula is:
Figure GDA0002791592710000066
in the formula, S1,S2,S3,...,SlFor each output layer neuron and current input vector in SOM neural network
Figure GDA0002791592710000067
L is the number of output layer neurons of the SOM neural network;
Figure GDA0002791592710000068
WJ*as winning output layer neuron J*T is the transpose operator;
in step S65, the method for adjusting the corresponding output value of the winning output layer neuron includes:
inputting the current vector
Figure GDA0002791592710000069
Corresponding winning output layer neuron J*The output value of (1) is set as 1, and the output values of the neurons of the rest output layers are set as 0;
for winning output layer neuron J*When the weight vector of the output layer neuron is adjusted, the weight vector of the other output layer neurons is unchanged;
wherein, winning output layer neuron J*The weight vector weight value adjustment formula is as follows:
Figure GDA0002791592710000071
in the formula, WJ*(t +1) is winning output layer neuron J*The adjusted weight vector weight;
Figure GDA0002791592710000072
as winning output layer neuron J*Normalizing the weight vector before adjustment to obtain a normalized value;
ΔWJ*the amount of change in the adjustment when the weight vector is adjusted, i.e. the weight vector
Figure GDA0002791592710000073
Alpha is the Konenon learning rate set by the SOM neural network;
Figure GDA0002791592710000074
normalized values for the weight vector of winning output layer neurons.
Further, the statistical analysis is performed on the mathematical features in the two sample sets in step S7, and the method for determining the set of the implanted hardware backdoor specifically includes:
respectively determining mathematical feature sets corresponding to the two sample sets, calculating the time distribution range and mathematical expectation of the two mathematical feature sets, and judging that the sample set corresponding to the mathematical feature set is a set implanted with a hardware backdoor when the time distribution range and the mathematical expectation of one mathematical feature set relative to the other mathematical feature set are shifted to the left;
set middle mathematical feature t to be implanted with hardware backdoorminTaking out and according to the mathematical characteristic tminAnd the corresponding circuit area (i, j) is judged as the hardware back door implantation position of the circuit integrated sample, so that the hardware back door detection is realized.
The invention has the beneficial effects that: the hardware back door intelligent diagnosis method based on the time-space characteristics of the chip temperature field selects the steady-state temperature triggering time characteristics of the chip temperature field as the basis of back door detection, extracts the classification characteristics according to the steady-state temperature triggering time characteristics, and finally performs classification detection on samples by utilizing an SOM autonomous classification network. According to the method, gold sample data is not needed to be used as a classification reference basis, and the threshold of engineering use is lowered. In addition, the temperature difference is mapped into the time difference to amplify the physical difference brought by the back door, so that the influence of process deviation and measurement noise can be weakened to a certain extent, the detection capability is improved, and the implantation position of the back door can be simply judged.
Drawings
Fig. 1 is a flowchart of a hardware back door intelligent diagnosis method based on a chip temperature field time-space characteristic provided by the invention.
FIG. 2 is a flow chart of a method for determining a mathematical characteristic of a sample of an integrated circuit according to the present invention.
FIG. 3 is a flow chart of a SOM neural network training method of the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
As shown in fig. 1, a hardware back door intelligent diagnosis method based on chip temperature field time-space characteristics includes the following steps:
s1, dividing all the integrated circuit samples x to be tested into the same area, so that each integrated circuit sample has a plurality of the same circuit areas (i, j);
s2, starting each circuit region (i, j) to operate under the same environment and operating condition, extracting temperature data of each circuit region (i, j) in a time period from starting to reaching a steady-state temperature, and constructing a steady-state temperature matrix Tx；
S3 according to the steady-state temperature matrix TxDetermining a temperature trigger threshold H for each circuit region (i, j)i,jConstructing a temperature trigger threshold matrix H;
s4, triggering H in threshold matrix H according to temperaturei,jDetermining a trigger time matrix t for each integrated circuit sample xxAnd mathematical features of the integrated circuit sample x
Figure GDA0002791592710000081
S5 mathematical characterization of all IC samples x
Figure GDA0002791592710000082
Carrying out normalization and disorder processing to obtain a training sample sequence and a test sample sequence;
s6, training the SOM neural network through a training sample sequence;
s7, inputting the test sample sequence into the trained SOM neural network to obtain two sample sets, performing statistical analysis on the characteristics in the two sample sets, determining the sample set of the implanted hardware back door, and realizing hardware back door detection.
In step S1, each ic sample is divided into m × m regions, and in step S2, due to the influence of environmental noise in the actual test, the temperature of each region does not keep an ideal fixed value after reaching the steady state, but rather one region jumps up and down within the noise range, so that the noise influence is eliminated by averaging to obtain the steady state temperature, which is the time from the start of the circuit region (i, j) to the steady state t0Average of temperature data over time.
Thus, a steady state temperature matrix T is constructedxThe method comprises the following steps:
a1, let circuit region (i, j) in IC sample x reach steady state t0The temperature data sequence in time is { w }1,w2,...,wsAt steady state temperature
Figure GDA0002791592710000091
Comprises the following steps:
Figure GDA0002791592710000092
wherein s is the total number of temperature data;
a2, constructing a steady-state temperature matrix T of all integrated circuit samples according to the steady-state temperature of each circuit region (i, j) in each integrated circuit sample x;
Figure GDA0002791592710000093
in the formula,
Figure GDA0002791592710000094
i,j＝1,2,...,m，x＝1,2,...,n，
Figure GDA0002791592710000095
is the steady state temperature of the circuit region (i, j) in the integrated circuit sample x, and m is the coordinate point in the region of a single row or column after the integrated circuit sample is dividedThe total number, i, j, is the coordinate variable corresponding to the circuit region (i, j) number, and n is the total number of integrated circuit samples.
The step S3 is specifically:
steady state temperature matrix T according to n integrated circuit samplesxDetermining steady state temperatures of the same circuit region (i, j) in different integrated circuit samples x, and determining the minimum steady state temperature
Figure GDA0002791592710000101
As temperature trigger threshold H for all circuit regions (i, j)i,jConstructing a temperature trigger threshold matrix H according to the temperature trigger threshold of each circuit area;
wherein the temperature of the circuit region (i, j) triggers the threshold Hi,jComprises the following steps:
Figure GDA0002791592710000102
in the formula, min {. cndot } is the minimum value;
all H isi,jMapping and combining the circuit areas (i, j) into a temperature trigger threshold matrix H facing all samples according to the corresponding circuit areas (i, j), wherein the matrix H comprises the following components:
Figure GDA0002791592710000103
as shown in fig. 2, step S4 specifically includes:
s41, setting the temperature value of the integrated circuit sample x at any time k in the temperature data change process of the circuit area (i, j) as temk；
S42, temperature value temkA first arrival of the temperature trigger threshold H at the circuit region (i, j)i,jThe time k is taken as the trigger time of the integrated circuit sample x in the circuit region (i, j)
Figure GDA0002791592710000104
I.e. when the temperature value temkWhen the following formula is satisfied, the circuit is set at the time kThe triggering time of region (i, j);
Figure GDA0002791592710000105
in the formula, z is a time variation value and is used to describe the time before the time k and the time after the time k.
S43, obtaining a temperature trigger time matrix t of each integrated circuit sample according to the trigger time of each integrated circuit sample in each circuit areax；
The same analysis and processing as described above is performed on all regions of the integrated circuit sample x to obtain m x m trigger time values
Figure GDA0002791592710000111
Finally, obtaining a trigger time matrix t of the integrated circuit sample xxComprises the following steps:
Figure GDA0002791592710000112
according to the above processing procedure, n trigger time matrices t can be obtained1、t2、...、tn。
For a chip implanted with a hardware back door, since the hardware back door is an unnecessary malicious logic circuit which is unauthorized to be added by an intruder, the chip will generate an unnecessary power consumption relative to a chip without the back door during the operation process of the chip. These excessive power consumptions will affect the temperature characteristics of the original chip. In the method, the temperature influence brought by the hardware back door can lead the back door chip to trigger the set steady-state temperature trigger threshold value in advance, and lead the steady-state temperature trigger time value matrix t of the back door chip to triggerxIn the time value of each area position
Figure GDA0002791592710000113
The characteristic of being reduced in size compared with the same zone without the rear door, where the influence of the zone in which the rear door is located (assumed to be (i0, j0)) is the greatest, is its time value
Figure GDA0002791592710000114
Will also be the entire back door chip matrix txThe minimum value is extracted as the characteristic of the chip, so that the influence of the hardware backdoor can be well characterized. Therefore, the method for determining the mathematical characteristics of the sample specifically comprises the following steps:
s44, triggering time matrix t of integrated circuit sample xxMinimum time to trigger
Figure GDA0002791592710000115
As a mathematical characteristic of the integrated circuit sample x;
wherein the mathematical characteristics
Figure GDA0002791592710000116
Comprises the following steps:
Figure GDA0002791592710000117
correspondingly, n features corresponding to n integrated circuit samples are obtained as
Figure GDA0002791592710000118
The step S5 is specifically:
mathematical characterization of all integrated circuit samples
Figure GDA0002791592710000119
Normalized to the interval [0, 1] by the standard]In the interior, normalized mathematical characteristics are obtained
Figure GDA00027915927100001110
Randomly scrambling the original sequence of the n mathematical characteristics, randomly extracting A% of the mathematical characteristics of the integrated circuit samples from the n scrambled mathematical characteristics as a training sample sequence of the SOM neural network, and taking the rest 1-A% of the mathematical characteristics of the integrated circuit samples as a test sample sequence.
The purpose of standard normalization processing is to enable data in different ranges to be compared under a reference system and prepare for a subsequent classification algorithm; the purpose of the disorder processing is to disturb recombination and facilitate the selection of subsequent training sample sequences and test sample sequences.
Wherein:
Figure GDA0002791592710000121
wherein x is 1, 2.., n,
Figure GDA0002791592710000122
as shown in fig. 3, step S6 specifically includes:
s61, initializing the SOM neural network;
firstly, the number l of neurons in an output layer and the Kononen learning rate alpha are set, a competitive learning network is constructed, and then the network training times, the weight value of a network topological structure and the deviation are initialized. After the output layer neurons are initialized and set with weights, each output neuron has a weight vector W corresponding to the output neuronJ(J ═ 1, 2.. times, l), then the weight vectors W for all output neurons are scaledJCarrying out normalization treatment as shown in the following formula;
Figure GDA0002791592710000123
wherein J ═ 1, 2.., l;
s62, recording the mathematical characteristics of each integrated circuit sample X as an input vector X, and normalizing the input vector to obtain a normalized input vector
Figure GDA0002791592710000124
Wherein the normalized input vector
Figure GDA0002791592710000125
Comprises the following steps:
Figure GDA0002791592710000126
in the formula, | | | | | is the modulo operation of the vector;
s63, inputting the current vector
Figure GDA0002791592710000131
Inputting the vector into the initialized SOM neural network, and calculating the input vector
Figure GDA0002791592710000132
And the weight vector of each output layer neuron in the SOM neural network
Figure GDA0002791592710000133
Similarity of (2)J；
Wherein the similarity SJThe calculation formula of (2) is as follows:
Figure GDA0002791592710000134
in the formula,
Figure GDA0002791592710000135
normalizing the weight vector of the output layer neuron in the initialized SOM neural network;
s64, according to similarity SJDetermining a winning output layer neuron corresponding to the input vector;
the method for determining the winning output layer neuron corresponding to the input vector specifically comprises the following steps:
when a certain output layer neuron J*When the judgment formula of the winning output layer neuron is satisfied, judging the output layer neuron as the winning output layer neuron;
wherein, the winning output layer neuron decision formula is:
Figure GDA0002791592710000136
in the formula, S1,S2,S3,...,SlFor each output layer neuron and current input vector in SOM neural network
Figure GDA0002791592710000137
L is the number of output layer neurons of the SOM neural network;
Figure GDA0002791592710000138
WJ*as winning output layer neuron J*T is the transpose operator, and
Figure GDA0002791592710000139
s65, adjusting the corresponding output value and weight vector weight of the neuron of the winning output layer;
the method for adjusting the corresponding output value of the neuron of the winning output layer comprises the following steps:
inputting the current vector
Figure GDA00027915927100001310
Corresponding winning output layer neuron J*Is set to 1, and the remaining output layer neuron output values are set to 0, even though the output O of the remaining output layer neuron J is set to 1JSatisfies the following conditions:
Figure GDA00027915927100001311
for winning output layer neuron J*When the weight vector of the output layer neuron is adjusted, the weight vector of the other output layer neurons is unchanged;
wherein, winning output layer neuron J*The weight vector weight value adjustment formula is as follows:
Figure GDA0002791592710000141
in the formula, WJ*(t +1) is winning output layer neuron J*The adjusted weight vector weight;
Figure GDA0002791592710000142
as winning output layer neuron J*Normalizing the weight vector before adjustment to obtain a normalized value;
ΔWJ*the amount of change in the adjustment when the weight vector is adjusted, i.e. the weight vector
Figure GDA0002791592710000143
Alpha is the Konenon learning rate set by the SOM neural network;
Figure GDA0002791592710000144
normalized values for the weight vector of winning output layer neurons.
At this time, the weight vector weights of the remaining output layer neurons J are:
Figure GDA0002791592710000145
s66, judging whether the Konen learning rate alpha of the adjusted SOM neural network is less than 0;
if so, finishing the training of the SOM neural network;
if not, the process returns to step S63 to use the next input vector
Figure GDA0002791592710000146
The weight vectors for the winning output layer neurons are adjusted.
In the step S7, the method for statistically analyzing the mathematical features in the two sample sets to determine the set of the implanted hardware backdoor specifically includes:
respectively determining mathematical feature sets corresponding to the two sample sets, calculating the time distribution range and mathematical expectation of the two mathematical feature sets, and judging that the sample set corresponding to the mathematical feature set is a set implanted with a hardware backdoor when the time distribution range and the mathematical expectation of one mathematical feature set relative to the other mathematical feature set are shifted to the left;
set middle mathematical feature t to be implanted with hardware backdoorminTaking out and according to the mathematical characteristic tminAnd the corresponding circuit area (i, j) is judged as the hardware back door implantation position of the circuit integrated sample, so that the hardware back door detection is realized.
Assuming that the two obtained sample sets are cluster1 and cluster2 respectively, statistical analysis is performed on mathematical characteristics of the integrated circuit samples in the sets cluster1 and cluster2 respectively, and which set of the two sets is a set attacked by the backdoor is judged. Assuming that there are n1 samples in the set cluster1, the corresponding mathematical feature set is
Figure GDA0002791592710000151
There are n2 samples in cluster2, and the mathematical feature set is
Figure GDA0002791592710000152
According to the analysis of the influence brought by the hardware backdoor, the mathematical characteristics of the chip with the hardware backdoor are smaller than those of the chip without the hardware backdoor, so that the mathematical expectation can be judged by analyzing the distribution diagrams and mathematical expectations of the cluster1 and cluster 2. If the time distribution range of the set Cluster1 (or Cluster2) and the mathematics expect that the relative Cluster2 (or Cluster1) is shifted to the left, namely is relatively small, the set Cluster1 (or Cluster2) is judged to be a set (marked as Cluster _ trojan) with a hardware backdoor implant;
taking out the mathematical characteristics of the integrated circuit samples in the set Cluster _ troman, and searching each integrated circuit sample and the mathematical characteristics t thereofminThe corresponding circuit area (i, j) is judged as the suspected hardware of the corresponding integrated circuit sample according to the characteristic that the back gate implantation influences the steady-state temperature trigger time value of the chipAnd the back door is implanted into a position, so that hardware back door detection is realized.
In one embodiment of the invention, a validation experiment of the method of the invention is provided:
and selecting a Benchmark on the Trust-hub website for verification. Logic synthesis, layout and wiring and power consumption simulation are carried out on the Design by using digital IC Design tools Design Compiler, IC Compiler and PTPX, and layout information and power consumption information of the Design are obtained. We divide the design layout into 16 x 16 regions (i.e., 256 Block blocks) on average, each Block being equal in area. For a back door insertion form, the influence of back door power consumption is directly considered, additional power consumption brought by a back door is added into the total power consumption of a selected back door implantation Block area, and a thermal simulation tool Hotspot is used for performing thermal simulation on a chip so as to obtain temperature change information of each Block area of the chip. The thermal simulation process considers the process variation PV (process variation) effects of 20% and 40%, respectively, and adds Gaussian noise to simulate the actual measurement noise. And finally, processing the obtained data, and inputting the processed data into the SOM autonomous classification network for classification detection. Some specific experimental condition information for this example is shown in tables 1,2, and 3.
TABLE 1 example parameter information Table
Figure GDA0002791592710000161
Note: LTPD: local back gate power density, LTDP ═ back gate power)/(area of area where back gate is located);
TABLE 2 table of condition information for verification experiment
Figure GDA0002791592710000162
TABLE 3 Hotspot simulation parameter settings
Figure GDA0002791592710000163
In the experiment, we performed experiments in both cases of 20% PV and 40% PV, respectively, using 1000 chip samples each time, 500 of which were no back door chips and 500 were chips with back doors implanted at the same positions. Then, 70% (i.e., a ═ 70) of the samples were randomly selected as training samples, and 30% of the samples were selected as the final samples to be tested. Finally, the results are shown in Table 4.
TABLE 4 test results
Figure GDA0002791592710000164
Figure GDA0002791592710000171
The invention has the beneficial effects that:
the hardware back door intelligent diagnosis method based on the time-space characteristics of the chip temperature field selects the steady-state temperature triggering time characteristics of the chip temperature field as the basis of back door detection, extracts the classification characteristics according to the steady-state temperature triggering time characteristics, and finally performs classification detection on samples by utilizing an SOM autonomous classification network. According to the method, gold sample data is not needed to be used as a classification reference basis, and the threshold of engineering use is lowered. In addition, the temperature difference is mapped into the time difference to amplify the physical difference brought by the back door, so that the influence of process deviation and measurement noise can be weakened to a certain extent, the detection capability is improved, and the implantation position of the back door can be simply judged.

Claims (8)

1. A hardware backdoor intelligent diagnosis method based on chip temperature field time-space characteristics is characterized by comprising the following steps:
s1, dividing all the integrated circuit samples x to be tested into the same area, so that each integrated circuit sample has a plurality of the same circuit areas (i, j);
s2, starting each circuit region (i, j) to operate under the same environment and operation condition, extracting each circuit region (i, j) (S)i, j) from start-up to steady-state temperature
Figure FDA0002829831590000011
Temperature data over a period of time and constructing a steady state temperature matrix Tx；
S3 according to the steady-state temperature matrix TxDetermining a temperature trigger threshold H for each circuit region (i, j)i,jConstructing a temperature trigger threshold matrix H;
s4, triggering H in threshold matrix H according to temperaturei,jDetermining a trigger time matrix t for each integrated circuit sample xxAnd mathematical features of the integrated circuit sample x
Figure FDA0002829831590000012
S5 mathematical characterization of all IC samples x
Figure FDA0002829831590000013
Carrying out normalization and disorder processing to obtain a training sample sequence and a test sample sequence;
s6, training the SOM neural network through a training sample sequence;
s7, inputting the test sample sequence into the trained SOM neural network to obtain two sample sets, performing statistical analysis on the characteristics in the two sample sets, determining the sample set of the implanted hardware back door, and realizing hardware back door detection;
wherein,
Figure FDA0002829831590000014
Figure FDA0002829831590000015
the steady-state temperature of the circuit region (i, j) in the integrated circuit sample x, m is the total number of coordinate points in the region of a single row or column after the integrated circuit sample is divided, i, j is the coordinate variable of the corresponding circuit region (i, j), and n is the total number of the integrated circuit samples.
2. The intelligent diagnosis method for hardware back door based on chip temperature field time-space characteristic as claimed in claim 1, wherein the steady state temperature in step S2 is from start-up to steady state t for circuit region (i, j)0Average of temperature data over time;
construction of the Steady-State temperature matrix TxThe method comprises the following steps:
a1, let circuit region (i, j) in IC sample x reach steady state t0The temperature data sequence in time is { w }1,w2,...,wsAt steady state temperature
Figure FDA0002829831590000021
Comprises the following steps:
Figure FDA0002829831590000022
wherein s is the total number of temperature data;
a2, constructing a steady-state temperature matrix T of all integrated circuit samples according to the steady-state temperature of each circuit region (i, j) in each integrated circuit sample x;
Figure FDA0002829831590000023
3. the intelligent diagnosis method for the hardware backdoor based on the chip temperature field time-space characteristic as claimed in claim 2, wherein the step S3 specifically comprises:
steady state temperature matrix T according to n integrated circuit samplesxDetermining steady state temperatures of the same circuit region (i, j) in different integrated circuit samples x, and determining the minimum steady state temperature
Figure FDA0002829831590000024
As temperature trigger threshold H for all circuit regions (i, j)i,jAnd triggering the threshold according to the temperature of each circuit regionConstructing a temperature trigger threshold matrix H;
wherein the temperature of the circuit region (i, j) triggers the threshold Hi,jComprises the following steps:
Figure FDA0002829831590000025
in the formula, min {. cndot } is the minimum value;
the temperature trigger threshold matrix H is:
Figure FDA0002829831590000026
4. the intelligent diagnosis method for the hardware backdoor based on the time-space characteristic of the chip temperature field according to claim 3, wherein the step S4 is specifically as follows:
s41, setting the temperature value of the integrated circuit sample x at any time k in the temperature data change process of the circuit area (i, j) as temk；
S42, temperature value temkA first arrival of the temperature trigger threshold H at the circuit region (i, j)i,jThe time k is taken as the trigger time of the integrated circuit sample x in the circuit region (i, j)
Figure FDA0002829831590000031
S43, obtaining a temperature trigger time matrix t of each integrated circuit sample according to the trigger time of each integrated circuit sample in each circuit areax；
Wherein the temperature trigger time matrix txComprises the following steps:
Figure FDA0002829831590000032
s44, triggering time matrix t of integrated circuit sample xxMinimum time to trigger
Figure FDA0002829831590000033
As a mathematical characteristic of the integrated circuit sample x;
wherein the mathematical characteristics
Figure FDA0002829831590000034
Comprises the following steps:
Figure FDA0002829831590000035
correspondingly, n features corresponding to n integrated circuit samples are obtained as
Figure FDA0002829831590000036
5. The intelligent diagnosis method for the hardware backdoor based on the time-space characteristic of the chip temperature field according to claim 4, wherein the step S5 is specifically as follows:
mathematical characterization of all integrated circuit samples
Figure FDA0002829831590000037
Normalized to the interval [0, 1] by the standard]In the interior, normalized mathematical characteristics are obtained
Figure FDA0002829831590000038
Randomly scrambling the original sequence of the n mathematical characteristics, randomly extracting A% of the mathematical characteristics of the integrated circuit samples from the n scrambled mathematical characteristics as a training sample sequence of the SOM neural network, and taking the rest 1-A% of the mathematical characteristics of the integrated circuit samples as a test sample sequence.
6. The intelligent diagnosis method for the hardware backdoor based on the time-space characteristic of the chip temperature field according to claim 5, wherein the step S6 is specifically as follows:
s61, initializing the SOM neural network;
s62, recording the mathematical characteristics of each integrated circuit sample X as an input vector X, and normalizing the input vector to obtain a normalized input vector
Figure FDA0002829831590000041
S63, inputting the current vector
Figure FDA0002829831590000042
Inputting the vector into the initialized SOM neural network, and calculating the input vector
Figure FDA0002829831590000043
And the weight vector of each output layer neuron in the SOM neural network
Figure FDA0002829831590000044
The similarity of (2);
s64, according to similarity SJDetermining a winning output layer neuron corresponding to the input vector;
s65, adjusting the corresponding output value and weight vector weight of the neuron of the winning output layer;
s66, judging whether the Konen learning rate alpha of the adjusted SOM neural network is less than 0;
if so, finishing the training of the SOM neural network;
if not, the process returns to step S63 to use the next input vector
Figure FDA0002829831590000045
The weight vectors for the winning output layer neurons are adjusted.
7. The intelligent diagnosis method for hardware back door based on chip temperature field time-space characteristics as claimed in claim 6,
the normalized input vector in step S62
Figure FDA0002829831590000046
Comprises the following steps:
Figure FDA0002829831590000047
in the formula, | | | | | is the modulo operation of the vector;
similarity degree S in the step S63JThe calculation formula of (2) is as follows:
Figure FDA0002829831590000048
in the formula,
Figure FDA0002829831590000049
normalizing the weight vector of the output layer neuron in the initialized SOM neural network;
in step S64, the method for determining the winning output layer neuron corresponding to the input vector specifically includes:
when a certain output layer neuron J*When the judgment formula of the winning output layer neuron is satisfied, judging the output layer neuron to be the winning output layer neuron J*；
Wherein, the winning output layer neuron decision formula is:
Figure FDA0002829831590000051
in the formula, S1,S2,S3,...,SlFor each output layer neuron and current input vector in SOM neural network
Figure FDA0002829831590000052
L is the number of output layer neurons of the SOM neural network;
Figure FDA0002829831590000053
Figure FDA0002829831590000054
as winning output layer neuron J*T is the transpose operator;
in step S65, the method for adjusting the corresponding output value of the winning output layer neuron includes:
inputting the current vector
Figure FDA0002829831590000055
Corresponding winning output layer neuron J*The output value of (1) is set as 1, and the output values of the neurons of the rest output layers are set as 0;
for winning output layer neuron J*When the weight vector of the output layer neuron is adjusted, the weight vector of the other output layer neurons is unchanged;
wherein, winning output layer neuron J*The weight vector weight value adjustment formula is as follows:
Figure FDA0002829831590000056
in the formula,
Figure FDA00028298315900000511
as winning output layer neuron J*The adjusted weight vector weight;
Figure FDA0002829831590000057
as winning output layer neuron J*Normalizing the weight vector before adjustment to obtain a normalized value;
Figure FDA0002829831590000058
the amount of change in the adjustment when the weight vector is adjusted, i.e. the weight vector
Figure FDA0002829831590000059
Alpha is the Konenon learning rate set by the SOM neural network;
Figure FDA00028298315900000510
normalized values for the weight vector of winning output layer neurons.
8. The intelligent diagnosis method for hardware back-door based on chip temperature field time-space feature of claim 7, wherein the statistical analysis of the mathematical features in the two sample sets in step S7, and the method for determining the set of implanted hardware back-door is specifically:
respectively determining mathematical feature sets corresponding to the two sample sets, calculating the time distribution range and mathematical expectation of the two mathematical feature sets, and judging that the sample set corresponding to the mathematical feature set is a set implanted with a hardware backdoor when the time distribution range and the mathematical expectation of one mathematical feature set relative to the other mathematical feature set are shifted to the left;
set middle mathematical feature t to be implanted with hardware backdoorminTaking out and according to the mathematical characteristic tminAnd the corresponding circuit area (i, j) is judged as the hardware back door implantation position of the circuit integrated sample, so that the hardware back door detection is realized.
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